CN110197993A - The VCSEL chip and its manufacturing method of high combined efficiency - Google Patents
The VCSEL chip and its manufacturing method of high combined efficiency Download PDFInfo
- Publication number
- CN110197993A CN110197993A CN201910523156.0A CN201910523156A CN110197993A CN 110197993 A CN110197993 A CN 110197993A CN 201910523156 A CN201910523156 A CN 201910523156A CN 110197993 A CN110197993 A CN 110197993A
- Authority
- CN
- China
- Prior art keywords
- dbr
- layer
- quantum well
- gaas
- vcsel chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 64
- 238000005036 potential barrier Methods 0.000 claims abstract description 34
- 230000012010 growth Effects 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 229910004205 SiNX Inorganic materials 0.000 claims abstract description 16
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 15
- 239000002131 composite material Substances 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 105
- 230000003647 oxidation Effects 0.000 claims description 25
- 238000007254 oxidation reaction Methods 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 22
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 13
- 239000011241 protective layer Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 230000008020 evaporation Effects 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000000465 moulding Methods 0.000 claims description 3
- 230000005855 radiation Effects 0.000 abstract description 7
- 230000005284 excitation Effects 0.000 abstract description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 20
- 239000004065 semiconductor Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000002994 raw material Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 230000000280 vitalizing effect Effects 0.000 description 2
- 241000931526 Acer campestre Species 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18361—Structure of the reflectors, e.g. hybrid mirrors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/185—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL]
- H01S5/187—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL] using Bragg reflection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/34313—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer having only As as V-compound, e.g. AlGaAs, InGaAs
- H01S5/3432—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer having only As as V-compound, e.g. AlGaAs, InGaAs the whole junction comprising only (AI)GaAs
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
Abstract
The present invention relates to laser chip technical fields, more particularly to the VCSEL chip and its manufacturing method of high combined efficiency, VCSEL chip includes substrate, epitaxial layer and N-contact, epitaxial layer includes N-DBR, Quantum Well, oxide layer and P-DBR, P-DBR, oxide layer, Quantum Well are etched to the surface N-DBR and form table top, Quantum Well includes multipair Quantum Well composite layer, and Quantum Well composite layer includes the Al of overlapping growthxGaAs potential barrier, InGaAs potential well and AlxGaAs potential barrier, central area, intermediate region and fringe region are divided on P-DBR, central area is light hole, P-DBR is upper to have the first SiNx layer in the growth of central area corresponding position, P-DBR is upper to be vapor-deposited with P-contact in intermediate region corresponding position, and P-DBR is upper to have the second SiNx layer in the growth of fringe region corresponding position.Potential barrier forbidden bandwidth with higher in Quantum Well in VCSEL chip of the invention, is easy to reach Lattice Matching, so that more electronics are concentrated and are strapped in Quantum Well, increases excitation probability, combined efficiency is improved, to reach the stimulated radiation of higher efficiency.
Description
Technical field
The present invention relates to laser chip technical field more particularly to the VCSEL chips and its manufacturing method of high combined efficiency.
Background technique
Vertical cavity surface emitting laser (Vertical Cavity Surface Emitting Laser) chip, also known as
VCSEL chip or vertical cavity surface emitting laser (VCSEL) chip are the Laser emission chips based on gallium arsenide semiconductor material,
Its laser is projected perpendicular to top surface, and with the general individual chips processing procedure with incision, laser is had by the edge-emitting laser that edge projects
Institute is different.VCSEL chip has small in size, round output facula, single longitudinal mode output, threshold current small, cheap, easy of integration
The advantages that for large area array, is widely applied and the fields such as optic communication, light network, optical storage.
One laser resonator is that a chip active reaction area is parallel to by two sides distributing Bragg reflector (DBR)
Surface, this reaction zone are to be constituted by one to several Quantum Well (MQW), are contained therein laser light belt.The DBR of one plane
It is made of the lens of several layers of high low-refractions of difference.The optical maser wavelength with a thickness of a quarter of every layer of lens, and give
Reflected intensity more than 99%.Long in order to balance the short axle of gain regions in VCSEL, the lens of high reflectance are necessary.
In general VCSEL, higher and lower two lens have plated p-type material and n-type material respectively, form a junction two
Pole pipe.In more complicated structure, p-type and n-type region may be embedded in lens, make more complex semiconductor in reaction zone
It is upper to process the connection for doing circuit, and remove the consume of the electron energy in dbr structure.
A kind of cross-section structure of VCSEL chip in the prior art is with reference to figure as shown in Figure 1, mainly including gallium arsenide substrate
10 and stacked gradually in gallium arsenide substrate 10 N-type DBR 20 (Distributed Bragg Reflection, it is distributed
Bragg mirror), quantum well layer 30, limiting layer 40, p-type DBR 50, gaas contact layer 60 and electrode structure 70, wherein
Limiting layer 40 includes conductive structure 41 and the oxidation structure 42 positioned at 41 two sides of conductive structure, to play convergence electric current, thus shape
At the purpose of excitation laser in Bulk current injection quantum well layer 30；Electrode structure 70 includes first electrode 71 and second electrode 72,
First electrode 71 and second electrode 72 are located at the both ends of gaas contact layer 60, between first electrode 71 and second electrode 72
Region be VCSEL chip output optical zone domain.
VCSEL jumps to conduction band by valence band as a kind of semiconductor laser, the electronics of vitalizing semiconductor, when electronics is by conduction band
When jumping back to valence band, energy is released in the form of luminous energy.And the Quantum Well in the VCSEL chip of the prior art is arranged in pairs or groups mostly
Be InGaAs/GaAs respectively as potential well and potential barrier, determine the allotment of the MQW combined efficiency of same number of stages it is basic only by
The influence of GaAs potential barrier, so quantum well designs combined efficiency in the prior art is lower, stimulated radiation rate is not high always.
Summary of the invention
In view of this, the object of the present invention is to provide the VCSEL chip and its manufacturing method of high combined efficiency, manufacture is obtained
VCSEL chip in Quantum Well in potential barrier forbidden bandwidth with higher, be easy to reach Lattice Matching, so that more electricity
Son, which is concentrated, to be strapped in Quantum Well, and excitation probability is increased, and combined efficiency is improved, to reach the stimulated radiation of higher efficiency.
The present invention solves above-mentioned technical problem by following technological means:
It is an aspect of the invention to provide a kind of VCSEL chip of high combined efficiency, the VCSEL chip includes lining
Bottom, and it is grown in the epitaxial layer and N-contact of the substrate opposite sides respectively, the epitaxial layer is included in the substrate
N-DBR, Quantum Well, oxide layer and the P-DBR that surface is successively grown from bottom to up, the P-DBR, oxide layer, Quantum Well are eclipsed
It carves to the surface N-DBR and forms table top, the Quantum Well includes the multipair Quantum Well composite layer of overlapping growth, and the Quantum Well is compound
Layer includes the Al of overlapping growthxGaAs potential barrier, InGaAs potential well and AlxGaAs potential barrier, on the P-DBR from center to outside according to
Secondary to be divided into central area, intermediate region and fringe region, the central area is light hole, in center on the P-DBR
Corresponding position growth in domain has the first SiNxLayer, it is vapor-deposited with P-contact in intermediate region corresponding position on the P-DBR, it is described
P-DBR is upper to have the 2nd SiN in the growth of fringe region corresponding positionxLayer.
Above-mentioned AlxThe Al component of GaAs potential barrier is adjusted according to VCSEL operating current size: when electric current 5mA, Al group
When point 0.1, electric current 10mA, Al component 0.2, electric current is directly proportional to Al component, and every increase of electric current is twice, and Al component also needs increase one
Times.
Optionally, the Quantum Well includes 2~5 pairs of Quantum Well composite layers of overlapping growth.
Optionally, the Al of each pair of Quantum Well composite layerxGaAs potential barrier with a thickness of 10 angstroms, the thickness of InGaAs potential well
It is 10 angstroms.
Optionally, the table top to the surface P-contact covers matcoveredn, and the section of the protective layer is complete in zigzag
All standing table top and the part covering surface P-contact.
Optionally, the N-DBR includes the reflector element of 40 pairs of stacking growths, and the P-DBR includes 30 pairs of stacking growths
Reflector element, the reflector element be AlGaAs layers.
Optionally, the oxide layer includes non-oxidation panel and the oxidation panel for surrounding the non-oxidation panel, the non-oxidation panel
By Al0.98GaAs Material growth is formed.
It is another aspect of the invention to provide the manufacturing methods of above-mentioned VCSEL chip, comprising the following steps:
Outer layer growth is made, and first grows in substrate surface using AlGaAs the N-DBR of material, then on the surface N-DBR
Grown quantum trap, grows Al in Quantum Well0.98GaAs layers, finally in Al0.98Growth is using AlGaAs the P- of material on GaAs layer
DBR obtains epitaxial layer on substrate；
The molding of VCSEL chip, is in turn divided into central area, intermediate region, edge by center to outside for the surface P-DBR
Region and outer region, grow layer of sin on P-DBRxLayer etches intermediate region, the corresponding SiN of outer regional locationxLayer is extremely
The surface P-DBR forms corresponding first SiN in central area positionxLayer twoth SiN corresponding with fringe region positionxLayer, then
On the surface P-DBR in the corresponding position evaporation metal in intermediate region as P-contact, along the 2nd SiNxThe edge etching of layer
After P-DBR, oxide layer and Quantum Well form table top to the surface N-DBR, to Al0.98GaAs layers of progress partial oxidation, will
Al0.98GaAs layers are divided into non-oxidation panel and oxidation panel, and deposition growing protective layer to part covers P-contact table on table top
Face finally carries out thinned and plates metal as N-contact to substrate.
Optionally, the growth of the Quantum Well is made as follows: the Al of one layer of 10 angstroms of thickness is first grown on N-DBRxGaAs
Potential barrier, then in AlxThe InGaAs potential well that one layer of 10 angstroms of thickness are grown in GaAs potential barrier, finally grows one in InGaAs potential well
Layer AlxGaAs potential barrier.
Optionally, the substrate surface growth has 40 pairs using AlGaAs the N-DBR of material, and growing in the Quantum Well has
30 pairs using AlGaAs the P-DBR of material.
Optionally, the protective layer uses SiNxVapor deposition is formed.
For VCSEL chip of the invention using N-DBR, P-DBR as laser mirror, Quantum Well, will be traditional as active area
GaAs material is changed to AlxGaAs, when potential barrier uses AlxGaAs, other opposite semiconductor materials will more easily reach lattice
Match, and Al0.1GaAs forbidden bandwidth 1.55, opposite GaAs forbidden bandwidth is higher, as shown in Fig. 2, and with the increase of Al component, taboo
Bandwidth is higher.When electronics is stimulated, relatively higher forbidden bandwidth is bound in more electronics in Quantum Well, improves
Combined efficiency, to reach the stimulated radiation of higher efficiency.Potential barrier in VCSEL chip of the invention uses AlxGaAs, phase
To GaAs, AlxGaAs forbidden bandwidth is higher, and is easy to reach Lattice Matching.And relatively higher forbidden bandwidth makes more electricity
Son, which is concentrated, to be strapped in Quantum Well, and a large amount of electronics increases the probability of excitation, improves combined efficiency, to reach higher
The stimulated radiation of efficiency.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the VCSEL chip of the prior art；
Fig. 2 is the forbidden bandwidth figure of the potential barrier of different materials；
Fig. 3 is the epitaxial layer structure schematic diagram in the VCSEL chip of high combined efficiency of the invention；
Fig. 4-Fig. 7 is that the corresponding structure of each step is shown in the manufacturing method of the VCSEL chip of high combined efficiency of the invention
It is intended to；
Wherein, substrate 100, N-contact 210, P-contact 220, N-DBR 310, Quantum Well 320, AlxGaAs
Potential barrier 321, InGaAs potential well 322, AlxGaAs potential barrier 323, oxide layer 330, non-oxidation panel 331, oxidation panel 332, P-
DBR340, table top 4, light hole 5, SiNxThe 600, the first SiN of layerxThe 610, the 2nd SiN of layerxLayer 620, protective layer 700, central area
81, intermediate region 82, fringe region 83, outer region 84, Al0.98GaAs layer 9.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in further detail.
It should be noted that similar or identical part all uses identical figure number, attached in attached drawing or specification description
The implementation for not being painted or describing in figure is form known to a person of ordinary skill in the art in technical field.In addition, though this
Text can provide the demonstration of the parameter comprising particular value, it is to be understood that parameter is equal to corresponding value without definite, but can connect
It is similar to be worth accordingly in the error margin or design constraint received.The direction term mentioned in embodiment, for example, "upper", "lower",
"top", "bottom", "left", "right" etc. are only the direction with reference to attached drawing, the protection scope being not intended to limit the invention.Herein
The relational terms such as first and second and the like of appearance are used merely to distinguish an entity with another entity, and
Not necessarily require or imply that there are any actual relationship or orders between these entities or operation.
As shown in fig. 7, the VCSEL chip of the high combined efficiency of the present embodiment, including substrate 100, and be grown in respectively
The epitaxial layer and N-contact 210 of 100 opposite sides of substrate, the manufacture raw material of substrate 100 include but is not limited to GaAs, extension
Layer includes N-DBR 310, Quantum Well 320, oxide layer 330 and the P-DBR 340, P- successively grown from bottom to up in substrate surface
DBR340, oxide layer 330, Quantum Well 320 are etched to 310 surface N-DBR and form table top 4.Quantum Well 320 includes overlapping life
Long multipair Quantum Well composite layer, preferably Quantum Well include 2~5 pairs of Quantum Well composite layers of overlapping growth, further preferably Quantum Well
3 pairs of Quantum Well composite layers including overlapping growth, are conducive to be bound in more electronics in Quantum Well, are conducive to improve multiple
Close efficiency.Specifically, Quantum Well composite layer includes the Al of overlapping growthxGaAs potential barrier 321, InGaAs potential well 322 and AlxGaAs
Potential barrier 323, the Al in each pair of Quantum Well composite layerxGaAs potential barrier 321 and AlxThe thickness of GaAs potential barrier 323 is 10 angstroms,
InGaAs potential well 322 with a thickness of 10 angstroms.
When potential barrier uses AlxGaAs material, other opposite semiconductor materials will more easily reach Lattice Matching, and
Al0.1GaAs forbidden bandwidth 1.55, opposite GaAs forbidden bandwidth is higher, as shown in Fig. 2, and with the increase of Al component, forbidden bandwidth
It is higher.When electronics is stimulated, relatively higher forbidden bandwidth is bound in more electronics in Quantum Well, improves compound
Efficiency, to reach the stimulated radiation of higher efficiency.Wherein, potential barrier AlxThe Al component of GaAs is according to VCSEL operating current size
Be adjusted: i.e. when electric current 5mA, when x 0.1, electric current 10mA, x 0.2, electric current is directly proportional to Al component, and electric current is every to increase one
Times, Al component is also needed to increase and is twice.
Specifically, N-DBR 310 includes the reflector element of 40 pairs of stacking growths, P-DBR 340 includes 30 pairs of stacking growths
Reflector element, reflector element be AlGaAs layers.Oxide layer 330 includes non-oxidation panel 331 and the oxidation for surrounding non-oxidation panel 331
Section 332, non-oxidation panel 331 is by Al0.98GaAs Material growth is formed, and oxidation panel 332 is by the Al after oxidation-treated0.98GaAs
It is formed.
Central area, intermediate region and fringe region, central area are in turn divided on P-DBR 340 from center to outside
For light hole 5, there is the first SiN in the growth of central area corresponding position on P-DBR 340xIn centre on layer 610, P-DBR 340
Region corresponding position evaporation metal material forms P-contact 220, and the raw material that P-contact 220 is used includes but is not limited to
Ti, Pt, Au have the 2nd SiN in the growth of fringe region corresponding position on P-DBR 340xLayer 620, table top 4 to P-contact
220 surfaces cover matcoveredn 700, and the section of protective layer 700 is in zigzag, and table top 4 is completely covered, covering Quantum Well 320,
The first SiN of oxide layer 330, the side of P-DBR 340 and coveringx610 side of layer and top surface, the protective layer 700 also partially cover
220 surface P-contact is covered, exposes 220 surface portion of P-contact, so that subsequent bonding wire makes current lead-through, protective layer
700 raw materials used include but is not limited to SiNx、SiO2。
The manufacturing method of above-mentioned VCSEL chip is as follows:
It is as shown in Figure 3:
S1. conventionally, first 100 surface of substrate made of GaAs is being used to grow 40 pairs using AlGaAs material
N-DBR210。
S2. in the surface N-DBR grown quantum trap 320, concrete operations are that one layer of 10 angstroms of thickness are first grown on N-DBR
AlxGaAs potential barrier 321, then in AlxThe InGaAs potential well 322 that one layer of 10 angstroms of thickness are grown in GaAs potential barrier, finally in InGaAs
One layer of Al is grown in potential wellxGaAs potential barrier 323.Potential barrier AlxThe Al component of GaAs is adjusted according to VCSEL operating current size:
When electric current 5mA, Al component 0.1, when electric current 10mA, Al component 0.2, electric current is directly proportional to Al component, and the every increasing of electric current is twice, Al
Component is also needed to increase and is twice.
S3. Al is grown in Quantum Well 3200.98GaAs layer 9 is used to be subsequently formed oxide layer 330, then in Al0.98GaAs layers
Upper 30 pairs of growth obtains epitaxial layer on substrate 100 using AlGaAs the P-DBR 340 of material.
340 surface P-DBR is in turn divided into central area 81, centre by center to outside by the molding of S4.VCSEL chip
Region 82, fringe region 83 and outer region 84.As shown in figure 4, conventionally growing layer of sin on P-DBR 340x
Layer 600；As shown in figure 5, etching intermediate region 82, the corresponding SiN in 84 position of outer regionxLayer is formed to 340 surface P-DBR
Corresponding first SiN in 81 position of central areax610 twoth SiN corresponding with 83 position of fringe region of layerxLayer 620, then in P-
In the corresponding position evaporation metal in intermediate region as P-contact 220, metal herein includes but is not limited on the surface DBR
Ti,Pt,Au；As shown in fig. 6, along the 2nd SiNxThe outer ICP of layer 620 etches P-DBR, oxide layer and Quantum Well to N-DBR
Surface forms table top 4, guarantees current convergence injection, according to conventional wet oxidizing process to Al0.98GaAs layers of progress part oxygen
Change, by Al0.98GaAs layers are divided into non-oxidation panel 331 and the composition oxide layer 330 of oxidation panel 332；As shown in fig. 7, then in table top 4
Upper deposition growing protective layer 700 to part covers 220 surface P-contact, and the section of the protective layer 700 is in zigzag, and complete
All standing table top 4, covering Quantum Well 320, the first SiN of oxide layer 330, the side of P-DBR 340 and coveringx610 side of layer
And top surface, the protective layer 700 also part covering surface P-contact expose P-contact surface portion, so as to subsequent weldering
Line makes current lead-through, and the raw material that protective layer uses includes but is not limited to SiNx、SiO2, finally substrate is carried out to be thinned to 110um,
And plating metal as N-contact 210, the N-contact metal material used includes but is not limited to AuGe, Au.
The VCSEL chip that above-mentioned manufacturing method manufactures, when P-contact and N-contact turn-on current in use,
Quantum Well starts recombination luminescence as active area, and projects laser from light hole.
When electronics is stimulated, the electronics of vitalizing semiconductor jumps to conduction band by valence band, when electronics jumps back to valence band by conduction band,
Energy is released in the form of luminous energy.Traditional GaAs material is changed to Al by the VCSEL chip of the present embodimentxGaAs, phase
To GaAs, AlxGaAs forbidden bandwidth is higher, and is easy to reach Lattice Matching.And relatively higher forbidden bandwidth makes more electricity
Son, which is concentrated, to be strapped in Quantum Well, and a large amount of electronics increases the probability of excitation, improves combined efficiency, to reach higher
The stimulated radiation of efficiency.
The above examples are only used to illustrate the technical scheme of the present invention and are not limiting, although referring to preferred embodiment to this hair
It is bright to be described in detail, those skilled in the art should understand that, it can modify to technical solution of the present invention
Or equivalent replacement should all cover without departing from the objective and range of technical solution of the present invention in claim of the invention
In range.Technology not described in detail in the present invention, shape, construction portion are well-known technique.
Claims (10)
1. the VCSEL chip of high combined efficiency, which is characterized in that the VCSEL chip includes substrate, and is grown in institute respectively
The epitaxial layer and N-contact of substrate opposite sides are stated, the epitaxial layer is included in the substrate surface and successively gives birth to from bottom to up
Long N-DBR, Quantum Well, oxide layer and P-DBR, the P-DBR, oxide layer, Quantum Well are etched to the surface N-DBR and form platform
Face, the Quantum Well include the multipair Quantum Well composite layer of overlapping growth, and the Quantum Well composite layer includes overlapping growth
AlxGaAs potential barrier, InGaAs potential well and AlxGaAs potential barrier, be in turn divided into from center to outside on the P-DBR central area,
Intermediate region and fringe region, the central area are light hole, and upper grow in central area corresponding position of the P-DBR has the
One SiNx layer is vapor-deposited with P-contact in intermediate region corresponding position on the P-DBR, in fringe region pair on the P-DBR
Position growth is answered to have the second SiNx layer.
2. the VCSEL chip of high combined efficiency according to claim 1, which is characterized in that the Quantum Well includes overlapping
2~5 pairs of Quantum Well composite layers of growth.
3. the VCSEL chip of high combined efficiency according to claim 2, which is characterized in that each pair of Quantum Well is compound
The Al of layerxGaAs potential barrier with a thickness of 10 angstroms, InGaAs potential well with a thickness of 10 angstroms.
4. the VCSEL chip of high combined efficiency according to claim 1, which is characterized in that the table top to P-contact
Surface covers matcoveredn, and table top is completely covered in zigzag for the section of the protective layer and part covers the surface P-contact.
5. the VCSEL chip of high combined efficiency according to claim 1, which is characterized in that the N-DBR includes 40 pairs of layers
The reflector element of storied length, the P-DBR include the reflector element of 30 pairs of stacking growths, and the reflector element is AlGaAs layers.
6. the VCSEL chip of -5 any high combined efficiencies according to claim 1, which is characterized in that the oxide layer packet
It includes non-oxidation panel and surrounds the oxidation panel of the non-oxidation panel, the non-oxidation panel is formed by Al0.98GaAs Material growth.
7. the manufacturing method of the VCSEL chip of high combined efficiency, which comprises the following steps:
Outer layer growth is made, and first grows in substrate surface using AlGaAs the N-DBR of material, then grows on the surface N-DBR
Quantum Well grows Al in Quantum Well0.98GaAs layers, finally in Al0.98It is grown on GaAs layer using AlGaAs the P-DBR of material,
Epitaxial layer is obtained on substrate；
The molding of VCSEL chip, is in turn divided into central area, intermediate region, fringe region by center to outside for the surface P-DBR
With outer region, layer of sin x layers is grown on P-DBR, etches intermediate region, the corresponding SiNx layer of outer regional location to P-
The surface DBR forms corresponding first SiNx layer in central area position and corresponding second SiNx layer in fringe region position, then exists
The surface P-DBR, as P-contact, etches P- along the edge of the second SiNx layer in the corresponding position evaporation metal in intermediate region
After DBR, oxide layer and Quantum Well form table top to the surface N-DBR, to Al0.98GaAs layers of progress partial oxidation, by Al0.98GaAs
Layer is divided into non-oxidation panel and oxidation panel, and deposition growing protective layer to part covers the surface P-contact on table top, finally to lining
Bottom carries out thinned and plates metal as N-contact.
8. the manufacturing method of the VCSEL chip of high combined efficiency according to claim 7, which is characterized in that the quantum
The growth of trap is made as follows: the Al of one layer of 10 angstroms of thickness is first grown on N-DBRxGaAs potential barrier, then in AlxIn GaAs potential barrier
The InGaAs potential well of one layer of 10 angstroms of thickness is grown, one layer of Al is finally grown in InGaAs potential wellxGaAs potential barrier.
9. the manufacturing method of the VCSEL chip of high combined efficiency according to claim 7, which is characterized in that the substrate
Surface growth has 40 pairs using AlGaAs the N-DBR of material, in the Quantum Well growth have 30 pairs using AlGaAs the P- of material
DBR。
10. the manufacturing method of the VCSEL chip of high combined efficiency according to claim 7, which is characterized in that the protection
Layer deposits to be formed using SiNx.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910523156.0A CN110197993B (en) | 2019-06-17 | 2019-06-17 | VCSEL chip with high recombination efficiency and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910523156.0A CN110197993B (en) | 2019-06-17 | 2019-06-17 | VCSEL chip with high recombination efficiency and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110197993A true CN110197993A (en) | 2019-09-03 |
| CN110197993B CN110197993B (en) | 2024-01-26 |
Family
ID=67754531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910523156.0A Active CN110197993B (en) | 2019-06-17 | 2019-06-17 | VCSEL chip with high recombination efficiency and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110197993B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112152084A (en) * | 2020-09-27 | 2020-12-29 | 深圳市飞研智能科技有限公司 | Lattice-matched silicon-based GaInNP vertical cavity surface emitting laser |
| CN112397997A (en) * | 2020-11-16 | 2021-02-23 | 扬州乾照光电有限公司 | Semiconductor laser and manufacturing method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6229153B1 (en) * | 1996-06-21 | 2001-05-08 | Wisconsin Alumni Research Corporation | High peak current density resonant tunneling diode |
| US20050110043A1 (en) * | 2003-11-21 | 2005-05-26 | Sanken Electric Co., Ltd. | Nitride semiconductor substrate, method of fabrication thereof, and semiconductor element built thereon |
| JP2007201040A (en) * | 2006-01-25 | 2007-08-09 | Anritsu Corp | Semiconductor light emitting element |
| CN101667715A (en) * | 2008-09-03 | 2010-03-10 | 中国科学院半导体研究所 | Single-mode high-power vertical cavity surface emitting laser and manufacturing method thereof |
| CN102593719A (en) * | 2012-03-09 | 2012-07-18 | 北京工业大学 | Edge-emission semiconductor laser for improving light field distribution of active area |
| US20170005455A1 (en) * | 2015-07-02 | 2017-01-05 | Sae Magnetics (H.K.) Ltd. | Tunable optical phase filter |
| CN109687288A (en) * | 2019-03-01 | 2019-04-26 | 厦门乾照半导体科技有限公司 | A kind of high density VCSEL array structure and preparation method thereof |
-
2019
- 2019-06-17 CN CN201910523156.0A patent/CN110197993B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6229153B1 (en) * | 1996-06-21 | 2001-05-08 | Wisconsin Alumni Research Corporation | High peak current density resonant tunneling diode |
| US20050110043A1 (en) * | 2003-11-21 | 2005-05-26 | Sanken Electric Co., Ltd. | Nitride semiconductor substrate, method of fabrication thereof, and semiconductor element built thereon |
| JP2007201040A (en) * | 2006-01-25 | 2007-08-09 | Anritsu Corp | Semiconductor light emitting element |
| CN101667715A (en) * | 2008-09-03 | 2010-03-10 | 中国科学院半导体研究所 | Single-mode high-power vertical cavity surface emitting laser and manufacturing method thereof |
| CN102593719A (en) * | 2012-03-09 | 2012-07-18 | 北京工业大学 | Edge-emission semiconductor laser for improving light field distribution of active area |
| US20170005455A1 (en) * | 2015-07-02 | 2017-01-05 | Sae Magnetics (H.K.) Ltd. | Tunable optical phase filter |
| CN109687288A (en) * | 2019-03-01 | 2019-04-26 | 厦门乾照半导体科技有限公司 | A kind of high density VCSEL array structure and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112152084A (en) * | 2020-09-27 | 2020-12-29 | 深圳市飞研智能科技有限公司 | Lattice-matched silicon-based GaInNP vertical cavity surface emitting laser |
| CN112397997A (en) * | 2020-11-16 | 2021-02-23 | 扬州乾照光电有限公司 | Semiconductor laser and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110197993B (en) | 2024-01-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7912105B2 (en) | Vertical cavity surface emitting laser | |
| CN101651287B (en) | Vertical cavity surface emitting laser | |
| US8040934B2 (en) | Vertical cavity surface emitting laser and method of manufacturing thereof | |
| JP2019012744A (en) | Semiconductor light-emitting element and manufacturing method thereof | |
| KR102518449B1 (en) | Indium Phosphide VCSEL with Dielectric DBR | |
| US20040258121A1 (en) | Multi-wavelength surface emitting laser and method for manufacturing the same | |
| US8027370B2 (en) | Semiconductor device | |
| JP3219823B2 (en) | Semiconductor light emitting device | |
| US20220224080A1 (en) | Vertical cavity surface emitting laser device and manufacturing method thereof | |
| CN110197993A (en) | The VCSEL chip and its manufacturing method of high combined efficiency | |
| JP3800856B2 (en) | Surface emitting laser and surface emitting laser array | |
| JP2002204026A (en) | Surface emitting device | |
| JP2009188238A (en) | Surface light-emitting laser and method of manufacturing the same | |
| JP5717640B2 (en) | Optoelectronic semiconductor chip and method of manufacturing optoelectronic semiconductor chip | |
| CN112290379B (en) | VCSEL chip and manufacturing method thereof | |
| CN209881094U (en) | VCSEL chip with high recombination efficiency | |
| CN109103745B (en) | VCSEL structure with air gap DBR and preparation method thereof | |
| JP2003017806A (en) | Compound semiconductor light-emitting element, manufacturing method therefor, and the compound semiconductor light-emitting device | |
| JP4771142B2 (en) | Vertical cavity light emitting diode | |
| US20220224082A1 (en) | Vertical cavity surface emitting laser device and manufacturing method thereof | |
| CN115764549B (en) | VCSEL laser | |
| US20240079854A1 (en) | Vertical Cavity Surface Emitting Laser, Electronic Device with Same and Manufacturing Method for Same | |
| CN216750641U (en) | Vertical cavity surface emitting laser structure | |
| KR100275774B1 (en) | Short wavelength luminous semiconductor laser diode | |
| CN216699077U (en) | Red light VCSEL chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |