CN110196612A - 电压调节器 - Google Patents
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- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
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- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
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Abstract
本发明涉及电压调节器。电压调节器具备有:连接在误差放大电路的第一输入端子与电压调节器的输入端子之间的第一开关、连接在误差放大电路的第二输入端子与电压调节器的输出端子之间的第二开关、连接在第一输入端子与第二输入端子之间的第三开关、以及基于电压调节器的输出电压来检测输出端子的短路的短路检测电路。
Description
技术领域
本发明涉及电压调节器。
背景技术
电压调节器具备基准电压源、误差放大电路、分压电阻和输出晶体管。
误差放大电路将分压电阻所输出的反馈电压和基准电压源的基准电压比较来控制输出晶体管的栅极电压,以使输出电压为固定。只要为输出电压被保持为固定的状态,则反馈电压和基准电压为大致相等的电压。即,误差放大电路的反相输入端子和非反相输入端子的电压大致相等。
在误差放大电路中,当反相输入端子和非反相输入端子的输入电压在长的时间内为彼此不同的电压时,由于偏置温度不稳定性,差动输入晶体管的阈值电压变动而产生输入偏移电压等性能进行劣化。
在图3中示出以往的误差放大电路300的电路图。误差放大电路300具备PMOS晶体管301~303、NMOS晶体管304~305、以及开关SW1~8。误差放大电路300在省电模式时使开关SW1接通,停止偏置电压Vbias,使PMOS晶体管301截止,由此,停止工作电流即停止工作。此外,使开关SW2和SW3关断来将输入端子INP和INN与作为输入晶体管的PMOS晶体管302和303断开。同时,使开关SW4~8接通,将PMOS晶体管302和303的栅极端子接地,将NMOS晶体管304和305的全部端子接地。误差放大电路300通过采取这样的电路结构,从而在省电模式时使各晶体管的各端子为相同的电压,因此,防止起因于偏置温度不稳定性的性能劣化(例如,专利文献1)。
现有技术文献
专利文献
专利文献1:日本特开2004-282121号公报。
发明要解决的课题
然而,在具备上述那样的以往的误差放大电路的电压调节器中,在通常工作中输出端子负载短路(电源短路或接地短路)的情况下,被输入反馈电压的输入端子(例如INN)的电压为比基准电压高或低的电压的状态持续,在栅极被连接于输入端子INN的PMOS晶体管303中发生起因于偏置温度不稳定性的性能劣化的可能性变高。
发明内容
本发明的目的在于提供即使在不是省电模式的工作中也能够防止起因于偏置温度不稳定性的性能劣化的电压调节器。
用于解决课题的方案
本发明的一个方式中的电压调节器的特征在于,具备:基于从输入端子输入的基准电压和从输出端子输出的输出电压来控制输出晶体管的栅极电压的误差放大电路;连接在所述误差放大电路的第一输入端子与所述输入端子之间的第一开关;连接在所述误差放大电路的第二输入端子与所述输出端子之间的第二开关;连接在所述第一输入端子与所述第二输入端子之间的第三开关;以及基于所述输出电压来检测输出端子的短路的短路检测电路,关于所述第一~第三开关,根据所述短路检测电路所输出的检测信号来控制接通关断。
发明效果
根据本发明的电压调节器,即使在不是省电模式的工作中,也能够防止起因于偏置温度不稳定性的性能劣化。
附图说明
图1是示出本发明的第1实施方式的电压调节器(voltage regulator)的电路图。
图2是示出本发明的第2实施方式的电压调节器的电路图。
图3是在以往的电压调节器中使用的误差放大电路的电路图。
具体实施方式
以下,参照附图来对本发明的实施方式进行说明。
<第一实施方式>
图1是本发明的第一实施方式的电压调节器100的电路图。
本实施方式的电压调节器100具备:误差放大电路10、输出电路20、对负载的接地短路进行检测的接地短路检测电路30、对负载的电源短路进行检测的电源短路检测电路40、AND电路51、OR电路52、电流源53、开关SW11~14、电源端子1、接地端子2、输入端子3、以及输出端子4。
误差放大电路10具备:作为差动输入对的NMOS晶体管11和12、PMOS晶体管13和14、以及电流源15。输出电路20具备作为输出晶体管的PMOS晶体管21。接地短路检测电路30具备PMOS晶体管31、电流源32和34、以及NMOS晶体管33。电源短路检测电路40具备二极管41、PMOS晶体管42、电流源43和44、NMOS晶体管45、以及NOT电路46。
误差放大电路10控制PMOS晶体管21的栅极端子,以使输入到输入端子3的基准电压Vref与输出端子4的输出电压Vout相等。接地短路检测电路30基于所输入的电压调节器100的输出端子的电压Vout,从NMOS晶体管33的漏极端子输出接地短路检测信号GF,从NMOS晶体管33的栅极端子输出接地短路非检测信号GFX。电源短路检测电路40基于所输入的电压调节器100的输出端子的电压Vout,从NOT电路46的输出端子输出电源短路检测信号SF,从NOT电路46的输入端子输出电源短路非检测信号SFX。开关SW11~14当低电平的信号被输入到控制端子时关断(断开),当高电平的信号被输入到控制端子时接通(闭合)。
接着,对第一实施方式的电压调节器100的连接进行说明。
在误差放大电路10中,在作为第一输入端子的NMOS晶体管11的栅极端子经由开关SW12连接有输入端子3,在作为第二输入端子的NMOS晶体管12的栅极端子经由开关SW11连接有输出端子4,作为输出端子的NMOS晶体管11的漏极端子被连接于PMOS晶体管21的栅极端子。在PMOS晶体管21中,在源极端子连接有电源端子1,漏极端子被连接于输出端子4。在接地短路检测电路30中,在输入端子连接有输出端子4,输出接地短路检测信号GF的第一输出端子被连接于OR电路52的一个输入端子,输出接地短路非检测信号GFX的第二输出端子被连接于AND电路51的一个输入端子。在电源短路检测电路40中,在输入端子连接有输出端子4,输出电源短路检测信号SF的第一输出端子被连接于OR电路52的另一个输入端子,输出电源短路非检测信号SFX的第二输出端子被连接于AND电路51的另一个输入端子。AND电路51从输出端子输出短路非检测信号FDX。OR电路52从输出端子输出短路检测信号FD。
开关SW11和开关SW12的控制端子连接有AND电路51的输出端子。开关SW13被连接在误差放大电路10的第一输入端子与第二输入端子之间,在控制端子连接有OR电路52的输出端子。
电流源53经由开关SW14被连接在PMOS晶体管21的栅极端子与接地端子2之间。开关SW14的控制端子连接有接地短路检测电路30的输出端子。电流源53和开关SW14构成用于从不是接地短路的接地短路检测状态恢复的启动电路。
对如上述那样构成的电压调节器100的工作进行说明。
在电压调节器100中,在向电源端子1施加了电源电压Vdd的通常时,误差放大电路10将输出电压Vout和输入电压Vref比较,以使它们相等的方式控制PMOS晶体管21的栅极电压,由此,向输出端子4输出固定的输出电压Vout。此时,开关SW11和开关SW12接通,开关SW13和开关SW14关断。
接着,对电压调节器100的输出端子4由于负载短路而接地短路的情况下的工作进行说明。
输出端子4的输出电压Vout由于接地短路而降低为接地端子2的电压电平。
接地短路检测电路30如以下那样工作来检测输出端子4的接地短路。
当输入端子的电压降低即栅极端子被接地后的PMOS晶体管31的源极端子的电压降低而PMOS晶体管31变得不能导通时,NMOS晶体管33根据电流源32而截止。因此,接地短路检测电路30利用电流源34输出高电平的接地短路检测信号GF,利用电流源32输出低电平的接地短路非检测信号GFX。
此外,在电源短路检测电路40中,当输入端子的电压变低时,PMOS晶体管42截止,根据电流源43而NMOS晶体管45截止,因此,利用电流源44和NOT电路46输出低电平的电源短路检测信号SF,利用电流源44输出高电平的电源短路非检测信号SFX。
在AND电路51中,由于被输入低电平的接地短路非检测信号GFX,所以从输出端子输出低电平的短路非检测信号FDX。在OR电路52中,由于被输入高电平的接地短路检测信号GF,所以从输出端子输出高电平的短路检测信号FD。
根据低电平的短路非检测信号FDX,开关SW11和开关SW12关断。因此,将NMOS晶体管11的栅极端子与输入端子3断开,将NMOS晶体管12的栅极端子从输出端子4断开。根据高电平的短路检测信号FD,开关SW13接通。因此,NMOS晶体管11的栅极端子与NMOS晶体管12的栅极端子被短路。此外,根据高电平的接地短路检测信号GF,开关SW14接通。因此,PMOS晶体管21的栅极端子经由电流源53被连接于接地端子2。
作为误差放大电路10的差动输入对的NMOS晶体管11的栅极端子和NMOS晶体管12的栅极端子如上述那样被控制,由此,即使输出端子4为接地短路状态,也总是被施加相等的电压,因此,能够防止起因于偏置温度不稳定性的性能劣化。
再有,当输出端子4变为接地短路状态时,PMOS晶体管21的漏极电流变为过电流状态,但是,利用未图示的过电流保护电路控制PMOS晶体管21的栅极端子,以使变为期望的漏极电流。此时,电流源53将PMOS晶体管21的栅极端子向接地端子2下拉(pull down)到不对过电流保护电路的控制造成坏影响的程度。
接着,对电压调节器100的启动时的工作进行说明。
电压调节器100当被向电源端子1施加电源电压Vdd时启动,但是,与输出端子4由于负载短路而接地短路的情况相同,此时的输出电压Vout与接地端子2的电压大致相等。因此,接地短路检测电路30由于输入端子变为接地端子2的电压,所以,判定为电压调节器100为接地短路模式。
接地短路检测电路30和电源短路检测电路40输出与上述的接地短路状态同样的接地短路检测信号GF、接地短路非检测信号GFX、电源短路检测信号SF和电源短路非检测信号SFX。然后,AND电路51和OR电路52也输出同样的短路非检测信号FDX和短路检测信号FD。
然后,也同样地控制开关SW11、开关SW12、开关SW13和开关SW14,PMOS晶体管21的栅极端子被电流源53下拉到接地端子2。即,PMOS晶体管21变为导通状态,因此,输出端子4的电压逐渐上升。
当输出端子4的电压逐渐上升因此接地短路检测电路30的输入端子的电压逐渐上升而PMOS晶体管31导通时,NMOS晶体管33导通,输出低电平的接地短路检测信号GF,输出高电平的接地短路非检测信号GFX。此时,电源短路检测电路40未检测到电源短路。因此,短路非检测信号FD为低电平,短路检测信号FDX为高电平,因此,开关SW11和开关SW12接通,开关SW13和开关SW14关断,电压调节器100变为通常的工作状态即进行启动。
像这样做,本实施方式的电压调节器100不损害启动时的工作,而在输出端子4由于负载短路等而接地短路时,使作为误差放大电路10的输入差动对的MOS晶体管的栅极为相同电位,由此,能够防止起因于偏置温度不稳定性的性能劣化。
此外,关于电压调节器100的输出端子4由于负载短路等而电源短路的情况下的工作,也与上述的接地短路的情况大致同样,因此,省略说明。
<第二实施方式>
参照图2来对第二实施方式的电压调节器200进行说明。
本实施方式的电压调节器200为从第1实施方式的电压调节器100将误差放大电路10和输出电路20更换为误差放大电路10b和输出电路20b、删除开关SW14和电流源53、追加开关SW15、16和电流源54、55后的结构。
关于结构的其他的部分,与图1的电压调节器200相同,因此,对相同的结构要素标注相同的附图标记,适当省略重复的说明。
误差放大电路10b具备:作为差动输入对的PMOS晶体管11b和12b、电流源13b、14b、15b、PMOS晶体管16和17、以及被向栅极端子施加偏置电压Vb后的共源共栅(cascode)晶体管即NMOS晶体管18和19。输出电路20b具备作为源极接地放大电路的NMOS晶体管22和电阻23、作为输出晶体管的PMOS晶体管21、以及开关SW17。
以下,关于本实施方式的电压调节器200的工作,着眼于与第1实施方式的电压调节器100的不同点来进行说明。
当电压调节器100的输出端子4由于负载短路而接地短路时,接地短路检测电路30检测输出端子4的接地短路,输出高电平的接地短路检测信号GF和低电平的接地短路非检测信号GFX。此外,电源短路检测电路40输出低电平的电源短路检测信号SF和高电平的电源短路非检测信号SFX。然后,AND电路51输出低电平的短路非检测信号FDX,OR电路52输出高电平的短路检测信号FD。
因此,与第一实施方式同样地,开关SW11和开关SW12关断,开关SW13接通,因此,向作为误差放大电路10b的输入差动对的MOS晶体管的栅极端子总是施加相等的电压,能够防止起因于偏置温度不稳定性的性能劣化。
在第二实施方式中,开关SW15接通,开关SW16关断。由于开关SW15接通,所以,误差放大电路10b从输出端子向NMOS晶体管22的栅极输出高电平的信号。因此,在输出电路20b中,NMOS晶体管22导通,PMOS晶体管21导通,因此,不会损害启动时的工作。
接着,对电压调节器200的输出端子4由于负载短路而与比电源端子1的电压高的电压的外部的电源电源短路的情况下的工作进行说明。
电源短路检测电路40如以下那样工作来检测输出端子4的电源短路。
电压调节器200的输出端子4的输出电压Vout由于电源短路而上升到比电源端子1的电压高的电压电平。当在将PMOS晶体管42的阈值设为VTP42并且将二极管41的正向电压设为VF时输出电压Vout为(Vdd+VTP42+VF)以上的电压时,PMOS晶体管42导通。当在PMOS晶体管42中流动的电流变为恒定电流源43的电流值以上而栅极电压变为阈值以上时,NMOS晶体管45导通。因此,电源短路检测电路40输出高电平的电源短路检测信号SF,输出低电平的电源短路非检测信号SFX。
其结果是,与接地短路检测时同样地,开关SW11和开关SW12关断,开关SW13接通,因此,其效果也是同样的。此外,此时,开关SW15关断,开关SW16接通,因此,误差放大电路10b从输出端子输出低电平的信号。因此,在输出电路20b中,NMOS晶体管截止,PMOS晶体管截止。进而,开关SW17关断,因此,能够防止从输出端子4向电源端子1的逆流电流。
因此,与第一实施方式同样,在本实施方式的电压调节器200中,也使作为误差放大电路10b的输入差动对的MOS晶体管的栅极为相同电位,由此,能够防止起因于偏置温度不稳定性的性能劣化。
以上,对本发明的实施方式进行了说明,但是,本发明并不限定于上述实施方式,当然能够在不偏离本发明的主旨的范围内进行各种变更。
例如,第二实施方式中的输出端子4所具备的逆流防止功能也可以应用于第一实施方式,如果不需要则也可以删除。
此外,例如,电源短路检测电路40为对比电源电压Vdd高的电压进行检测的电路结构,但是,也可以构成为以期望的电压值检测。
此外,例如,关于作为误差放大电路10的输入差动对的MOS晶体管的栅极,以在开关SW11和开关SW12关断时不会变为浮置(floating)的方式使用电流源进行下拉也可。
此外,例如,接地短路检测电路30和电源短路检测电路40根据电源电压Vdd、基准电压Vref、连接于输出端子4的外部电源电压的大小关系而仅具备任一个也可。
此外,例如,说明为误差放大电路10的输入端子连接有输出端子4,但是也可以在输出端子4连接有具备对输出电压Vout进行分压的分压电路的、分压电路的输出端子。
附图标记的说明
100 电压调节器
10、10b 误差放大电路
20、20b 输出电路
30 接地短路检测电路
40 电源短路检测电路。
Claims (4)
1.一种电压调节器,其特征在于,具备:
基于从输入端子输入的基准电压和从输出端子输出的输出电压来控制输出晶体管的栅极电压的误差放大电路;
连接在所述误差放大电路的第一输入端子与所述输入端子之间的第一开关;
连接在所述误差放大电路的第二输入端子与所述输出端子之间的第二开关;
连接在所述第一输入端子与所述第二输入端子之间的第三开关;以及
基于所述输出电压来检测输出端子的短路的短路检测电路,
关于所述第一~第三开关,根据所述短路检测电路所输出的检测信号来控制接通关断。
2.根据权利要求1所述的电压调节器,其特征在于,所述短路检测电路检测所述输出端子的接地短路。
3.根据权利要求2所述的电压调节器,其特征在于,还具备启动电路,所述启动电路根据所述短路检测电路检测到所述输出端子的接地短路时的检测信号进行工作。
4.根据权利要求1至3的任一项所述的电压调节器,其特征在于,所述短路检测电路检测所述输出端子的电源短路。
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