CN110166061B

CN110166061B - Selective protection method based on Viterbi decoder

Info

Publication number: CN110166061B
Application number: CN201910475011.8A
Authority: CN
Inventors: 高镇; 闫丽娜; 朱锦华
Original assignee: Tianjin University
Current assignee: Tianjin University
Priority date: 2019-06-03
Filing date: 2019-06-03
Publication date: 2021-06-08
Anticipated expiration: 2039-06-03
Also published as: CN110166061A

Abstract

The invention relates to a selective protection method based on a Viterbi decoder, which comprises the following steps on the basis of realizing the Viterbi decoder based on an FPGA and calculating the bit width of a register: selective protection of the Viterbi decoder: and (3) adopting three-mode protection to the register bit with the SEU tolerance capacity of 0: and adding two bits of redundant information to all bit positions simultaneously, storing the same information as the original bit positions, and taking any two bits of the same bit information as the final result. Performing two-mode protection on the SEU fault-tolerant register bit position: and adding corresponding one-bit redundant information to each bit, storing the information identical to the original bit position, adding a logic AND gate after the storage, wherein the output result of the AND gate is the final result of the protected bit position.

Description

Selective protection method based on Viterbi decoder

Technical Field

The invention relates to a selective protection method based on a Viterbi decoder.

Background

Communication is a key element of spatial systems, particularly satellites. In fact, in many cases, the primary purpose of a satellite is to provide communications for terrestrial services. Therefore, these satellites need to be able to process the received signals on board. This requires complex circuitry in many cases. For example, to achieve an acceptable Bit Error Rate (BER) even at low signal-to-noise ratios (SNRs), the transmit-end signal is typically encoded with some form of coding, and then the errors are corrected at the receiver. When convolutional coding is used at the transmitter, the receiver typically implements a Viterbi (Viterbi) decoder to detect and correct errors. The decoder may be implemented in software running on a processor. However, in the space environment, there are radiation particles, and after the space radiation particles bombard the processor, the logic configuration or the stored data of the processing module may be changed, which causes processing failure and reduces the accuracy of the decoding result, thereby disabling the communication system. The most common of them is Single Event events (SEUs). Therefore, the method is extremely important for the radiation-resistant protection work of the space communication system.

Protection methods commonly used at present include hardware reinforcement, system level protection and circuit level fault tolerance. Hardware reinforcement includes the covering of a protective shield outside the processing platform and the use of special packaging technology for aerospace grade chips. Although hardware reinforcement can shield most of the radiation particles, radiation induced failures are not completely eliminated. The system level protection can restore system faults through mechanisms such as multi-machine backup, periodic fault detection and restarting and the like. However, the method has poor real-time performance, and cannot ensure that the system carries out instant fault tolerance under the condition of uninterrupted operation. The circuit level fault tolerance is a necessary means for dealing with the single event effect and realizing the instant fault detection and fault tolerance of the communication signal processing module.

The essence of circuit level fault-tolerant signal processing is that through introducing redundancy (logic or time), a processing module can still output correct results under the condition that a single event effect causes the fault of partial logic or storage units. The most common scheme is the Triple modular Redundancy scheme (TMR). The basic idea is to duplicate two original processing modules, so that three identical modules process input data simultaneously, and when one of the modules fails, the output end can output correct results through a majority selector. Since this solution needs to increase the computing resources and power consumption by two times on the original basis, it is a huge burden for the space platform with strictly limited volume, weight and power. On the other hand, under the same system resource limitation, if the TMR scheme is used, the overall processing capacity of the system will be reduced to one third of that of the unprotected case, which will greatly limit the processing capacity and the diversity of functions of the space platform. In addition, in the conventional three-mode protection scheme, the overall behavior characteristics of the Viterbi decoder and the self fault-tolerant capability are not fully utilized.

The selective protection scheme for the Viterbi decoder provided by the invention greatly reduces the resource overhead while ensuring the correctness of the decoding result.

Disclosure of Invention

In view of the above problems, it is an object of the present invention to provide a selective protection scheme for Viterbi decoders. The method has the advantages that the overall behavior characteristics of the Viterbi decoder are obtained based on theoretical analysis and simulation experiments, the fault-tolerant capability of the Viterbi decoder is quantized, selective protection is carried out on modules which are beyond the fault-tolerant capability range of the Viterbi decoder and easily cause decoding failure, and the decoding accuracy is improved. In order to achieve the purpose, the invention adopts the following technical scheme:

a selective protection method based on a Viterbi decoder comprises the following steps on the basis of realizing the Viterbi decoder based on an FPGA and calculating the bit width of a register:

1) selective protection of the Viterbi decoder: and (3) adopting three-mode protection to the register bit with the SEU tolerance capacity of 0: and adding two bits of redundant information to all bit positions simultaneously, storing the same information as the original bit positions, and taking any two bits of the same bit information as the final result.

2) Performing two-mode protection on the SEU fault-tolerant register bit position: and adding corresponding one-bit redundant information to each bit, storing the information identical to the original bit position, adding a logic AND gate after the storage, wherein the output result of the AND gate is the final result of the protected bit position.

Due to the adoption of the technical scheme, the invention has the following advantages:

(1) the two-mode selective protection scheme adopted by the invention focuses on the self fault-tolerant capability of the decoder, and is a fault-oriented protection method. The fault tolerance is carried out aiming at the faults exceeding the self fault tolerance capability, and compared with other schemes, the fault tolerance method reduces the excessive protection and greatly reduces the resource overhead.

(2) The overall behavior characteristics of the Viterbi decoder are fully utilized in the invention.

(3) The scheme provided by the invention is a fault-tolerant method researched on the basis of a decoding principle, so that the scheme is irrelevant to a specific implementation mode and is convenient to combine with other fault-tolerant schemes.

Drawings

Fig. 1 is a flow diagram of an implementation of a Viterbi decoder selective protection scheme.

Fig. 2 is a diagram of a two-mode selective protection scheme.

Detailed Description

1) The convolutional code is of the form (n, k, m), where n is the code outputBit information, k is the encoded input bit information, and m represents the number of shift registers in the convolutional encoder. In total 2^kmA state, therefore, has 2^kmA bar survivor path information (PM) (PathMetric) value; each state has 2^kBranch of strips, thus having 2^kPath transfer information bm (branch metric) values. The input sequence is L bits long and will be divided into groups of k bits after entering the encoder.

L_C＝n*(L/k) (1)

Calculating the length L of the output sequence after coding according to the formula (1)_C；

PM_max＝L_C*A_mean (2)

Calculating the maximum value PM required to be expressed by the path information PM register stored in each branch according to the formula (2)_max，A_meanIs the average amplitude of the input signal;

calculating the bit width W required by the register storing the PM value information corresponding to each state according to the formula (3)_PM。

Calculating the bit width W of the path transfer information BM register according to a formula (4)_BMWherein A is_maxIs the input signal maximum amplitude. The decoder control bit information and other module register bit width information can be obtained by searching.

2) The register bit position with SEU tolerance capacity of 0 (the fault can lead the final decoding result to be wrong) is subjected to three-mode protection: adding two bits of redundant information to all bit positions at the same time, storing the information which is the same as the original bit position, and taking any two bits of the same bit information as the standard of the final result so as to realize the 100 percent fault-tolerant capability of the bit position to the SEU;

and performing two-mode protection on the register bit position which has fault-tolerant capability to the SEU (even if a certain amount of faults occur, the correctness of a final decoding result cannot be influenced, but the fault-tolerant capability beyond the bit position can cause the decoding result to be wrong): and adding a corresponding redundant bit information for each bit to store the information with the same position as the original bit position, and adding a logic AND gate after the redundant bit information is stored in the original bit position, wherein the output result of the AND gate is the final result of the position of the protected bit. The two-mode protection mentioned in the scheme is only suitable for the condition that the original bit position information is 0 and the SEU is subjected to single particle bombardment and then is inverted into 1. The purpose of improving the fault-tolerant performance of the Viterbi decoder by using lower expenditure is realized.

Example 1:

1) convolutional coding (3,1,6) is used for the inventive examples. The length of the information to be coded in the encoder is 54, and 60 s are added at the tail of the sequence to realize a return-to-zero code, so that the length of the coded information is L3 (54+6) 180. The bit widths of the PM register and the BM register are calculated to be 13(12+1) and 8(7+1) according to the formulas (1) to (4) in the above embodiment, and 1 bit is added additionally to indicate that the most significant bit is used for representing the sign bit. Since k is 1 and m is 3, each decoding step in the decoding process has 2⁶64 states, each state having 2¹2 transfer paths are used to find the optimal path for each state in each step in the decoding process.

2) The Viterbi decoder is realized based on FPGA, and the whole decoder mainly comprises four modules: top Controller: the enable signal which controls other modules of the decoder is 23 bits in total; PMupdate: storing the PM information of the survivor path of each state in each step in the decoding process and the BM information in the comparing and selecting module, and continuously refreshing along with the decoding depth information, wherein 13 × 64 bits in the PM value register is 832 bits, and 8 × 32 × 4 bits in the BM value register is 1024 bits; traceback: storing the decoding result in the backtracking process, wherein the total number of the decoding result is 60 bits; BRAM: and the register for storing all state survivor path information in the whole decoding process has 60 × 64-3840 bits.

3) And performing fault injection on the decoder based on the single event reversal of the simulation space of the FPGA platform. Bit positions with tolerance 0 for SEU: the Top Controller module and the Traceback module adopt a protection scheme of triple modular redundancy to ensure 100% of fault-tolerant capability theoretically; the rest bit information has a certain SEU fault-tolerant capability, wherein the fault-tolerant capability of the BRAM module to the SEU reaches more than 99%, the low bit position of the PM register and the fault-tolerant capability of the BM register to the SEU are 100% (theoretical analysis and experimental auxiliary verification prove that the conclusion is true). From the perspective of reducing the overhead of fault-tolerant protection resources, the protection scheme of two-mode redundancy mainly aims at the high bit position of the PM register.

4) In the Viterbi decoding process for soft decision input, there are two cases where the final decoding fails due to the variation of the PM value:

(a) the PM value information of the correct route becomes small (1 → 0); (b) the PM value information of the incorrect path becomes larger (0 → 1)

Failure assumption 1: under the condition of no fault, two 0's are stored in the two-mode register, wherein one path is changed into 1 by SEU bombardment, the result is still 0 after passing through an AND gate, and the fault caused by the condition (b) is avoided;

failure assumption 2: under the condition of no fault, two 1 are stored in the two-mode register, wherein one path is changed into 0 by SEU bombardment, the result is changed into 0 after passing through an AND gate, and the fault caused by the condition (a) cannot be avoided;

in practical experiments, the probability of the occurrence of the case (a) is 0.5/64-0.7%, and the overhead is reduced by 4.4% relative to the conventional triple-modular redundancy after the selective protection scheme is adopted.

Claims

1. A selective protection method based on a Viterbi decoder comprises the following steps on the basis of realizing the Viterbi decoder based on an FPGA and calculating the bit width of a register:

1) selective protection of the Viterbi decoder: and (3) adopting three-mode protection to the register bit with the SEU tolerance capacity of 0: adding two bits of redundant information to all bit positions at the same time, storing the same information as the original bit positions, and taking any two bits of the same bit information as the standard of the final result;

2) performing two-mode protection on the SEU fault-tolerant register bit position: and adding corresponding one-bit redundant information to each bit, storing the information identical to the original bit position, adding a logic AND gate after the storage, wherein the output result of the AND gate is the final result of the bit position of the protected register.