CN110166061A - A kind of selective protection method based on Viterbi decoder - Google Patents
A kind of selective protection method based on Viterbi decoder Download PDFInfo
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- CN110166061A CN110166061A CN201910475011.8A CN201910475011A CN110166061A CN 110166061 A CN110166061 A CN 110166061A CN 201910475011 A CN201910475011 A CN 201910475011A CN 110166061 A CN110166061 A CN 110166061A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
- H03M13/235—Encoding of convolutional codes, e.g. methods or arrangements for parallel or block-wise encoding
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
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Abstract
The present invention relates to a kind of selective protection methods based on Viterbi decoder; on the basis of realizing Viterbi decoder and counter register bit wide based on FPGA; include: selectively to be protected to Viterbi decoder: being protected using three moulds the register bit position for being 0 to SEU tolerance: to all bit positions while adding two redundancies; storage and former bit position identical information, final result are subject to any two same bits information.Have the register bit position of fault-tolerant ability to carry out two mould protections SEU: each all adds a corresponding redundancy; storage and former bit position identical information; and a logical AND gate is added hereafter, it is this by protection bit position final result with door output result.
Description
Technical field
The present invention relates to a kind of selective protection methods based on Viterbi decoder.
Background technique
Communication is space system, especially the key element of satellite.In fact, in many cases, the main mesh of satellite
Be to provide communication for terrestrial service.Therefore, these satellites are required to carry out onboard processing to reception signal.This is in many feelings
Complicated circuit is needed under condition.For example, to realize the acceptable bit error rate at low signal-to-noise ratio (SNR) to reach
(BER) purpose, sending end signal usually has some form of coding, then corrects mistake in receiver.When in transmitter
When end is using convolutional encoding, receiver usually realizes Viterbi (Viterbi) decoder to detect and correct mistake.Decoder can
To be realized in running software on a processor.But in the space environment, there is radiating particles, when irradiation space particle
After bombarding processor, the logic configuration of processing module or storing data may be made to change, lead to handling failure, reduce
The accuracy of decoding result, so that communication system be made to fail.One of the most common is exactly single particle effect (Single Event
Upsets,SEUs).Therefore particularly important to the Flouride-resistani acid phesphatase protected working of space communication system.
The guard method being commonly used includes that hardware reinforcing, system-level protection and circuit-level are fault-tolerant.Hardware reinforces packet
It includes and covers shield and the aerospace grade chip using special package technique outside processing platform.Although hardware reinforcing can shield big
Partial radiation particle, but failure caused by irradiation can not be completely eliminated.System-level protection passes through multi-computer back-up, periodically event
Barrier detection with the mechanism such as restart can be with recovery system failure.But this method real-time is poor, does not ensure that system not
It is carried out in the case where operating intermittently immediately fault-tolerant.It is reply single particle effect that circuit-level is fault-tolerant, realizes signal of communication processing module
Instant fault detection and fault-tolerant necessary means.
The essence of the fault-tolerant signal processing of circuit-level is to make processing module in simple grain by introducing redundancy (logic or time)
In the case that sub- effect causes part logic or storage unit to break down, output correct result is remained to.Most common scheme is
For triplication redundancy scheme (Triple Module Redundancy, TMR).Its basic ideas is to replicate original processing module again
Two parts, make three tunnel equal modules while handling input data, when wherein breaking down all the way, output end can be by the way that " majority selects
Select device " output correct result.Since this scheme need to increase by twice of computing resource and power consumption on the original basis, for volume,
It is huge burden for weight and all strictly limited space platform of power.From the perspective of from another side, same system resource limit
Under system, if having used TMR scheme, for system overall process ability by the one third in the case of being reduced to unprotect, this will be big
The processing capacity of big limitation space platform and the diversity of function.In addition, in three traditional mould protection schemes, Viterbi decoding
The global behavior feature of device and the fault-tolerant ability of itself are not efficiently used.
The selective protection scheme for Viterbi decoder proposed in the present invention is guaranteeing the correct of decoding result
Resource overhead is greatly reduced while property.
Summary of the invention
In view of the above-mentioned problems, the purpose of the present invention is to propose to a kind of selective protection schemes for Viterbi decoder.
Viterbi decoder global behavior feature is obtained based on theory analysis and emulation experiment, quantifies the fault-tolerant ability of its own, for
Outside beyond Viterbi decoder fault-tolerant ability range and the module of decoding failure is easy to cause to carry out selective protection, raising is translated
Code accuracy.To achieve the above object, the present invention takes following technical scheme:
A kind of selective protection method based on Viterbi decoder, by FPGA realize Viterbi decoder and based on
On the basis of calculation register bit wide, comprising:
1) selectively protect to Viterbi decoder: the register bit position for being 0 to SEU tolerance uses
The protection of three moulds: two redundancies, storage and former bit position identical information, final result are added simultaneously to all bit positions
It is subject to any two same bits information.
2) have the register bit position of fault-tolerant ability to carry out two mould protections SEU: each all adds corresponding one
Redundancy, storage and former bit position identical information, and a logical AND gate is added hereafter, being with door output result should
By protection bit position final result.
The invention adopts the above technical scheme, which has the following advantages:
(1) the two mode selectivity protection schemes that the present invention uses pay close attention to the fault-tolerant ability of decoder itself, are towards failure
Guard method.It is fault-tolerant for the failure progress beyond itself fault-tolerant ability, reduce overprotection compared with other schemes, provides
Source expense substantially reduces.
(2) the global behavior feature of Viterbi decoder is fully utilized in the present invention.
(3) scheme that proposes is that fault-tolerance approach is studied based on decoding principle in the present invention, therefore and concrete implementation
Mode is unrelated, convenient to combine with other fault-tolerant networks.
Detailed description of the invention
Fig. 1 is Viterbi decoder selective protection scheme implementation flow chart.
Fig. 2 is two mode selectivity protection scheme structure charts.
Specific embodiment
1) convolutional encoding form is (n, k, m), and wherein n is coding output bit information, and k is coding input bit information, m
Indicate the number of shift register in convolution coder.Share 2kmA state, therefore have 2kmSurvivor path information, that is, PM
(PathMetric) value；Each state has 2kBranch, therefore have 2kPath transinformation BM (BranchMetric) value.Input
Sequence length is L bit, into encoder after will be divided into the list entries of one group of every k bit.
LC=n* (L/k) (1)
According to output sequence length L after formula (1) calculation codeC；
PMmax=LC*Amean (2)
The maximum value PM indicated required for the routing information PM register of each branch storage is calculated according to formula (2)max,
AmeanFor the average amplitude of input signal；
Bit wide W required for the register for calculating the corresponding storage PM value information of each state according to formula (3)PM。
Path transinformation BM register bit wide W is calculated according to formula (4)BM, wherein AmaxFor input signal amplitude peak.
Decoder control bit information and other module register bit wide information by searching for mode by can obtain.
It 2) is the register bit of 0 (break down and centainly will lead to final decoding result error) for SEU tolerance
Position carries out three mould protections: two redundancies, storage and former bit position identical information are added simultaneously to all bit positions,
Final result is subject to any two same bits information, to realize the bit position to 100% fault-tolerant ability of SEU；
There is fault-tolerant ability (will not be to final decoding result just there is a certain amount of failure SEU itself
True property has any impact, but the fault-tolerant ability beyond the bit position will lead to the error of decoding result) register bit position
Set and carry out two mould protections: each all adds a corresponding redundancy, for storing information identical with former bit position,
And a logical AND gate is added hereafter, it is this by protection bit position final result with door output result.It is mentioned in this programme
To two moulds protection be only applicable to former bit position information be 0, meet with SEU single-particle bombardment after occur invert become 1.
Realize the purpose that Viterbi decoder error resilience performance is improved with lower expense.
Example 1:
1) convolutional encoding (3,1,6) implements sample for the present invention.Information bit length to be encoded is 54 in encoder, and
Tail of sequence adds 60, and to realize zero code, therefore the message length after coding is L=3* (54+6)=180.According to upper
Stating formula in specific embodiment (1)~(4) and calculating PM, BM register bit wide is respectively 13 (12+1), 8 (7+1), additionally plus 1
Position indicates highest order for representing sign bit.Due to k=1, each step that m=3 is then decoded during decoding has 26=64
A state, each state have 2 respectively1=2 transfer paths are used to find decode during in each step each state it is optimal
Path.
2) Viterbi decoder is realized based on FPGA, entire decoder is mainly by four module compositions: Top
Controller: enable signal totally 23 bit comprising controlling other modules of decoder；PMupdate: every during storage decoding
BM information and as decoding depth information constantly refreshes in the survivor path PM information and Gabi selection module of each state of one step,
The total 13*64=832 bit of PM value register, the total 8*32*4=1024 bit of BM value register；Traceback: storage was recalled
Decoding is as a result, totally 60 bit in journey；BRAM: the register of the stateful survivor path information of institute during the entire decoding of storage is total to
60*64=3840 bit.
3) direct fault location is carried out to decoder based on FPGA platform simulation space Single Event Upset.For SEU tolerance
Bit position for 0: Top Controller module, Traceback module, using the protection scheme of triplication redundancy, it is ensured that reason
By upper 100% fault-tolerant ability；Remaining bit information is to there is certain SEU fault-tolerant ability, and wherein BRAM module is to the fault-tolerant of SEU
It is 100% (theory point that ability, which reaches the register low bit position 99% or more, PM and the fault-tolerant ability of BM register pair SEU,
It analyses and assists verifying the establishment of this conclusion with experiment).From the fault-tolerant protection resource overhead angle of reduction, the protection side of Duplex redundancy
Higher bit position of the case mainly for PM register.
4) during for the Viterbi decoding of soft-decision input, PM value variation the case where leading to final decoding failure, has
Two kinds:
(a) the PM value information of correct path becomes smaller (1 → 0)；(b) the PM value information in incorrect path becomes larger (0 → 1)
Failure assumes 1: storing in two mould registers under non-failure conditions is two 0, wherein being bombarded all the way by SEU
Become 1, by being still 0 with result behind the door, the failure as caused by (b) situation will be avoided by；
Failure assumes 2: storing in two mould registers under non-failure conditions is two 1, wherein being bombarded all the way by SEU
Become 0, by becoming 0 with result behind the door, the failure as caused by (a) situation is not avoided that；
In actual experiment, the probability that situation (a) occurs is 0.5/64=0.7%, using opening after selective protection scheme
Pin reduces by 4.4% relative to traditional triplication redundancy.
Claims (1)
1. a kind of selective protection method based on Viterbi decoder is realizing Viterbi decoder based on FPGA and is calculating
On the basis of register bit wide, comprising:
1) selectively protect to Viterbi decoder: the register bit position for being 0 to SEU tolerance uses three moulds
Protection: two redundancies, storage and former bit position identical information are added simultaneously to all bit positions, final result is to appoint
Subject to two same bits information of anticipating.
2) have the register bit position of fault-tolerant ability to carry out two mould protections SEU: each all adds a corresponding redundancy
Information, storage and former bit position identical information, and a logical AND gate is added hereafter, it is that this is protected with door output result
Protect bit position final result.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1485847A (en) * | 2002-09-24 | 2004-03-31 | 联发科技股份有限公司 | Partial response maximum likelihood system possessing branch estimating equipment |
| US20040122883A1 (en) * | 2002-12-18 | 2004-06-24 | Lee Seok-Jun | High speed add-compare-select circuit for radix-4 Viterbi decoder |
| US20040120427A1 (en) * | 2002-12-18 | 2004-06-24 | Lee Seok-Jun | Branch metric unit duplication for high speed decoder FPGA implementation |
| CN1780153A (en) * | 2004-11-24 | 2006-05-31 | 朱明程 | Universal re-establishable Witby decoding device and method |
| US20100322358A1 (en) * | 2009-06-17 | 2010-12-23 | Drumm David B | Parallel Execution of Trellis-Based Methods |
| CN106559369A (en) * | 2015-09-29 | 2017-04-05 | 晨星半导体股份有限公司 | Sequence estimation device and sequence estimation method |
-
2019
- 2019-06-03 CN CN201910475011.8A patent/CN110166061B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1485847A (en) * | 2002-09-24 | 2004-03-31 | 联发科技股份有限公司 | Partial response maximum likelihood system possessing branch estimating equipment |
| US20040122883A1 (en) * | 2002-12-18 | 2004-06-24 | Lee Seok-Jun | High speed add-compare-select circuit for radix-4 Viterbi decoder |
| US20040120427A1 (en) * | 2002-12-18 | 2004-06-24 | Lee Seok-Jun | Branch metric unit duplication for high speed decoder FPGA implementation |
| CN1780153A (en) * | 2004-11-24 | 2006-05-31 | 朱明程 | Universal re-establishable Witby decoding device and method |
| US20100322358A1 (en) * | 2009-06-17 | 2010-12-23 | Drumm David B | Parallel Execution of Trellis-Based Methods |
| CN106559369A (en) * | 2015-09-29 | 2017-04-05 | 晨星半导体股份有限公司 | Sequence estimation device and sequence estimation method |
Non-Patent Citations (2)
| Title |
|---|
| ZHEN GAO等: "Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders", 《2018 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT)》 * |
| 杨爽: "基于FPGA的CAN接口抗SEU容错方法研究", 《万方数据库》 * |
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