CN1101611C - Controller for static reacance generator - Google Patents

Abstract

The present invention relates to a controller for a static var generator, which comprises an input converter, a storage device, an ordering device, a phase angle regulator, a reference sine voltage generator, a pulse width regulator for the stable voltage protection of a DC bus of a non-constant voltage bridge, a crossing point voltage calculator, a crossing point voltage arbiter, a pulse edge selector for keeping the balance of the voltage of the DC buses of constant voltage bridges, and a bridge drive pulse generator. With the adoption of the controller, the voltage of the DC buses of the bridges connected in series can be still kept stable when output voltage and output current vary rapidly; thereby, the waveform of the output voltage is guaranteed not to be distorted, and the normal work of the controlled static var generator is ensured.

Description

A kind of control device of static reacance generator

Technical field

The invention belongs to a kind of control device of static reacance generator of electric power system realization reactive power compensation, be adapted to be coupled directly to the control device that does not wait dc bus voltage cascaded H bridge pattern SVG device of electrical network especially.

Background technology

The principle of SVG device as shown in Figure 1, Fig. 2 exports the situation of leading reactive current for device, Fig. 3 is the situation of lag output reactive current.The fundamental equation of device is:

V _s＝V _c+jI _cX _s

V in the formula _sBe line voltage, V _cBe SVG device output voltage, I _cBe SVG device output current, X _sImpedance for input inductance.By following formula as can be known, as long as keep the SVG output voltage V _cPress V with net _sSame-phase, then SVG output current and V _sPhase difference is 90 °, i.e. I _cBe pure reactive current, the SVG device sends idle or absorbs idle from electrical network to electrical network.Only need to regulate V _cAmplitude, promptly adjustable apparatus injects the size and the characteristic (perception or capacitive) of the reactive current of electrical network.Work as V _cAmplitude is greater than V _sThe time, the reactive current of output capacitive, opposite then reactive current that output is perceptual.

Fig. 4 is not for waiting dc bus cascaded H bridge pattern SVG schematic diagram of device.Among the figure, each bridge dc bus voltage is unequal, and its jackshaft I, II, III dc bus rated voltage are 2V _d/ 7, the DC link rated voltage of bridge IV is V _d/ 7.The voltage that each H bridge can be exported is+V _Di, O ,-V _Di, V wherein _DiBe its dc bus voltage.With bridge I is example, and as IGBT pipe V11, when V14 opens, this bridge output voltage is+V _Di, and as V13, when V12 opens, this bridge output voltage is-V _Di, when V11, V13 open or V12, V14 when opening simultaneously simultaneously, output voltage is 0.

Table 1 does not wait the tabulation of dc bus voltage cascaded H bridge circuit output voltage

Bridge I output voltage	0	?0	?0	?0	?0	?0	?2V d?/7	?2V d?/7
									Bridge II output voltage	0	?0	?0	?0	?2V d/7	?2V d/7	?2V d?/7	?2V d?/7
Bridge III output voltage	0	?0	?2V d?/7	?2V d?/7	?2V d/7	?2Vdc/ ?7	?2V d?/7	?2V d?/7
									Bridge IV output voltage	0	?V d/7	?0	?V d/7	?0	?V d7	?0	?V d/7
Total output voltage V ao	0	?V d/7	?2V d?/7	?3V d?/7	?4V d/7	?5V d/7	?6V d?/7	?V d

Total output voltage is the stack of each bridge output voltage values, by combination, can realize different total output voltage values.Table 1 has been listed all positive voltages and the no-voltage that circuit shown in Figure 1 can be exported, and adds unlisted negative voltage, can realize 15 kinds of output voltages altogether.These 15 kinds of output voltages enough are used for the desired reference sine wave of match.Staircase waveform is total output voltage V among Fig. 5 _cWaveform, sine wave is a reference sine wave, the bottom is each bridge output voltage waveforms.Total output voltage V _cThe waveform near sinusoidal, have lower harmonic content.

Normal operating condition will keep each cascaded H bridge dc bus voltage stable at device output voltage, electric current when changing, this is the controlled target that will reach.

Device from the active power that electrical network absorbs is:

P _c＝V _cI _ccosΦ

Wherein Φ is V _cWith I _cPhase angle difference.During the ideal operation state, Φ equals 90 °, then P _cEqual zero, device equals zero from the active power that electrical network absorbs, and each bridge dc bus voltage remains unchanged.But in fact, device itself has certain loss, and it is stable to keep each bridge dc bus voltage, must absorb certain active power from electrical network.In addition, the startup stage of device, each cascaded H bridge dc bus voltage also needs to absorb active power from electrical network from the rated voltage that is raised to above freezing.

For a certain reason, as electric current and voltage variation, disturbance, distortion or some transient process etc., each bridge dc bus voltage may be higher or lower than rated value to device in running, and this situation certainly exists.At this moment, just must discharge or absorb active power to electrical network, stable to keep dc bus voltage.

Summary of the invention

The object of the present invention is to provide a kind of control device that does not wait dc bus voltage cascaded H bridge pattern SVG device, output voltage waveforms is the match reference sine wave preferably, output voltage amplitude is identical with outside given amplitude, keeps each bridge dc bus voltage stable.

For reaching above purpose, the technical scheme of taking is: comprising:

An input converter, receiving inputted signal also carries out the A/D conversion in good time;

A memory will store to get off from the signal of input converter;

A sorting unit sorts the dc bus voltage value of the medium breaking the bridge of memory and exports a median U _D

A phase-angle regulator, this phase-angle regulator is according to median U _DAnd etc. the dc bus voltage set-point U of breaking the bridge _D ^*Generate phase angle Φ _C

One with reference to sinusoidal voltage V _C ^*Generator, this generator is according to output voltage amplitude set-point and phase angle Φ _CGenerate total dc bus voltage V _C ^*

Guarantee that anisobaric bridge dc bus voltage keeps stable pulse width regulator (kw) for one, according to the anisobaric bridge dc bus voltage set-point UD in the memory ₄ ^*And anisobaric bridge dc bus voltage value UD ₄Production burst width adjustment COEFFICIENT K w;

An intersection point Voltage Calculator, according to etc. breaking the bridge dc bus voltage median and pulsewidth adjust COEFFICIENT K w, adopts suitable computing formula, calculate the intersection point magnitude of voltage of exporting staircase waveform Vc and reference sine wave.

An intersection point voltage checker, this arbiter compares intersection point magnitude of voltage and reference sine wave voltage in the value of current time, and whether decision changes each bridge driving pulse, and its output comparison signal is delivered to the porch selector;

One make each etc. the breaking the bridge dc bus voltage porch selector of keeping in balance, according to the output comparison signal of intersection point voltage checker, select corresponding bridge;

A bridge drive-pulse generator according to the output of porch selector, is converted to the driving pulse of the corresponding IGBT pipe of selected bridge.

Because the present invention has introduced phase-angle regulator, pulse width regulator and porch selector, wherein the effect of pulse width regulator is make the voltage of dc bus voltage set point that bridge different with other bridges stable, phase-angle regulator is used for keeping the stable of total dc bus voltage, and the effect of porch selector is each bridge dc bus voltage equilibrium of guaranteeing that the dc bus voltage set point is identical.Under the comprehensive function of above-mentioned three adjusters, each the cascaded bridges dc bus voltage that does not wait dc bus voltage cascaded H bridge SVG device held stationary substantially still when the output voltage electric current changes fast, thus guarantee that output voltage waveforms does not distort.

Description of drawings

Fig. 1 is the theory diagram of SVG device;

Fig. 2 exports the situation of leading reactive current for the SVG device;

Fig. 3 is the situation of SVG device lag output reactive current;

Fig. 4 is that directly coupling does not wait dc bus cascaded H bridge pattern SVG device circuit schematic diagram;

Fig. 5 is an output voltage waveforms;

Fig. 6 is a controller scheme block diagram;

Fig. 7 is an output voltage current waveform behind the adding adjuster;

Voltage waveform when Fig. 8 is embodiment output voltage 742V;

Current waveform when Fig. 9 is embodiment output voltage 742V;

Voltage current waveform when Figure 10 is the saltus step of embodiment output voltage;

Bridge I dc bus voltage waveform when Figure 11 is the saltus step of embodiment output voltage;

Bridge IV dc bus voltage waveform when Figure 12 is the saltus step of embodiment output voltage;

Figure 13 is a structure chart of the present invention;

Figure 14 is a software flow pattern.

Embodiment

In order to reach the purpose that discharges or absorb active power to electrical network, holding device output voltage V again _cWith line voltage V _sThe phase place unanimity, and to make V _cSlightly lag or lead is in V _sΦ is less than 90 °, then P _cGreater than zero, device absorbs active power from electrical network, and dc bus voltage rises.Φ is greater than 90 °, P _cLess than zero, device sends active power to electrical network, and dc bus voltage descends.

As mentioned above, by regulating Φ _cCan keep the stable of total dc bus voltage.But it is not enough only keeping total dc bus voltage to stablize, and also must make each bridge dc bus voltage keep stable respectively, and SVG circuit shown in Figure 4 could operate as normal.Each bridge from the active power that electrical network absorbs is

P _i＝V _iI _ccosΦ

V wherein _iBe each bridge output voltage.As shown in Figure 5, each H bridge output voltage waveforms difference, i.e. V _iDifferent.Work as V _c, V _sWhen having phase difference, when promptly Φ is not equal to 90 °, the active power P that each bridge absorbs from electrical network _iDifference, thus the imbalance of each bridge dc bus voltage will be caused, can't operate as normal.Concerning bridge I, II, III, these three bridge output voltage waveforms are similar, if the circuit parameter of three bridges is also identical, solution to the problems described above is very simple.As shown in Figure 5, the method that can take pulse to rotate, promptly each cycle exchange driving pulse once makes three bridges identical from the average power that electrical network absorbs, thereby makes dc bus voltage be consistent.But in the real system, the circuit parameter of three bridges has dispersiveness to be inevitable, and adopts above-mentioned method of simply rotating, and can't guarantee the balance of each bridge dc bus voltage, must adopt more complicated way.Concerning bridge IV, because output voltage waveforms and other three bridges have remarkable difference, circuit parameter inconsistent (the dc bus capacitance is the twice of other bridges), the dc bus rated voltage is half of other three bridges.It is stable to keep its dc bus voltage, also need try every possible means on control method.

Figure 13 is a structure chart of the present invention.Comprise:

An input converter, receiving inputted signal also carries out the A/D conversion in good time;

A memory will store to get off from the signal of input conversion apparatus; Described input converter receive output voltage V c amplitude set-point, etc. breaking the bridge dc bus voltage set-point U _D ^*, anisobaric bridge dc bus voltage set-point UD ₄ ^*, etc. breaking the bridge dc bus voltage value UD ₁, UD ₂, UD ₃, anisobaric bridge dc bus voltage value UD ₄, and convert input signal to digital signal and export in the memory.For the reacance generator of more bridge series connection, the dc bus voltage of its reception comprises the dc bus voltage value of all bridges.

A sorting unit sorts the dc bus voltage value of the medium breaking the bridge of memory and exports a median U _DWith the selection foundation of ranking results as the porch selector, with the median of ordering as feedback quantity, the input variable of calculating as phase-angle regulator.For the reacance generator of more bridges series connection, its dc bus voltage that participates in ordering comprises the dc bus voltage value that does not wait all bridges the voltage bridge except that independent.

A phase-angle regulator, this phase-angle regulator is according to median U _DAnd etc. the dc bus voltage set-point U of breaking the bridge _D ^*Generate phase angle Φ _C

One with reference to sinusoidal voltage V _C ^*Generator, this generator is according to output voltage amplitude set-point and phase angle Φ _CGenerate total dc bus voltage V _C ^*

Guarantee that anisobaric bridge dc bus voltage keeps stable pulse width regulator (KW) for one, according to the anisobaric bridge dc bus voltage set-point UD in the memory ₄ ^*And anisobaric bridge dc bus voltage value UD ₄Production burst width adjustment COEFFICIENT K w;

An intersection point Voltage Calculator, according to etc. breaking the bridge dc bus voltage median and pulsewidth adjust COEFFICIENT K w, adopts suitable computing formula, calculate the intersection point magnitude of voltage of exporting staircase waveform Vc and reference sine wave.

An intersection point voltage checker, this arbiter compares intersection point magnitude of voltage and reference sine wave voltage in the value of current time, and whether decision changes each bridge driving pulse, and its output comparison signal is delivered to the porch selector;

One make each etc. the breaking the bridge dc bus voltage porch selector of keeping in balance, according to the output comparison signal of intersection point voltage checker, select corresponding bridge; Described porch selector adopts following system of selection:

In comparator, compare reference sine wave polarity of voltage and output current polarity;

Breaking the bridge dc bus voltage ordering signal such as in sorting unit, get;

Select breaking the bridge such as corresponding;

The output porch selects signal to the bridge drive-pulse generator.

A bridge drive-pulse generator according to the output of porch selector, is converted to the driving pulse of the corresponding IGBT pipe of selected bridge.

Phase-angle regulator, pulse width regulator and porch selector have been introduced.As Fig. 6, Vc ^*Be the output voltage set-point, provide its amplitude as required by peripheral control unit.UD ^*Be bridge I, II, III dc bus voltage set-point, UD ₄ ^*Be bridge IV dc bus voltage set-point.UD ₁, UD2, UD3, UD ₄Be each bridge dc bus voltage value.The effect of " MID " link is to get the median of UD1, UD2, UD3 as feedback quantity UD." comprehensive 1 " is Φ _cForm link,, adopt adjusting algorithms such as common pi regulator or neuron pi regulator to calculate Φ according to the difference of UD* and UD _cCome Here it is so-called phase regulator." comprehensive 2 " are the formation links that the pulsewidth of bridge IV is adjusted COEFFICIENT K w, according to UD ₄* with UD ₄Difference, adopt common pi regulator to calculate Kw and come, Here it is so-called pulse width regulator." comprehensive 3 " are that reference sine wave Vc* forms link." comprehensive 4 " major function is to produce each bridge output voltage pulse, forms staircase waveform, comes the given Vc* of match output voltage (reference sine wave), in the algorithm of face, has just comprised so-called porch selection algorithm here.In a word, the purpose of entire controller is to make final output voltage waveforms match reference sine wave preferably, and output voltage amplitude is identical with outside given amplitude, and controlled target is to keep each bridge dc bus voltage stable.

The effect of porch selection algorithm be make each etc. the dc bus voltage of breaking the bridge keep in balance.It below is detailed description to its content.

Referring to Fig. 7.The output voltage V of Fig. 7 and Fig. 5 _CAmplitude be the same.Among two figure dotted line corresponding reference sine wave constantly also identical with the value of staircase waveform intersection point voltage.And dotted line the corresponding edge of bridge I, II, III output voltage waveforms just.The difference of two figure is that bridge II is different with the output waveform of bridge III.Carefully see both differences, exchange has been done in the trailing edge position that is actually both.If the leading electric current I of SVG device output this moment _c, as shown in Figure 7, then for each cascaded H bridge, in this following period of time of dashdotted left side, electrical network charges to the dc bus capacitor.In this following period of time on chain-dotted line right side, the dc bus capacitor discharges to electrical network.Through half period, bridge I, II, III dc tache voltage variable quantity are: ${\mathrm{\ΔU}}_{\mathrm{di}}=\frac{1}{C_i}({\∫}_0^{t_1}{i}_c\mathrm{dt}+{\∫}_1^{t_2}{i}_c\mathrm{dt})$

T wherein ₀For corresponding bridge rise of output voltage along moment corresponding, t ₁Be chain-dotted line moment corresponding, t ₂Be corresponding bridge output voltage trailing edge moment corresponding, C _iBe corresponding bridge dc bus capacitance.When the output voltage symmetry, voltage variety Δ U _Di=0.Work as t ₁-t ₀＞t ₂-t ₁The time, Δ U _Di＞0.Work as t ₁-t ₀＞t ₂During-t1, Δ U _Di＜0.As shown in Figure 7, through half period, bridge III dc bus voltage will rise to some extent, and bridge II dc bus descends to some extent, and bridge I dc bus voltage no change.As seen, as long as according to each bridge dc bus voltage size sequence, dotted line moment corresponding in Fig. 7, choose reasonable each etc. breaking the bridge output positive voltage, negative voltage or no-voltage, the bridge that the low bridge of dc bus voltage charges, voltage is high is charged less, just can keep the balance of bridge I, II, III dc bus voltage.It should be noted that the moment to be selected can only be a dotted line moment corresponding among Fig. 7, could guarantee that so total output voltage waveforms does not distort substantially.Here it is so-called edge selection algorithm.

To compare decision bridge driving pulse with reference to the output valve of the sinusoidal voltage generator intersection point magnitude of voltage corresponding with each bridge driving pulse edge of intersection point Voltage Calculator gained:

Reference sine wave voltage computing formula is V _C ^*=V _Cm ^*Sin (314t+ φ _c), Vcm is outside given output voltage amplitude, Φ c is the output of phase-angle regulator.The computing formula of intersection point Voltage Calculator is: $V_{\mathrm{stairn}}=\frac{{\mathrm{nUD}}^{*}}{2}+\mathrm{mod}\left(\frac{n}{2}\right)\frac{{\mathrm{UD}}^{*}}{K_W}$ ，1≤n≤7， $0\&le;t<\frac{\mathrm{\&pi;}}{2}$ The time $V_{\mathrm{stairn}}=\frac{{\mathrm{nUD}}^{*}}{2}+\mathrm{mod}\left(\frac{n}{2}\right)K_W{\mathrm{UD}}^{*}$ , 1≤n≤7, when $\frac{\mathrm{\&pi;}}{2}\&le;t_i<\mathrm{\&pi;}$ The time

In the formula, UD ^*For etc. breaking the bridge dc bus voltage instruction.N is the sequence number at each bridge driving pulse edge, and contrast Fig. 6 respectively has 7 porches, as can be known so the value of n is 1 to 7 on the chain-dotted line both sides.Kw is that pulsewidth is adjusted coefficient.After calculating good each bridge driving pulse edge corresponding reference magnitude of voltage (being staircase waveform and reference sine wave intersection point magnitude of voltage), sinusoidal reference magnitude of voltage and these values with current time compares again.When just crossing a certain intersection point magnitude of voltage as current reference voltage level, then the driving pulse level of certain bridge will change.Contrast Fig. 6, the porch of non-in the drawings dotted line correspondence has only the driving pulse level of bridge IV to overturn, and handles comparatively simple.And for the porch of dotted line correspondence among the figure, then not only the driving pulse level of bridge IV will overturn, and the driving pulse level of other a certain bridges also will overturn.As for specifically being which bridge overturns, then decide by the porch selector.In the porch selector, at first compare reference sine wave polarity of voltage and output current polarity, both are identical then to think to be between charging zone, ensuing program is just according to the bridge I, the II that obtain in sorting unit, the ordering of III dc bus voltage, select the driving pulse of the low bridge of voltage open earlier, open behind the driving pulse of the bridge that voltage is high.If sync direction is opposite with output current polarity, then the method for Xuan Zeing is opposite.

The effect of pulse width regulator is make anisobaric bridge dc bus voltage stable.Concerning bridge IV, because output voltage waveforms and other three bridges have remarkable difference, circuit parameter inconsistent (the dc bus capacitance is the twice of other bridges), the dc bus rated voltage is half of other three bridges.It is stable to keep its dc bus voltage, and the basic principle of employing is with aforementioned consistent, promptly charges and discharge electric weight keep voltage and stablize in one-period by adjusting its dc bus capacitor.Comparison diagram 5 and Fig. 7 jackshaft IV output voltage waveforms find that the waveform among Fig. 5 is symmetrical.And the waveform among Fig. 7, the pulse width on the peak pulse duration right side on the left of chain-dotted line.Such result is that through after the half period, the voltage of bridge IV dc bus descends to some extent.If make the pulsewidth in left side be wider than the pulsewidth on right side, then pass through half period after, the voltage of bridge IV dc bus will rise to some extent.For this reason, the special pulsewidth of introducing is adjusted COEFFICIENT K w, in aforementioned intersection point Voltage Calculator formula, has embodied the effect of Kw.Adjust this coefficient according to bridge IV dc bus voltage again and reach that to keep dc bus voltage be the purpose of rated value.It should be noted that equally to avoiding total output voltage waveforms that too big distortion takes place, thereby cause that the harmonic current that injects electrical network increases, and must follow a principle.Promptly when adjusting bridge IV output voltage pulsewidth, the edge constantly corresponding with dotted line among Fig. 7 should remain unchanged.Here it is so-called pulse width regulator.

Described phase-angle regulator generates phase angle as follows:

φ _c(t)＝K ₁e ₁(t)+w ₁(t-1)

w ₁(t)＝w ₁(t-1)+K ₁e ₁(t)-K _p1e ₁(t)

Wherein: e ₁(t) breaking the bridge dc bus voltage set-point UD such as be ^*With each etc. the difference of breaking the bridge dc bus voltage median, w ₁(t) be integral, φ _c(t) be the output of phase-angle regulator, K ₁, kp ₁Be constant coefficient.In an embodiment, K ₁Get 0.005, kp ₁, get 0.02.

Described pulse width regulator is production burst adjustment factor Kw as follows:

K _w(t)＝K ₂e ₂(t)+w ₂(t-1)

w ₂(t)＝w ₂(t-1)+K ₂e ₂(t)-K _p2e ₂(t)

Wherein: e ₂(t) be anisobaric bridge dc bus voltage UD4 ^*With the difference of set-point UD, W ₂(t) be integral, Kw (t) is the output of pulse width regulator, k ₂, kp ₂Be constant coefficient.In an embodiment, k ₂Get 0.08, kp ₂Get 0.08.

The phase-angle regulator of present embodiment and pulse width regulator can also be realized with methods such as analog regulator or MN pi regulators:

Figure 14 is a software flow pattern.Carry out A/D conversion earlier, obtain the signal that each bridge dc bus voltage etc. needs.Get etc. in the breaking the bridge dc bus voltage median and rated value relatively, by aforementioned Φ _cAdjuster calculates Φ _cAgain according to reference sinusoidal voltage value and Φ _cConcern V _C ^*=V _CmSin (314t+ φ _c) calculate with reference to sinusoidal voltage value Vc.Dc bus voltage according to independent anisobaric bridge calculates Kw by the Kw adjuster, adopts the intersection point calculation formula to calculate the intersection point voltage of output staircase waveform and reference sine wave.When the value of reference sine wave is crossed the intersection point corresponding with bridge I, II, III, select corresponding bridge according to the porch selection algorithm, change its output voltage values, make output voltage increase or reduce a ladder.When the value of reference sine wave is crossed other intersection points, then change bridge IV output voltage values, make output voltage increase or reduce a ladder.

The embodiment result of the test has been verified the correctness of the controlling schemes that is adopted.

In the process of the test, device starts steadily not have and impacts, and output voltage, current waveform are uniform and stable.Fig. 8 output voltage waveforms, Fig. 9 are corresponding current waveform.Sinusoidal voltage shown in the CH2 is to press synchronous synchronization waveform with net among the figure.

Figure 10 (a) is the voltage current waveform of output voltage when the ceiling voltage saltus step is minimum voltage.Figure 10 (b) is the voltage current waveform of output voltage when minimum voltage 458V saltus step is ceiling voltage 742V.Figure 11 (a) is an output voltage by high-situation of bridge I dc bus during low saltus step, Figure 11 (b) be output voltage by low-during the Gao saltus step bridge I dc bus situation of change.From figure, overshoot is about 10%, and the adjustment time is about 5S.Figure 12 (a) is high-situation of change of bridge IV dc bus voltage during low saltus step, and Figure 12 (b) is low-situation of change of bridge IV dc bus voltage during the Gao saltus step.From figure, overshoot almost be can't see, and this is owing to introduced pulse-width modulation COEFFICIENT K w, the cause that response speed is increased.Test waveform from Figure 11, Figure 12, can reach a conclusion, adopt the described controlling schemes of the art of this patent file, each the cascaded bridges dc bus voltage that does not wait dc bus voltage cascaded H bridge SVG device held stationary substantially still when the output voltage electric current changes fast, thereby guarantee that output voltage waveforms does not distort the assurance device operate as normal.

Claims (6)

1, a kind of control device of static reacance generator is characterized in that comprising:

An input converter, receiving inputted signal also carries out the A/D conversion in good time;

A memory will store to get off from the signal of input converter;

A sorting unit sorts the dc bus voltage value of the medium breaking the bridge of memory and exports a median (U _D);

A phase-angle regulator, this phase-angle regulator is according to median (U _D) and etc. the dc bus voltage set-point (U of breaking the bridge _D ^*) generation phase angle (Φ _C);

A reference sine wave generator, this generator is according to output voltage amplitude set-point and phase angle (Φ _C) the total dc bus voltage (V of generation _C ^*);

Guarantee that anisobaric bridge dc bus voltage keeps stable pulse width regulator (KW) for one, according to the anisobaric bridge dc bus voltage set-point (UD in the memory ₄ ^*) and anisobaric bridge dc bus voltage value (UD ₄) production burst width adjustment coefficient (Kw);

An intersection point Voltage Calculator, according to etc. breaking the bridge dc bus voltage median and pulsewidth adjust coefficient (Kw), obtain the intersection point magnitude of voltage of output staircase waveform (Vc) and reference sine wave;

An intersection point voltage checker, this arbiter compares intersection point magnitude of voltage and reference sine wave voltage in the value of current time, and its output comparison signal is delivered to the porch selector;

One make each etc. the breaking the bridge dc bus voltage porch selector of keeping in balance, according to the output comparison signal of intersection point voltage checker, select corresponding bridge;

A bridge drive-pulse generator according to the output of porch selector, is converted to the driving pulse of the corresponding IGBT pipe of selected bridge.

2, the control device of a kind of static reacance generator as claimed in claim 1 is characterized in that described input converter receives output voltage set-point (U _C ^*), etc. breaking the bridge dc bus voltage set-point (U _D ^*), anisobaric bridge dc bus voltage set-point (UD ₄ ^*), etc. breaking the bridge dc bus voltage value (UD ₁), (UD ₂), (UD ₃), anisobaric bridge dc bus voltage value (UD ₄), output current signal (Ic), and convert input signal to digital signal and export in the memory.

3, the control device of a kind of static reacance generator as claimed in claim 1, it is characterized in that described sorting unit will receive etc. breaking the bridge dc bus voltage value (UD ₁), (UD ₂), (UD ₃) sort and input to porch selector and phase-angle regulator.

4, the control device of a kind of static reacance generator as claimed in claim 1 is characterized in that described intersection point Voltage Calculator adopts following formula to calculate the staircase voltage of reacance generator output and the intersection point voltage of reference sine wave voltage: $V_{\mathrm{stairn}}=\frac{{\mathrm{nUD}}^{*}}{2}+\mathrm{mod}\left(\frac{n}{2}\right)\frac{{\mathrm{UD}}^{*}}{K_W}$ ，1≤n≤7， $0\&le;t<\frac{\mathrm{\&pi;}}{2}$ The time $V_{\mathrm{stairn}}=\frac{{\mathrm{nUD}}^{*}}{2}+\mathrm{mod}\left(\frac{n}{2}\right)K_w{\mathrm{UD}}^{*}$ , 1≤n≤7, when $\frac{\mathrm{\&pi;}}{2}\&le;t_i<\mathrm{\&pi;}$ In the up-to-date style, UD ^*For etc. breaking the bridge dc bus voltage instruction, n be the sequence number at each bridge driving pulse edge, Kw is a pulsewidth adjustment coefficient.

5, the control device of a kind of static reacance generator as claimed in claim 1 is characterized in that described phase-angle regulator generates phase angle as follows:

φ _c(t)＝K ₁e ₁(t)+w ₁(t-1)

w ₁(t)＝w ₁(t-1)+K ₁e ₁(t)-K _p1e ₁(t)

Wherein: e ₁(t) breaking the bridge dc bus voltage set-point (UD such as be ^*) with each etc. the difference of breaking the bridge dc bus voltage median, w ₁(t) be integral, φ _c(t) be the output of phase-angle regulator, K ₁, kp ₁Be constant coefficient.

6, the control device of a kind of static reacance generator as claimed in claim 1 is characterized in that described pulse width regulator (Kw) generates phase angle as follows:

K _w(t)＝K ₂e ₂(t)+w ₂(t-1)

w ₂(t)＝w ₂(t-1)+K ₂e ₂(t)-K _p2e ₂(t)

Wherein: e ₂(t) be anisobaric bridge dc bus voltage (UD4 ^*) with the difference of set-point (UD), W ₂(t) be integral, Kw (t) is the output of pulse width regulator, k ₂, kp ₂Be constant coefficient.

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