CN110138380B - Power-down time monitoring circuit and method - Google Patents
Power-down time monitoring circuit and method Download PDFInfo
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- CN110138380B CN110138380B CN201910411628.3A CN201910411628A CN110138380B CN 110138380 B CN110138380 B CN 110138380B CN 201910411628 A CN201910411628 A CN 201910411628A CN 110138380 B CN110138380 B CN 110138380B
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- 238000012544 monitoring process Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims abstract description 45
- 238000001514 detection method Methods 0.000 claims abstract description 21
- 238000006243 chemical reaction Methods 0.000 claims abstract description 15
- 238000012545 processing Methods 0.000 claims abstract description 5
- 238000004146 energy storage Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
- H03K21/403—Arrangements for storing the counting state in case of power supply interruption
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
- Measurement Of Current Or Voltage (AREA)
Abstract
A power down time monitoring circuit, the circuit comprising: the capacitor comprises a core circuit formed by a holding capacitor C0 and a charge-discharge control circuit, an analog-digital conversion or voltage detection circuit which is responsible for converting the capacitor voltage into time output, and a time display or execution circuit which is responsible for subsequent processing. The invention realizes continuous monitoring of the power failure time under the condition of no power supply, provides a novel power supply monitoring method, monitors whether the power-down-power-up interval of the chip exceeds a certain range, and has the advantages of low power consumption and low cost. The invention can be applied to power supply monitoring, safety protection, goods checking and other occasions needing to keep information within a specified time after power failure, such as access refusing, access allowing and the like. Therefore, the invention can save the expenditure of the standby battery or the energy storage capacitor, improve the flexibility and the reliability of the power failure monitoring system and create conditions for developing new security and monitoring applications.
Description
Technical Field
The invention relates to a power-down time monitoring circuit and method, and belongs to the technical field of power-down time monitoring.
Background
The conventional time monitoring circuit needs a clock source and a counting circuit to realize timing, and the schematic diagram is shown in fig. 1, but after the monitoring circuit is powered down, if the standby power supply or the large capacitor support is not available, the clock and the counting cannot be maintained, so that the power down time cannot be effectively monitored.
In view of the above-mentioned technical problems, a number of patent documents are disclosed in the art:
the method, system and device for recording the power-down time of the microcomputer relay protection device disclosed in the chinese patent document CN106354119a are to record the power-down time, and require to continuously perform the operation of writing the current time when the power is not turned off, and require a memory, a time signal and a memory writing control circuit, and always have power consumption, and further require to obtain the current time signal from the outside after power-up.
The power failure processing method and device disclosed in the chinese patent document CN109144832a also need a non-volatile memory and provide a time signal, and write the current time into the non-volatile memory when power is lost, and particularly indicate that an energy storage and discharge module is needed when power is lost, so as to supply power to the information writing and storing device.
The driving control circuit, driving control method and display device disclosed in chinese patent document CN109215559a relate to a driving control and display circuit, and are aimed at avoiding the display failure such as black screen or dead halt when the power is turned on again before the power is turned off to 0V (if the power is not turned off to 0V). Among these, a so-called power-down time acquisition circuit is used, which is based on the principle that the time required for VIN to decrease is estimated by recording the time interval in which VIN decreases from a specific voltage V1 to a specific voltage V2, and the conduction of the power-on switch is controlled by this time. Therefore, the power-down time acquisition (prediction/calculation) referred to in the literature refers to the time required for the power-down waveform of a specific external power supply voltage to be passively predicted (acquired) for the power supply to be powered down to 0V under normal conditions, and in addition, the literature also needs the coordination of an external clock or a time signal; when power is lost, it requires additional calculation circuitry to perform the calculation.
In summary, in the prior art, the general circuit cannot monitor the self-power-down time or other events occurring during the power-down period without the backup power source, such as a battery or a large capacitor.
Disclosure of Invention
Aiming at the defects of the prior art, the invention discloses a power failure time monitoring circuit.
The invention also discloses a working method of the power failure time monitoring circuit.
Summary of The Invention
The invention utilizes specific internal capacitance, specific charging voltage and specific leakage to generate standard discharging waveform, and is matched with a voltage comparison circuit to judge the power-down time length. In the invention, the holding capacitor is charged to a certain voltage in the power-on state, and the capacitor is continuously and slowly discharged by means of leakage current after the circuit is powered down, and the voltage on the holding capacitor is gradually reduced along with the time. As can be seen from the above, different capacitor voltages correspond to different power-down times, i.e. when the circuit is powered up again, the length of the duration of the power-down time, such as a specific time value or time interval, can be determined by detecting the voltage on the holding capacitor.
The technical scheme of the invention is as follows:
a power down time monitoring circuit, the circuit comprising: the capacitor comprises a core circuit formed by a holding capacitor C0 and a charge-discharge control circuit, an analog-to-digital conversion (ADC) or voltage detection circuit which is responsible for converting the capacitor voltage into time output, and a time display or execution circuit which is responsible for subsequent processing. As shown in fig. 2.
According to the invention, the core circuit comprises a bistable trigger formed by a gate circuit, wherein the R end of the bistable trigger is connected with the output end of a first OR gate I9, one input end of the first OR gate I9 is connected with the POR signal input end through a first inverting amplifier I7, the other input end of the first OR gate I9 is connected with the POR signal input end, and the S end of the bistable trigger is connected with the SET signal input end;
one input end of the first OR gate I9 is connected with a switching device, the holding capacitor CO and an analog-to-digital conversion or voltage detection circuit through a second inverting amplifier I14 and a third OR gate I13;
the analog-to-digital conversion or voltage detection circuit is connected with the display or execution circuit.
According to a preferred embodiment of the present invention, the switching device is a MOS switch.
Preferably, according to the present invention, the bistable flip-flop is a nor gate RS flip-flop.
The working method of the power down time monitoring circuit is characterized by comprising the following steps: when the monitored circuit is powered up again after power is lost, the duration of the power loss time is monitored, the interval in which the duration of the power loss time falls is given, and corresponding operation is adopted.
The invention has the technical advantages that:
the invention realizes continuous monitoring of the power failure time under the condition of no power supply, provides a novel power supply monitoring method, monitors whether the power-down-power-up interval of the chip exceeds a certain range, and has the advantages of low power consumption and low cost.
The invention can be applied to power supply monitoring, safety protection, goods checking and other occasions needing to keep information within a specified time after power failure, such as access refusing, access allowing and the like. Therefore, the invention can save the expenditure of the standby battery or the energy storage capacitor, improve the flexibility and the reliability of the power failure monitoring system and create conditions for developing new security and monitoring applications.
Drawings
FIG. 1 is a schematic circuit diagram of a conventional timing circuit;
FIG. 2 is a schematic circuit diagram of a power down time monitoring circuit of the present invention;
FIG. 3 is a schematic circuit diagram of a power down time monitoring circuit in an embodiment of the invention;
in fig. 2, 3, wherein CLR is the CLR signal input; PCR is a PCR signal input end; the SET is a SET signal input end; DET_Signal is the DET_Signal Signal output; i6 is a first and gate; i7 is a first inverting amplifier; i9 is a first or gate; i10 and I11 are two not gates in a nor gate RS flip-flop; i12 second or gate; i13 is a third or gate; i14 is a second inverting amplifier; SW1 is a MOS switch; comp_0 is a comparator chip; CO is the holding capacitance; r2 is a second resistor; r3 is a first resistor.
Detailed Description
The following is a detailed description, but is not limited to, with reference to the examples and the accompanying drawings.
Example 1,
As shown in fig. 2.
A power down time monitoring circuit, comprising: the capacitor comprises a core circuit formed by a holding capacitor C0 and a charge-discharge control circuit, an analog-to-digital conversion (ADC) or voltage detection circuit which is responsible for converting the capacitor voltage into time output, and a time display or execution circuit which is responsible for subsequent processing. As shown in fig. 2.
The core circuit comprises a bistable trigger formed by a gate circuit, wherein the R end of the bistable trigger is connected with the output end of a first OR gate I9, one input end of the first OR gate I9 is connected with the POR signal input end through a first phase-inverting amplifier I7, the other input end of the first OR gate I9 is connected with the POR signal input end, and the S end of the bistable trigger is connected with the SET signal input end;
one input end of the first OR gate I9 is connected with a switching device, the holding capacitor CO and an analog-to-digital conversion or voltage detection circuit through a second inverting amplifier I14 and a third OR gate I13;
the analog-to-digital conversion or voltage detection circuit is connected with the display or execution circuit.
The switching device is a MOS switch.
The bistable flip-flop is a nor gate RS flip-flop.
As shown in fig. 3, which is a preferred example of the present embodiment, the R terminal of the bistable flip-flop is connected to the output terminal of the first or gate I9, one input terminal a of the first or gate I9 is connected to the output terminal Y of the first or gate I6 and is connected to the holding capacitor C0 and the detection circuit through the second inverting amplifier I14 and the third or gate I13, respectively, one input terminal a of the first or gate I6 is a CLR signal input terminal, and the first inverting amplifier I7 is connected between the other input terminal B of the first or gate I6 and the other input terminal B of the first or gate I9, while the other input terminal B of the first or gate I9 is a POR signal input terminal; the S end of the bistable trigger is connected with the output end of a second OR gate I12, one input end A of the second OR gate I12 is connected with the SET signal input end, and the other input end B of the second OR gate I12 is connected with the DET_signal signal output end;
the positive input end of the comparator chip COMP_0 is connected with the core circuit through a switching device, and the output end of the comparator chip COMP_0 is connected with the DET_signal signal output end.
The positive input end of the comparator chip comp_0 is grounded through a holding capacitor C0, and the negative input end of the comparator chip comp_0 is connected with the chip working voltage VDD through a first resistor R3 and is grounded through a second resistor R2.
EXAMPLE 2,
The method for operating the power down time monitoring circuit of embodiment 1, comprising:
when the monitored circuit is powered on again after power failure, the duration of the power failure is monitored, the interval in which the duration of the power failure falls is given, corresponding operation is adopted, and whether the power failure time exceeds the preset time T0 is determined: if T0 is exceeded, the flag signal DET_s ignal signal will be cleared.
The independent power down monitoring period comprises the following steps: first power-up, power-down and power-up again; setting a reference voltage VREF 0=vdd-I0T 0/C0; the CLR signal of the CLR input end is used for resetting the detection circuit, the POR signal of the POR input end is output by the power-on reset circuit, and the normal power-on state is 0;
at first power up: CLR signal input terminal clr=0, by adding a positive pulse to SET signal input terminal, MOS switch SW1 is turned on to charge holding capacitor C0 to VDD, and since VDD > VREF0, analog conversion or voltage detection circuit outputs det_s ignal high level; the high level is fed back to the control end of the MOS switch SW1 through the control circuit, so that the MOS switch SW1 is always in an on state;
after power failure: the MOS switch SW1 is turned off, and the charge on the holding capacitor is discharged through the first resistor of the MOS switch SW1 and the leakage current on the second resistor;
when powered up again: comparing the upper voltage of the holding capacitor with a reference voltage VREF0, when VC
< VREF0, the power down duration is determined to exceed T0, so the analog conversion or voltage detection circuit output programming det_signal Signal will be cleared.
The specific circuit shown in fig. 3 functions as a flag signal, and when the power-down time does not exceed a certain range, the flag signal automatically recovers after the power-up again. The description is as follows: in the power-up situation, the capacitor is charged to vdd through the SET Signal input terminal, and the flag Signal det_signal is SET since the preset reference voltage vref < vdd. Once the circuit is powered down, the holding capacitor voltage will drop over time. When the circuit is powered up again, the circuit compares the holding capacitance upper voltage with a preset reference voltage vref: if the power-down time is longer than the preset time, the voltage on the capacitor is lower than vref, and the comparator chip outputs 0, namely the flag signal is cleared; if the power-down time does not exceed the preset time, the voltage on the capacitor is higher than vref, the comparator chip outputs a high level, and meanwhile, the capacitor is kept full through the feedback circuit, namely, the state before power-down is restored.
In the two embodiments described above, it can be seen that:
the conventional time detection circuit needs a clock source and a counting circuit to count time, as shown in fig. 1, if the circuit is powered down, the pulse and the count cannot be maintained without the support of a standby power supply or a storage capacitor, so that the time cannot be detected.
However, the invention can continuously monitor the power-down time after power-down by utilizing the leakage characteristics of the capacitor and the device, and can judge the power-down time when the circuit is powered up again. The invention has the characteristics of continuous timing without power supply after power failure, not only can simplify the design of a power failure monitoring system, save the expenditure of a standby battery and an energy storage capacitor, improve the flexibility and the reliability of the power failure detecting system, but also can create conditions for developing new monitoring and security protection applications.
Although the present invention has been described with reference to specific examples, the description of the examples does not limit the scope of the invention. Various modifications and combinations of the embodiments can be readily made by those skilled in the art, without departing from the spirit and scope of the invention, by reference to the description of the invention.
Claims (3)
1. A power down time monitoring circuit, the circuit comprising: a core circuit formed by a holding capacitor C0 and a charge-discharge control circuit, an analog-digital conversion or voltage detection circuit for converting the capacitor voltage into time output, and a time display or execution circuit for subsequent processing;
the core circuit comprises a bistable trigger formed by a gate circuit, wherein the R end of the bistable trigger is connected with the output end of a first OR gate I9, one input end of the first OR gate I9 is connected with the POR signal input end through a first phase-inverting amplifier I7, the other input end of the first OR gate I9 is connected with the POR signal input end, and the S end of the bistable trigger is connected with the SET signal input end;
one input end of the first OR gate I9 is connected with a switching device, the holding capacitor CO and an analog-to-digital conversion or voltage detection circuit through a second inverting amplifier I14 and a third OR gate I13;
the analog-to-digital conversion or voltage detection circuit is connected with the display or execution circuit;
the switching device is a MOS switch;
the bistable flip-flop is a nor gate RS flip-flop.
2. A power down time monitoring circuit, the circuit comprising: a core circuit formed by a holding capacitor C0 and a charge-discharge control circuit, an analog-digital conversion or voltage detection circuit for converting the capacitor voltage into time output, and a time display or execution circuit for subsequent processing;
the core circuit comprises a bistable trigger formed by a gate circuit, wherein the R end of the bistable trigger is connected with the output end of a first OR gate I9, one input end A of the first OR gate I9 is connected with the output end Y of a first NOT gate I6 and is respectively connected with the holding capacitor C0 and the detection circuit through a second inverting amplifier I14 and a third OR gate I13, one input end A of the first NOT gate I6 is a CLR signal input end, a first inverting amplifier I7 is connected between the other input end B of the first NOT gate I6 and the other input end B of the first OR gate I9, and the other input end B of the first OR gate I9 is a POR signal input end; the S end of the bistable trigger is connected with the output end of a second OR gate I12, one input end A of the second OR gate I12 is connected with the SET signal input end, and the other input end B of the second OR gate I12 is connected with the DET_signal signal output end;
the positive input end of the comparator chip COMP_0 is connected with the core circuit through a switching device, and the output end of the comparator chip COMP_0 is connected with the DET_signal signal output end;
the positive input end of the comparator chip comp_0 is grounded through a holding capacitor C0, and the negative input end of the comparator chip comp_0 is connected with the chip working voltage VDD through a first resistor R3 and is grounded through a second resistor R2.
3. A method of operating a power down time monitoring circuit according to claim 2, wherein,
when the monitored circuit is powered on again after power failure, the duration of the power failure is monitored, the interval in which the duration of the power failure falls is given, corresponding operation is adopted, and whether the power failure time exceeds the preset time T0 is determined: if T0 is exceeded, the flag signal DET_Signal signal will be cleared;
the independent power down monitoring period comprises the following steps: first power-up, power-down and power-up again; setting a reference voltage VREF 0=vdd-I0T 0/C0; the CLR signal of the CLR input end is used for resetting the detection circuit, the POR signal of the POR input end is output by the power-on reset circuit, and the normal power-on state is 0;
at first power up: CLR Signal input terminal clr=0, by adding a positive pulse to SET Signal input terminal, MOS switch SW1 is turned on to charge holding capacitor C0 to VDD, and since VDD > VREF0, analog conversion or voltage detection circuit outputs det_signal high level; the high level is fed back to the control end of the MOS switch SW1 through the control circuit, so that the MOS switch SW1 is always in an on state;
after power failure: the MOS switch SW1 is turned off, and the charge on the holding capacitor is discharged through the first resistor of the MOS switch SW1 and the leakage current on the second resistor;
when powered up again: comparing the upper voltage of the holding capacitor with a reference voltage VREF0, and judging that the power-down duration exceeds T0 when VC < VREF0, so that the output programming DET_Signal Signal of the analog conversion or voltage detection circuit is cleared;
the R end of the bistable trigger is connected with the output end of a first OR gate I9, one input end A of the first OR gate I9 is connected with the output end Y of a first OR gate I6 and is respectively connected with the holding capacitor C0 and the detection circuit through a second inverting amplifier I14 and a third OR gate I13, one input end A of the first OR gate I6 is a CLR signal input end, a first inverting amplifier I7 is connected between the other input end B of the first AND gate I6 and the other input end B of the first OR gate I9, and the other input end B of the first OR gate I9 is a POR signal input end; the S end of the bistable trigger is connected with the output end of a second OR gate I12, one input end A of the second OR gate I12 is connected with the SET signal input end, and the other input end B of the second OR gate I12 is connected with the DET_signal signal output end;
the positive input end of the comparator chip COMP_0 is connected with the core circuit through a switching device, and the output end of the comparator chip COMP_0 is connected with the DET_signal signal output end;
the positive input end of the comparator chip comp_0 is grounded through a holding capacitor C0, and the negative input end of the comparator chip comp_0 is connected with the chip working voltage VDD through a first resistor R3 and is grounded through a second resistor R2.
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| CN113109738B (en) * | 2021-03-15 | 2023-08-04 | 苏州汇川技术有限公司 | Power-down time detection circuit and power-down time detection system |
| CN114325481B (en) * | 2021-12-29 | 2023-10-31 | 深圳市欧瑞博科技股份有限公司 | Power-off duration detection method and device, electronic equipment and storage medium |
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Denomination of invention: A power outage time monitoring circuit and method Granted publication date: 20230804 Pledgee: Huaxia Bank Co.,Ltd. Jinan Branch Pledgor: SHANDONG HUAYI MICRO-ELECTRONICS Co.,Ltd. Registration number: Y2024980024862 |