CN110138380A - A kind of power down time observation circuit and method - Google Patents
A kind of power down time observation circuit and method Download PDFInfo
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- CN110138380A CN110138380A CN201910411628.3A CN201910411628A CN110138380A CN 110138380 A CN110138380 A CN 110138380A CN 201910411628 A CN201910411628 A CN 201910411628A CN 110138380 A CN110138380 A CN 110138380A
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- 238000000034 method Methods 0.000 title claims abstract description 13
- 239000003990 capacitor Substances 0.000 claims abstract description 37
- 238000012544 monitoring process Methods 0.000 claims abstract description 11
- 238000006243 chemical reaction Methods 0.000 claims abstract description 10
- 238000012545 processing Methods 0.000 claims abstract description 5
- 238000001514 detection method Methods 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
- H03K21/403—Arrangements for storing the counting state in case of power supply interruption
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Measurement Of Current Or Voltage (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
A kind of power down time observation circuit, it is characterized in that, the circuit includes: core circuit, the responsible time showing or execution circuit by analog-to-digital conversion or voltage detecting circuit and responsible subsequent processing that convert of capacitor to voltage is time output that holding capacitor C0 and charge-discharge control circuit are constituted.The present invention realizes in the case where no power supply power supply and continues to monitor to power down time, provides a kind of new method for monitoring power supply, powers on whether interval is monitored more than a certain range to electricity-under chip, the advantage with low-power consumption, low cost.It is checked present invention can apply to power supply monitoring, safeguard protection, cargo and other needs keeps the occasion of information in the stipulated time after a power failure, such as denied access, allow to access situation.Therefore using the expense that can save reserve battery or storage capacitor after the present invention, the flexibility and reliability of down Monitor Unit system are improved, to start new security protection, monitoring application creates conditions.
Description
Technical field
The present invention relates to a kind of power down time observation circuit and methods, belong to the technical field of power down time monitoring.
Background technique
Traditional time supervision circuit needs a clock source and a counting circuit to realize timing, schematic diagram such as attached drawing 1
It is shown, but after observation circuit power down itself, if supported without backup power source or bulky capacitor, clock and counting are all without Faville
It holds, so can not effectively be monitored to power down time.
For the above technical problems, art discloses multiple patent documents:
The recording method of microcomputer protective relay device power down time, system disclosed in Chinese patent literature CN106354119A and
Device is to need constantly to carry out to be written the operation of current time in non-power down in order to record power down time, need storage
Device, time signal and memory write control circuit simultaneously have always power consumption, and also to need to be worked as from outside after powering on
Preceding time signal.
A kind of power supply power-fail processing method and processing device disclosed in Chinese patent literature CN109144832A is also required to non-easily deposit
Reservoir simultaneously provides time signal, non-easy memory is written in current time during power down, and illustrate and need to store up during power down
Energy and discharge module are written for above- mentioned information and store equipment power supply.
Drive control circuit disclosed in Chinese patent literature CN109215559A, drive control method and display device are related to
A kind of drive control and display circuit, the purpose is to for avoid re-powering before power supply power-fail to 0V (if not dropping to 0V,
Power on again display will appear blank screen or crash etc. display it is bad).It wherein uses so-called power down time and obtains circuit, principle is to pass through
It records VIN and drops to the time interval of specific voltage V2 from specific voltage V1 to calculate that VIN reduces the required time, and use this
The conducting of a time control upper electrical switch.So power down time signified in document obtains (prediction/reckoning), refer to for spy
Fixed external power supply supply voltage power down waveform, passive prediction (acquisition) this power supply under normal circumstances required for power down to 0V when
Between, in addition to this, the document also needs the cooperation of external clock or time signal；During power down, it needs additional calculating electricity
Road is calculated.
In conclusion in the prior art, in the case where no backup power source such as battery or bulky capacitor are supported, general electricity
Road, which all cannot achieve, is monitored other events occurred during itself power down time or power down.
Summary of the invention
In view of the deficiencies of the prior art, the present invention discloses a kind of power down time observation circuit.
Invention additionally discloses the working methods of above-mentioned power down time observation circuit.
Summary of the invention
The present invention generates standard discharge waveform, matches using specific internal capacitor, specific charging voltage, specific electric leakage
Close judgement of the voltage comparator circuit realization to power down time length.The present invention is charged to one under power-up state, by holding capacitor
Constant voltage, and just start that capacitor continue by leakage current and is slowly discharged after circuit power down, the holding electricity
Voltage in appearance gradually decreases increase at any time.As can seen above, different capacitance voltages corresponds to different power down times,
I.e. when circuit powers on again, by the voltage in detection holding capacitor, that is, the length of this power-down duration, example can determine
Such as specific time numerical value or time interval.
Technical scheme is as follows:
A kind of power down time observation circuit, which is characterized in that the circuit includes: holding capacitor C0 and charge-discharge control circuit
The core circuit of composition, be responsible for by convert of capacitor to voltage be the time output analog-to-digital conversion (ADC) or voltage detecting circuit and
It is responsible for the time showing or execution circuit of subsequent processing.As shown in Figure 2.
Preferred according to the present invention, the core circuit includes the flip and flop generator that gate circuit is constituted, the bistable state
The end R of trigger is connected with the output end of first or door I9, and an input terminal of described first or door I9 is put by the first paraphase
Big device I7 is connected with por signal input terminal, and another input terminal of described first or door I9 is connected with por signal input terminal, institute
The end S for stating flip and flop generator is connected with SET signal input part；
An input terminal of described first or door I9 passes through the second inverting amplifier I14 and third or door I13 and derailing switch
Part, the holding capacitor CO are connected with analog-to-digital conversion or voltage detecting circuit；
Analog-to-digital conversion or voltage detecting circuit are connected with the display or execution circuit.
Preferred according to the present invention, the switching device is MOS switch.
Preferred according to the present invention, the flip and flop generator is nor gate rest-set flip-flop.
The working method of power down time observation circuit of the present invention characterized by comprising when monitored circuit power down
When powering on again afterwards, monitoring provides power down time length and falls in which section and take corresponding when time power-down duration length
Operation.
Technical advantage of the invention is as follows:
The present invention realizes in the case where no power supply power supply and continues to monitor to power down time, provides a kind of new
Method for monitoring power supply powers on whether interval is monitored more than a certain range to electricity-under chip, with low-power consumption, low cost
Advantage.
It is checked present invention can apply to power supply monitoring, safeguard protection, cargo and other needs stipulated times after a power failure
It is interior keep information occasion, such as denied access, allow access situation.Therefore using the present invention after can save reserve battery or
The expense of storage capacitor improves the flexibility and reliability of down Monitor Unit system, and to start new security protection, item is created in monitoring application
Part.
Detailed description of the invention
Fig. 1 is the circuit diagram of traditional timing circuit；
Fig. 2 is the circuit diagram of power down time observation circuit of the invention；
Fig. 3 is the circuit diagram of power down time observation circuit in the embodiment of the present invention；
In Fig. 2,3, wherein CLR is CLR signal input terminal；PCR is PCR signal input part；SET is the input of SET signal
End；DET_Signal is DET_Signal signal output end；I6 is the first NOT gate；I7 is the first inverting amplifier；I9 is first
Or door；I10 and I11 is two NOT gates in nor gate rest-set flip-flop；I12 second or door；I13 is third or door；I14 is second
Inverting amplifier；SW1 is MOS switch；COMP_0 is comparator chip；CO is to maintain capacitor；R2 is second resistance；R3 is first
Resistance.
Specific embodiment
It is described in detail below with reference to embodiment and Figure of description, but not limited to this.
Embodiment 1,
As shown in Figure 2.
A kind of power down time observation circuit, comprising: holding capacitor C0 and the core circuit of charge-discharge control circuit composition are born
Duty by the analog-to-digital conversion (ADC) that convert of capacitor to voltage is time output or voltage detecting circuit and responsible subsequent processing when
Between show or execution circuit.As shown in Figure 2.
The core circuit includes the flip and flop generator that gate circuit is constituted, the end R and first of the flip and flop generator
Or the output end of door I9 is connected, an input terminal of described first or door I9 is defeated by the first inverting amplifier I7 and por signal
Enter end to be connected, another input terminal of described first or door I9 is connected with por signal input terminal, the S of the flip and flop generator
End is connected with SET signal input part；
An input terminal of described first or door I9 passes through the second inverting amplifier I14 and third or door I13 and derailing switch
Part, the holding capacitor CO are connected with analog-to-digital conversion or voltage detecting circuit；
Analog-to-digital conversion or voltage detecting circuit are connected with the display or execution circuit.
The switching device is MOS switch.
The flip and flop generator is nor gate rest-set flip-flop.
As shown in figure 3, being a preferred embodiment of the present embodiment, the end R of the flip and flop generator and first or door I9
Output end be connected, an input terminal A of described first or door I9 is connected with the output end Y of the first NOT gate I6 and passes through the respectively
Two inverting amplifier I14 and third or door I13 are connected with the holding capacitor C0 and detection circuit, and the one of the first NOT gate I6
A input terminal A is CLR signal input terminal, another input terminal B of another input terminal B and first or door I9 of the first NOT gate I6
Between connect the first inverting amplifier I7, while another input terminal B of first or door I9 is por signal input terminal；It is described double
The end S of steady state trigger is connected with the output end of second or door I12, an input terminal A and the SET letter of described second or door I12
Number input terminal is connected, and another input terminal B of described second or door I12 is connected with DET_signal signal output end；
The electrode input end of the comparator chip COMP_0 is connected by switching device with core circuit, the comparator
The output end of chip COMP_0 is connected with DET_signal signal output end.
The electrode input end of the comparator chip COMP_0 also passes through holding capacitor C0 and is grounded, the comparator chip
The negative input of COMP_0 is connect by first resistor R3 with chip operating voltage VDD, is also grounded by second resistance R2.
Embodiment 2,
The working method of power down time observation circuit as described in Example 1, comprising:
When powering on again after monitored circuit power down, it is long to provide power down time when time power-down duration length for monitoring
Which section degree falls in and takes corresponding operating, determines whether power down time is more than preset time T 0: if it exceeds T0, then indicate
Signal DET_signal signal will be cleared.
It include: to power on, power down and power on again for the first time in an independent down Monitor Unit period；Reference voltage is set
VREF0=VDD-I0*T0/C0；Wherein the CLR signal of CLR input terminal is used to reset detection circuit, the POR letter of POR input terminal
Number for electrification reset circuit export, normal power-up state be 0；
When the system is first powered on: CLR signal input terminal CLR=0 is opened by adding a positive pulse in SET signal input part
Holding capacitor C0 is charged to VDD by MOS switch SW1, due to VDD > VREF0, so analog-converted or voltage detecting circuit output
DET_Signal high level；This high level feeds back the control terminal to MOS switch SW1 by control circuit, and MOS switch SW1 is allowed to begin
Whole open state；
After a power failure: the MOS switch SW1 is closed, the first electricity that the charge in holding capacitor passes through MOS switch SW1
It hinders and discharges the electric leakage in second resistance；
When powering on again: voltage in holding capacitor and a reference voltage VREF0 are compared, as VC < VREF0,
Then judge that power-down duration is more than T0, so analog-converted or voltage detecting circuit output programming DET_Signal signal will be by
It resets.
Physical circuit as shown in Figure 3, function be a marking signal, when power was lost between be no more than a certain range when,
The marking signal can restore automatically after powering on again.It is described as follows: under electrifying condition, by SET signal input part to capacitor
It is charged to vdd, due to preset reference voltage vref < vdd, so marking signal DET_Signal is set.Once circuit occurs
Power down, holding capacitor voltage can decline at any time.When circuit powers on again, circuit can be by voltage in holding capacitor and default base
Quasi- voltage vref compares: if power down time is greater than preset time, voltage will be less than vref on capacitor, then comparator
Chip output 0, namely marking signal are removed；If power down time is less than preset time, voltage be will be above on capacitor
Holding capacitor then comparator chip will export high level, while being full of, namely restored power down by vref by feed circuit
Preceding state.
In the above two embodiments, it is known that:
Traditional time detection circuit needs a clock source and a counting circuit to carry out timing, as shown in Fig. 1, when
After circuit power down itself, if without the support of backup power source or storage capacitor, since pulse and counting are all unable to maintain that, so
Time can not be detected.
However, the present invention utilizes the leakage current characteristic of capacitor and device, power down time can be continued to monitor after a power failure,
When circuit powers on again, the length of this section of power down time can be judged.The present invention is not necessarily to power supply after a power failure and remains to
The characteristic for continuing timing not only can simplify the design of down Monitor Unit system, saves the expense of reserve battery and storage capacitor, mentions
High detection of power loss system flexibility and reliability, and can be to start new monitoring and security protection application to create conditions.
Although the present invention is illustrated using specific embodiment, the explanation of embodiment is not intended to limit of the invention
Range.One skilled in the art is by reference to explanation of the invention, without departing substantially from the spirit and scope of the present invention
In the case of, it is easy to carry out various modifications or embodiment can be combined.
Claims (6)
1. a kind of power down time observation circuit, which is characterized in that the circuit includes: holding capacitor C0 and charge-discharge control circuit structure
At core circuit, be responsible for by convert of capacitor to voltage be the time output analog-to-digital conversion or voltage detecting circuit and be responsible for after
The time showing or execution circuit of continuous processing.
2. a kind of power down time observation circuit according to claim 1, which is characterized in that the core circuit includes door electricity
The flip and flop generator that road is constituted, the end R of the flip and flop generator is connected with the output end of first or door I9, described first or
An input terminal of door I9 is connected by the first inverting amplifier I7 with por signal input terminal, and described first or door I9's is another
A input terminal is connected with por signal input terminal, and the end S of the flip and flop generator is connected with SET signal input part；
An input terminal of described first or door I9 passes through the second inverting amplifier I14 and third or door I13 and switching device, institute
Holding capacitor CO is stated to be connected with analog-to-digital conversion or voltage detecting circuit；
Analog-to-digital conversion or voltage detecting circuit are connected with the display or execution circuit.
3. a kind of power down time observation circuit according to claim 2, which is characterized in that the switching device is opened for MOS
It closes.
4. a kind of power down time observation circuit according to claim 3, which is characterized in that the flip and flop generator be or
NOT gate rest-set flip-flop.
5. a kind of working method of power down time observation circuit according to claim 1 characterized by comprising
When powering on again after monitored circuit power down, monitoring provides power down time length and falls when time power-down duration length
In which section and corresponding operating is taken, determines whether power down time is more than preset time T 0: if it exceeds T0, then marking signal
DET_signal signal will be cleared.
6. a kind of working method of power down time observation circuit as claimed in claim 5, which is characterized in that independently fall at one
It include: to power on, power down and power on again for the first time in the pyroelectric monitor period；Reference voltage VREF0=VDD-I0*T0/C0 is set；Wherein
The CLR signal of CLR input terminal is used to reset detection circuit, and the por signal of POR input terminal is electrification reset circuit output, just
Normal power-up state is 0；
When the system is first powered on: CLR signal input terminal CLR=0 opens MOS by adding a positive pulse in SET signal input part
Holding capacitor C0 is charged to VDD by switch SW1, due to VDD > VREF0, so analog-converted or voltage detecting circuit export DET_
Signal high level；This high level feeds back the control terminal to MOS switch SW1 by control circuit, and MOS switch SW1 is allowed to open always
Open state；
After a power failure: the MOS switch SW1 is closed, the charge in holding capacitor by the first resistor of MOS switch SW1 with
And it discharges to the electric leakage in second resistance；
When powering on again: voltage in holding capacitor and a reference voltage VREF0 being compared, as VC < VREF0, then sentenced
Disconnected power-down duration is more than T0, so analog-converted or voltage detecting circuit output programming DET_Signal signal will be clear
Zero.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2019102582654 | 2019-04-01 | ||
| CN201910258265 | 2019-04-01 |
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| Publication Number | Publication Date |
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| CN110138380A true CN110138380A (en) | 2019-08-16 |
| CN110138380B CN110138380B (en) | 2023-08-04 |
Family
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| CN201910411628.3A Active CN110138380B (en) | 2019-04-01 | 2019-05-17 | Power-down time monitoring circuit and method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113109738A (en) * | 2021-03-15 | 2021-07-13 | 苏州汇川技术有限公司 | Power-down time detection circuit and power-down time detection system |
| CN114325481A (en) * | 2021-12-29 | 2022-04-12 | 深圳市欧瑞博科技股份有限公司 | Power-off duration detection method and device, electronic equipment and storage medium |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113109738A (en) * | 2021-03-15 | 2021-07-13 | 苏州汇川技术有限公司 | Power-down time detection circuit and power-down time detection system |
| CN113109738B (en) * | 2021-03-15 | 2023-08-04 | 苏州汇川技术有限公司 | Power-down time detection circuit and power-down time detection system |
| CN114325481A (en) * | 2021-12-29 | 2022-04-12 | 深圳市欧瑞博科技股份有限公司 | Power-off duration detection method and device, electronic equipment and storage medium |
| CN114325481B (en) * | 2021-12-29 | 2023-10-31 | 深圳市欧瑞博科技股份有限公司 | Power-off duration detection method and device, electronic equipment and storage medium |
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| Publication number | Publication date |
|---|---|
| CN110138380B (en) | 2023-08-04 |
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Denomination of invention: A power outage time monitoring circuit and method Granted publication date: 20230804 Pledgee: Huaxia Bank Co.,Ltd. Jinan Branch Pledgor: SHANDONG HUAYI MICRO-ELECTRONICS Co.,Ltd. Registration number: Y2024980024862 |