CN110138375B

CN110138375B - Circuit for chip pin

Info

Publication number: CN110138375B
Application number: CN201810106736.5A
Authority: CN
Inventors: 王珏; 黄伦学
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-02-02
Filing date: 2018-02-02
Publication date: 2021-08-27
Anticipated expiration: 2038-02-02
Also published as: WO2019149126A1; CN110138375A

Abstract

The application discloses a circuit for chip pins, which releases voltage on the chip pins and protects electronic devices in the chip from being damaged. The method comprises the following steps: a first transistor, a second transistor, a first sub-circuit, a second sub-circuit, and a third sub-circuit; the first pole of the first transistor is connected with the first pole of the second transistor and connected to a chip pin, the second pole of the first transistor is connected to the positive pole of a power supply, and the second pole of the second transistor is connected to the negative pole of the power supply; the first sub-circuit is connected between the positive power supply electrode and the negative power supply electrode, and the first sub-circuit is connected to a third pole of the first transistor and a third pole of the second transistor; the second sub-circuit is connected between the positive electrode of the power supply and the chip pin; the third sub-circuit is connected between the chip pin and the power supply negative electrode and used for releasing positive voltage on the chip pin to the power supply negative electrode.

Description

Circuit for chip pin

Technical Field

The present application relates to the field of chip technology, and more particularly, to a circuit for a chip pin.

Background

Chip pins (pins), also called chip pins, are interfaces between the chip internal circuitry and the chip external circuitry. The chip pins are divided into input pins or output pins, the input pins are used for inputting signals of an external circuit to the chip internal circuit, and the output pins are used for outputting signals of the chip internal circuit to the chip external circuit.

At present, an output circuit structure inside an input/output (IO) pin of a chip is mainly composed of two Metal Oxide Semiconductor (MOS) transistors, and drains of the two MOS transistors are connected to each other and further connected to the pin of the chip. The first MOS transistor is connected with an IO power supply, and the second MOS transistor is connected with a grounding end. When a voltage which may cause damage, such as an electrostatic discharge (ESD) voltage, exists on a chip pin, effective protection is required. Therefore, when the voltage is positive, the parasitic diode of the first MOS transistor releases the positive voltage to the IO power supply to release the positive voltage on the chip pin, so as to prevent the positive voltage from affecting the normal output of the chip pin signal, and thus the parasitic diode plays a role in preventing the pin from being damaged. Because a large number of other devices are connected to the IO power supply, releasing the positive voltage on the chip pin to the IO power supply may affect the normal operation of the circuit system.

Therefore, the anti-backflow processing circuit is added on the basis of the output circuit structure and is used for cutting off a positive voltage discharge channel between the chip pin and the IO power supply, and the positive voltage on the chip pin is prevented from being released to the IO power supply, so that the normal work of a circuit system is ensured. However, the backflow prevention processing circuit cannot realize the function of preventing the pin from being damaged while avoiding the influence of the positive voltage discharge channel on the IO power supply.

Disclosure of Invention

The application provides a circuit for a chip pin, which is used for releasing voltage on the chip pin and protecting an electronic device in a chip from being damaged.

In a first aspect, the present application provides a circuit for a chip pin, comprising: a first transistor, a second transistor, a first sub-circuit, a second sub-circuit, and a third sub-circuit; the first pole of the first transistor is connected with the first pole of the second transistor and further connected to a chip pin, the second pole of the first transistor is connected to the positive pole of a power supply, and the second pole of the second transistor is connected to the negative pole of the power supply; the first sub-circuit is connected between the positive power supply electrode and the negative power supply electrode, and the first sub-circuit is connected to a third pole of the first transistor and a third pole of the second transistor and used for controlling the first transistor and the second transistor to output a high-level signal or a low-level signal to the chip pin; the second sub-circuit is connected between the positive power supply electrode and the chip pin and used for preventing positive voltage on the chip pin from being released to the positive power supply electrode; the third sub-circuit is connected between the chip pin and the power supply negative electrode and is used for releasing the positive voltage on the chip pin to the power supply negative electrode.

From the above technical solution, it can be seen that the present application has the following advantages: the second sub-circuit prevents positive voltage on the chip pin from being released to the positive electrode of the power supply, so that adverse effect on the positive electrode of the power supply is reduced, and meanwhile, the positive voltage is released to the negative electrode of the power supply through the third sub-circuit to provide a current leakage channel for the positive voltage on the chip pin so as to protect electronic devices, such as the first transistor or the second transistor, from being damaged by the positive voltage, so that the failure rate of the chip in the production, test or use process is reduced.

With reference to the first aspect, in a first possible implementation manner of the first aspect, the first transistor is a P-channel metal oxide semiconductor (PMOS) transistor, the second transistor is an NMOS transistor, the first pole of the first transistor and the first pole of the second transistor are drains, the second pole of the first transistor and the second pole of the second transistor are sources, and the third pole of the first transistor and the third pole of the second transistor are gates.

With reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the third sub-circuit includes: a first diode, a second diode and a fourth sub-circuit; the anode of the first diode is connected with the chip pin, the anode of the second diode is connected with the anode of the power supply, and the cathode of the first diode and the cathode of the second diode are connected to a first node; the fourth sub-circuit is connected between the first node and the negative power supply for discharging the positive voltage to the negative power supply.

With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the third sub-circuit further includes: a third diode; the cathode of the third diode is connected with the anode of the first diode and the chip pin, and the anode of the third diode is connected with the cathode of the power supply; the third diode is used for releasing the negative voltage on the chip pin to the negative pole of the power supply.

With reference to the second possible implementation manner of the first aspect or the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the fourth sub-circuit includes a first electrostatic discharge protection circuit.

With reference to the first aspect, or any one of the first possible implementation manner to the fourth possible implementation manner of the first aspect, in a fifth possible implementation manner of the first aspect, the positive voltage is higher than a withstand voltage threshold of the chip pin.

With reference to the first aspect, or any one of the first possible implementation manner to the fifth possible implementation manner of the first aspect, in a sixth possible implementation manner of the first aspect, the negative electrode of the power supply is a ground terminal. Alternatively, the power supply cathode is a negative power supply terminal.

With reference to the first aspect, any one of the first possible implementation manner of the first aspect to the sixth possible implementation manner of the first aspect, in a seventh possible implementation manner of the first aspect, the circuit further includes: and the second electrostatic discharge protection circuit is connected between the positive electrode of the power supply and the negative electrode of the power supply and used for releasing the voltage on the positive electrode of the power supply to the negative electrode of the power supply.

With reference to the first aspect, or any one of the first possible implementation manner to the seventh possible implementation manner of the first aspect, in an eighth possible implementation manner of the first aspect, the positive voltage is generated by a test device connected to the chip pin. Optionally, the test equipment comprises a multimeter.

With reference to the first aspect, or any one of the first possible implementation manner to the eighth possible implementation manner of the first aspect, in a ninth possible implementation manner of the first aspect, the second sub-circuit is configured to prevent a positive voltage on the chip pin from being released to the power supply positive electrode through a parasitic diode of the first transistor. Optionally, the second sub-circuit includes a backflow prevention processing circuit.

In a second aspect, the present application provides a chip, where the chip includes the circuit, the chip pin, the positive power supply terminal, and the negative power supply terminal described in any one of the first aspect, the first possible implementation manner of the first aspect, and the eighth possible implementation manner of the first aspect.

Similar to the advantages of the circuit described in the first aspect, the chip has a function of protecting an electronic device, such as the first transistor or the second transistor, in an output structure of the chip from being damaged by a voltage, such as an electrostatic discharge voltage, on a pin of the chip, so that the occurrence of chip failure caused by the chip being damaged due to the voltage existing on the output pin in the production, test or use process of the chip is effectively reduced, and the failure rate of the chip in the production, test or use process is reduced.

Drawings

FIG. 1 is a diagram illustrating a chip structure according to an embodiment of the present application;

FIG. 2 is a schematic diagram of one embodiment of a circuit in an embodiment of the present application;

FIG. 3 is a schematic diagram of another embodiment of a circuit in an embodiment of the present application;

fig. 4 is a schematic diagram of another embodiment of a circuit in an embodiment of the present application.

Detailed Description

The application provides a circuit for a chip pin, which is used for releasing voltage on the chip pin, protecting an electronic device in a chip from being damaged and reducing the failure rate of the chip in the production, test or use process.

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings in the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps, functions, or elements is not necessarily limited to those steps, functions, or elements expressly listed, but may include other steps, functions, or elements not expressly listed or inherent to such process, method, article, or apparatus.

A chip (chip) is a general term for a semiconductor device, and is obtained by designing, testing, manufacturing, and packaging an electronic device. The chip may be a carrier of an Integrated Circuit (IC), such as a silicon chip, or may be an integrated circuit, and thus is also called a semiconductor chip. As shown in fig. 1, a chip structure diagram of a chip is shown, and the chip mainly includes: chip pin, input structure circuit, internal logic control circuit, output structure circuit. The chip pins are also called pins or IO pins, and are mainly used for inputting or outputting level signals. In fig. 1, 12 pins are shown, pin 1 being a power supply pin for connecting a positive power supply such as an IO power supply to power the chip, and pin 13 being a digital circuit ground pin for connecting a negative power supply. The pins 2 to 7 are input pins, each of which is connected to an input structure circuit, so that an external signal is input to the chip, and the input structure circuit performs corresponding processing on the input signal (high level signal or low level signal). The internal logic control circuit performs a series of mathematical logic operations on the input signal and controls the output structure circuit to output a corresponding output signal (high level signal or low level signal). Pins 8-12 are output pins, each of which is electrically connected to an output structure for outputting an output signal to a corresponding output pin.

The circuit for the chip pin in the embodiment of the application is mainly used in the output structure circuit to protect electronic devices in the output structure circuit from being damaged by high voltage on the output pin, for example, electrostatic discharge protection is realized. In view of the above, the circuit in the present application will be described in detail with reference to specific embodiments. As shown in fig. 2, the circuit for a chip pin in the embodiment of the present application includes: a first transistor 201, a second transistor 202, a first sub-circuit 203, a second sub-circuit 204, a third sub-circuit 205. Fig. 2 also shows a chip pin 206 for outputting a high level signal or a low level signal, a power supply positive electrode 207, and a power supply negative electrode 208.

A first pole of the first transistor 201 is connected to a first pole of the second transistor 202 and further to a chip pin 206. The second pole of the first transistor 201 is connected to the positive power supply electrode 207, and the second pole of the second transistor 202 is connected to the negative power supply electrode 208. The first sub-circuit 203 is connected between the power supply anode 207 and the power supply cathode 208, and the first sub-circuit 203 is respectively connected with the second pole of the first transistor 201 and the third pole of the second transistor 202, and the first sub-circuit 203 is used for controlling the first transistor 201 and the second transistor 202 to output a high-level signal or a low-level signal to the chip pin 206. Specifically, at the same time, the first sub-circuit 203 controls only one of the first transistor 201 and the second transistor 202 to be turned on to output a high-level signal or a low-level signal to the chip pin 206. When the first transistor 201 is turned on, a high-level signal is output to the chip pin 206, and when the second transistor 202 is turned on, a low-level signal is output to the chip pin 206. The second sub-circuit 204 is connected between the power supply anode 207 and the chip pin 206, and the second sub-circuit 204 is used for preventing the positive voltage on the chip pin from being discharged to the power supply anode 207 through a parasitic diode (not shown in the figure) of the first transistor 201. The third sub-circuit 205 is connected between the chip pin 206 and the power supply negative electrode 208, and the third sub-circuit 205 is configured to release the positive voltage on the chip pin 206 to the power supply negative electrode 208, so that the positive voltage on the chip pin 206 is adjusted to be lower than the withstand voltage threshold of the chip pin 206.

As can be seen from the output circuit shown in fig. 2, a positive voltage on the chip pin 206, which is greater than the voltage withstanding threshold, can be discharged to the power supply cathode 208 through the third sub-circuit 205, so that the voltage value of the positive voltage on the chip pin 206 is adjusted to be smaller than the voltage withstanding threshold of the chip pin 206, so as to avoid at least one of the first transistor 201 and the second transistor 202 from being damaged, thereby achieving the effect of protecting the chip and reducing the failure rate of the chip during production, testing or use.

Optionally, as shown in the circuit in fig. 3, the first transistor 201 may be a PMOS transistor 301, the second transistor 202 may be an NMOS transistor 302, first electrodes of the first transistor 201 and the second transistor 202 are drains, second electrodes of the first transistor 201 and the second transistor 202 are sources, third electrodes of the first transistor 201 and the second transistor 202 are gates, and at least one of the first transistor 201 and the second transistor 202 may also be one or more other switching transistors, such as diodes or carbon nanotubes, having similar functions to the PMOS transistor or the NMOS transistor, for controlling the chip pin 206 to output a high-level signal or a low-level signal, which is not limited in this application. Optionally, the negative electrode of the power supply in the above embodiment may be a ground terminal, such as a digital signal ground terminal, or may be a negative power supply.

The circuit in this application may use an IO power supply to supply power to the IO power supply, as shown in fig. 3, another embodiment of the circuit in this application embodiment includes: a PMOS transistor 301, an NMOS transistor 302, a logic circuit 303 inside the chip, a backflow prevention processing circuit 304, a first diode 306, a second diode 307, an electrostatic discharge protection circuit 308 and an electrostatic discharge protection circuit 309. Also shown in fig. 3 are chip pin 305, IO power supply 310, and ground 311, which correspond to chip pin 206, power supply positive electrode 207, and power supply negative electrode 208, respectively, in fig. 2. The related descriptions of the PMOS transistor 301, the NMOS transistor 302, the internal logic circuit 303 of the chip, and the anti-backflow processing circuit 304 can refer to the related descriptions of the first transistor 201, the second transistor 202, the first sub-circuit 203, and the second sub-circuit 204 in fig. 2, which are not repeated herein.

In this embodiment, the substrate of the PMOS transistor 301 is a floating substrate, i.e., the threshold voltage between the gate and the source of the PMOS transistor 301 is adjustable. The anti-backflow processing circuit 304 is further connected to the PMOS transistor 301, and further, the anti-backflow processing circuit 304 is configured to adjust a threshold voltage of the PMOS transistor 301 according to a voltage of the IO power supply 310 and a voltage of the chip pin 305, so that a parasitic diode (not shown) of the PMOS transistor 301 is always in a reverse bias state and is not turned on. It is easy to know that the parasitic diode of PMOS transistor 301 is oriented from its drain to its source, so the positive voltage on chip pin 305 cannot be discharged to IO power supply 310, reducing the impact on IO power supply 310.

The logic circuit 303 is used to generate a control gate of the PMOS transistor 301 and the NMOS transistor 302 to control the on or off of the two transistors, so that the chip pin 305 outputs a high level signal or a low level signal. The logic circuit 303 may include a logic control circuit or an arithmetic circuit, and may also include a processor, such as a central processing unit, a microcontroller, a microprocessor, a digital signal processor, etc., and may run necessary driving software or application software.

It should be noted that the parasitic diode is formed by a manufacturing process of a MOS transistor, and functions as an ordinary diode, and when the anode voltage of the parasitic diode is higher than the cathode voltage thereof, the parasitic diode is turned on, and when the anode voltage of the parasitic diode is lower than the cathode voltage thereof, the parasitic diode is turned off, and for the turn-on, the parasitic diode is referred to as a forward bias state, and the turn-off is referred to as a reverse bias state. The parasitic diode of the MOS transistor is equivalent to the MOS transistor, but both of them may correspond to substantially the same physical structure. The direction of the parasitic diode of the PMOS transistor 301 is from the drain to the source, and the direction of the parasitic diode of the NMOS transistor 302 is from the source to the drain.

As with the third sub-circuit 205, the first diode 306, the second diode 307 and the esd protection circuit 308 form a high voltage leakage path, wherein the anode of the first diode 306 is connected to the chip pin 305, the anode of the second diode 307 is connected to the IO power supply 310, and the cathode of the first diode 306 and the cathode of the second diode 307 are connected to the first node. The esd protection circuit 308 is connected between the first node and the ground 311. When a positive voltage is present on the chip pin 305, the esd protection circuit 308 discharges the positive voltage to the ground 311, thereby preventing the circuit of the chip pin 305 from being damaged due to the positive voltage on the chip pin 305 exceeding the withstand voltage threshold of the chip pin 305. Of course, the esd protection circuit 308 can be replaced by other circuits having the above-mentioned positive voltage discharging function, and the application is not limited thereto. The second diode 307 is used for providing a fixed voltage to the esd protection circuit 308, so that the esd protection circuit 308 can work normally, and the high voltage discharging channel can achieve its discharging function, and further discharge the positive voltage on the chip pin 305 to the ground terminal 311.

The esd protection circuit 309 or other circuits with similar functions are used to discharge the static electricity on the IO power supply 310 to the ground 311, so as to enhance the protection capability of the circuit and improve the protection effect on the chip, so that the chip is not damaged by the static electricity. In practical applications, the IO power supply 310 and the ground terminal 311 are also connected to other circuits in the chip or other chips, so that the static electricity on the IO power supply 310 is discharged to the ground terminal 311, and the other circuits in the chip or other chips can also work normally.

From the above description of NMOS transistors it follows that: the parasitic diode of the NMOS transistor 302 is oriented from source to drain. Therefore, in the circuit shown in fig. 3, when a negative voltage is present at the chip pin 305, the negative voltage is drained to the ground 311 through the parasitic diode of the NMOS transistor 302. However, long-term use of the NMOS transistor 302 to drain the negative voltage at the chip pin 305 may cause the NMOS transistor 302 to be damaged or to have a reduced service life. Therefore, in order to better protect the NMOS transistor 302 and quickly release the negative high voltage to the ground, the present application also provides yet another embodiment.

As shown in fig. 4, another embodiment of the circuit in the embodiment of the present application includes: a PMOS transistor 401, an NMOS transistor 402, a logic circuit 403 inside the chip, a backflow prevention processing circuit 404, a first diode 406, a second diode 407, an electrostatic discharge protection circuit 408, an electrostatic discharge protection circuit 409 and a third diode 410. Also shown in fig. 4 are chip pin 405, IO power supply 411, and ground 412.

In this embodiment, the descriptions of the PMOS transistor 401, the NMOS transistor 402, the logic circuit 403 inside the chip, the backflow prevention processing circuit 404, the first diode 406, the second diode 407, the esd protection circuit 408, and the esd protection circuit 409 may refer to the descriptions of the PMOS transistor 301, the NMOS transistor 302, the logic circuit 303 inside the chip, the backflow prevention processing circuit 304, the first diode 306, the second diode 307, the esd protection circuit 308, and the esd protection circuit 309 in fig. 3, and the descriptions in the corresponding embodiment of fig. 2, respectively, and therefore, the descriptions thereof are omitted here.

The description of the rest of fig. 4 can refer to the description of fig. 2 and the description of the relevant parts of fig. 3, for example, the chip pin 405, the IO power supply 411 and the ground terminal 412 correspond to the chip pin 305, the IO power supply 310 and the ground terminal 311 of fig. 3, respectively. The cathode of the third diode 410 is connected to the anode of the first diode 406 and the chip pin 405, and the anode of the third diode 410 is connected to the ground 412; the third diode 410 is used to discharge the negative voltage of the chip pin 405 to the ground 412.

The working principle of the circuit in the embodiment of the present application is described below with reference to a specific application scenario, specifically, as shown in fig. 4 as an example, when a chip is in a detection process, it is a common chip detection method by detecting an impedance value of a chip pin to a ground terminal. In the above-mentioned detection method, a commonly used test device, such as a buzzer of the multimeter, detects whether the impedance between the chip pin 405 and the ground 412 is significantly small, for example, less than 1000 ohms, and the multimeter will issue a buzzer prompt. The detection principle of the buzzing gear is as follows: a current source is generated within the multimeter to deliver a constant current, e.g., 1mA, to the object being measured. Because the impedance of the object to be measured is different, the output voltage can be automatically adjusted according to the impedance of the object to be measured in the multimeter, so that the output current of 1mA is ensured. The impedance of the object to be measured cannot exceed a certain preset value, and if the impedance exceeds the certain preset value, the buzzer basically keeps outputting a fixed voltage, which is equivalent to an open-circuit voltage.

During detection, the multimeter is adjusted to a buzzing gear and connected with the chip pin 405, and because the parasitic diode of the NMOS tube is in a reverse bias state and is not conducted at the moment, the impedance is equivalent to an open circuit greatly. At this time, the multimeter outputs a constant current, so that an open-circuit voltage exists on the chip pin 405, if the open-circuit voltage does not exceed the voltage-withstanding threshold of the chip pin 405, the electrostatic protection circuit 408 is in a high-resistance state and is not conducted, if the open-circuit voltage exceeds the voltage-withstanding threshold of the chip pin 405, the electrostatic protection circuit 408 is in a low-resistance state and is conducted, and the high voltage on the chip pin 405 is released to a low-connection end through the electrostatic protection circuit 408, so that the high voltage of the chip pin 405 is reduced to be lower than the voltage-withstanding threshold of the chip pin 405, and therefore the chip pin 405 of the chip is protected from being damaged by the high voltage, and further the chip failure rate in the chip testing process is reduced. Similarly, the circuit in the present application can also be applied to protect the chip pins from being damaged by high voltage during the production and use processes, which results in the chip being unusable.

An embodiment of the present application further provides a chip, where the chip includes any one of the circuits, chip pins, IO power supplies, and ground terminals described in the method embodiments corresponding to fig. 2, fig. 3, and fig. 4, and specifically, refer to a chip schematic diagram corresponding to fig. 1. Similar to the above-mentioned beneficial effects of the circuits described in fig. 2, fig. 3 and fig. 4, the chip has a function of protecting the electronic device (such as the first transistor or the second transistor) in the output structure from being damaged by the high voltage on the pin of the chip, so as to ensure that the chip and the circuit system including the chip can work normally, and at the same time, effectively reduce the occurrence of chip failure caused by the chip being damaged due to the voltage, such as the electrostatic discharge voltage, existing on the output pin during the production, test or use of the chip, thereby reducing the failure rate of the chip during the production, test or use of the chip.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in this application, the connections between the various devices or modules shown or discussed represent a coupling or electrical connection. Such connections may be direct or through other devices to allow electrical communication between different devices or modules.

The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the technical solution scope of the embodiments of the present application.

Claims

1. A circuit for a chip pin, comprising:

a first transistor, a second transistor, a first sub-circuit, a second sub-circuit, and a third sub-circuit;

the first pole of the first transistor is connected with the first pole of the second transistor and further connected to a chip pin, the second pole of the first transistor is connected to the positive pole of a power supply, and the second pole of the second transistor is connected to the negative pole of the power supply;

the first sub-circuit is connected between the positive power supply electrode and the negative power supply electrode, and the first sub-circuit is connected to a third pole of the first transistor and a third pole of the second transistor and used for controlling the first transistor and the second transistor to output a high-level signal or a low-level signal to the chip pin;

the second sub-circuit is connected between the positive power supply electrode and the chip pin and used for preventing positive voltage on the chip pin from being released to the positive power supply electrode;

the third sub-circuit is connected between the chip pin and the power supply negative electrode and used for releasing the positive voltage on the chip pin to the power supply negative electrode;

the third sub-circuit comprises: a first diode, a second diode and a fourth sub-circuit; the anode of the first diode is connected with the chip pin, the anode of the second diode is connected with the anode of the power supply, and the cathode of the first diode and the cathode of the second diode are connected to a first node; the fourth sub-circuit is connected between the first node and the negative power supply electrode and used for releasing the positive voltage on the chip pin to the negative power supply electrode;

the second sub-circuit comprises a backflow prevention processing circuit.

2. The circuit of claim 1, wherein the first transistor is a P-channel metal-oxide-semiconductor (PMOS) transistor, the second transistor is an N-channel metal-oxide-semiconductor (NMOS) transistor, a first pole of the first transistor and a first pole of the second transistor are drains, a second pole of the first transistor and a second pole of the second transistor are sources, and a third pole of the first transistor and a third pole of the second transistor are gates.

3. The circuit of claim 2, wherein the third sub-circuit further comprises: a third diode;

the cathode of the third diode is connected with the anode of the first diode and the chip pin, and the anode of the third diode is connected with the cathode of the power supply; the third diode is used for releasing the negative voltage on the chip pin to the negative pole of the power supply.

4. The circuit of claim 3, wherein the fourth sub-circuit comprises a first ESD protection circuit.

5. The circuit according to any one of claims 1 to 4, wherein the positive voltage is higher than a withstand voltage threshold of the chip pin.

6. The circuit of any of claims 1-4, wherein the negative power supply terminal is ground.

7. The circuit of any of claims 1-4, further comprising: and the second electrostatic discharge protection circuit is connected between the positive electrode of the power supply and the negative electrode of the power supply and used for releasing the voltage on the positive electrode of the power supply to the negative electrode of the power supply.

8. The circuit of any of claims 1-4, wherein the positive voltage is generated by test equipment connected to the chip pin.

9. The circuit of any of claims 1-4, wherein the second sub-circuit is configured to prevent the positive voltage on the chip pin from being discharged to the positive power supply via a parasitic diode of the first transistor.

10. A chip characterized in that it comprises a circuit according to any one of claims 1 to 9, the chip pin, the positive power supply and the negative power supply.