CN110120387A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN110120387A
CN110120387A CN201910088560.XA CN201910088560A CN110120387A CN 110120387 A CN110120387 A CN 110120387A CN 201910088560 A CN201910088560 A CN 201910088560A CN 110120387 A CN110120387 A CN 110120387A
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China
Prior art keywords
pad
semiconductor chip
semiconductor
chip
substrate
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CN201910088560.XA
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English (en)
Inventor
李晟观
朴彻
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN110120387A publication Critical patent/CN110120387A/zh
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Abstract

一种半导体封装，包括：包括外部端子在内的衬底；衬底上的第一半导体芯片，具有第一区域和第二区域；第一半导体芯片的第二区域上的至少一个第二半导体芯片，至少一个第二半导体芯片暴露第一半导体芯片的第一区域的顶表面；以及至少一个第二半导体芯片上的至少一个第三半导体芯片，其中，第一半导体芯片包括电连接到至少一个第二半导体芯片的第一焊盘；电连接到至少一个第三半导体芯片的第二焊盘；以及电连接到外部端子的第三焊盘，第一焊盘在第一区域的顶表面上，并且第二焊盘和第三焊盘中的至少一个在第二区域的顶表面上。

Description

半导体封装
相关申请的交叉引用
于2018年2月5日在韩国知识产权局提交的标题为“Semiconductor Package”的韩国专利申请No.10-2018-0013998通过引用整体并入本文中。
技术领域
实施例涉及半导体封装。
背景技术
提供半导体封装以实现以有资格用于电子产品中的集成电路芯片。
发明内容
可以通过提供包括衬底在内的半导体封装来实现实施例，该衬底包括外部端子；所述衬底上的第一半导体芯片，在平面图中所述第一半导体芯片具有第一区域和第二区域；第一半导体芯片的第二区域上的至少一个第二半导体芯片，至少一个第二半导体芯片暴露第一半导体芯片的第一区域的顶表面；以及至少一个第二半导体芯片上的至少一个第三半导体芯片，其中，第一半导体芯片包括电连接到至少一个第二半导体芯片的第一焊盘；电连接到至少一个第三半导体芯片的第二焊盘；以及电连接到外部端子的第三焊盘，第一焊盘在第一区域的顶表面上，并且第二焊盘和第三焊盘中的至少一个在第二区域的顶表面上。
实施例可以通过提供一种半导体封装来实现，所述半导体封装包括：衬底；所述衬底上的第一半导体芯片，包括第一焊盘、第二焊盘和第三焊盘，所述第一焊盘、所述第二焊盘和所述第三焊盘在所述第一半导体芯片的顶表面上；第一半导体芯片上的至少一个第二半导体芯片，至少一个第二半导体芯片部分地暴露第一半导体芯片的顶表面；以及至少一个第二半导体芯片上的至少一个第三半导体芯片，其中，第一焊盘电连接到至少一个第二半导体芯片，第二焊盘电连接到至少一个第三半导体芯片，第三焊盘电连接到第一焊盘和第二焊盘，并且至少一个第二半导体芯片暴露第一焊盘并覆盖第二焊盘和第三焊盘中的至少一个。
附图说明
通过参考附图详细描述示例性实施例，特征对于本领域技术人员将是显而易见的，在附图中：
图1示出了示出根据示例性实施例的半导体封装的电连接的示意图。
图2A示出了示出根据示例性实施例的半导体封装的平面图。
图2B示出了沿着图2A的线I-II截取的横截面图。
图3A示出了示出根据示例性实施例的半导体封装的平面图。
图3B示出了沿着图3A的线I-II截取的横截面图。
图4A示出了示出根据示例性实施例的半导体封装的平面图。
图4B示出了沿着图4A的线I-II截取的横截面图。
图5A示出了示出根据示例性实施例的半导体封装的平面图。
图5B示出了沿着图5A的线I-II截取的横截面图。
图6A示出了示出根据示例性实施例的半导体封装的平面图。
图6B示出了沿着图6A的线I-II截取的横截面图。
图7示出了示出根据示例性实施例的半导体封装的横截面图。
图8示出了示出根据示例性实施例的半导体封装的横截面图。
图9示出了示出根据示例性实施例的半导体封装的横截面图。
具体实施方式
图1示出了示出根据示例性实施例的半导体封装的电连接的示意图。
参考图1，半导体封装可以包括衬底100、第一半导体芯片200、第二半导体芯片300和第三半导体芯片400。衬底100可以具有外部端子120。外部电信号和/或数据可以通过外部端子120从衬底100传输或传输到衬底100。第一半导体芯片200可以包括集成电路部分210和内部布线215。集成电路部分210可以包括缓冲电路。在一个实现中，集成电路部分210可以包括控制器电路。内部布线215可以电连接到集成电路部分210。
第一半导体芯片200可以包括第一焊盘P1、第二焊盘P2和第三焊盘P3。第一焊盘P1可以电连接到第二半导体芯片300。第二焊盘P2可以电连接到第三半导体芯片400。在本说明书中，短语“电连接”可以包括“直接连接”或“通过其他导电组件间接连接”。短语“电连接到半导体芯片”可以表示“电连接到半导体芯片的集成电路”。第三焊盘P3可以电连接到外部端子120。第一焊盘至第三焊盘P1、P2和P3可以通过内部布线215电连接到集成电路部分210。第三焊盘P3可以通过集成电路部分210电连接到第一焊盘P1和第二焊盘P2。第三焊盘P3可以用作信号和/或数据通过其传输到第一焊盘P1和第二焊盘P2以及从第一焊盘P1和第二焊盘P2传输的路径。
如果一个或多个第二半导体芯片300和一个或多个第三半导体芯片400通过一个焊盘电连接到集成电路部分210，则当向第二半导体芯片300和第三半导体芯片400传输信号和从第二半导体芯片300和第三半导体芯片400传输信号时可以在焊盘上施加大的负载。另外，焊盘或芯片可以电连接到第三焊盘P3，并且还可以在第三焊盘P3上施加大的负载。根据一些实施例，一个或多个第二半导体芯片300可以通过第一焊盘P1电连接到第三焊盘P3，并且一个或多个第三半导体芯片400可以通过第二焊盘P2电连接到第三焊盘P3。这种连接关系可以帮助减少连接到第一焊盘P1的芯片(例如，第二半导体芯片300)的数量。另外，这种连接关系可以帮助减少连接到第二焊盘P2的芯片(例如，第三半导体芯片400)的数量。第二半导体芯片300和第三半导体芯片400可以与集成电路部分210通信信号和/或数据(在下文中称为信号)，该信号可以分别分配到第一焊盘P1和第二焊盘P2。第三焊盘P3可以发送和接收分配的信号。因此，半导体封装可以提高操作速度。
图2A示出了示出根据示例性实施例的半导体封装的平面图。图2B示出了沿着图2A的线I-II截取的横截面图。
参照图2A和图2B，半导体封装1可以包括衬底100、第一半导体芯片200、第二半导体芯片300、第三半导体芯片400、密封剂700和模制层800。例如，衬底100可以包括印刷电路板。衬底100可以在其顶表面上包括衬底焊盘110。衬底焊盘110可以包括诸如铜或铝的金属。衬底100可以在其底表面(例如，与顶表面相对)上包括外部端子120。外部端子120可以通过衬底100内的导电线130电连接到衬底焊盘110。在附图中，衬底100内的虚线示意性地指示衬底焊盘110与外部端子120之间的导电线130。在实现中，外部端子120可以成形为类似焊球并且可以包括诸如锡的导电材料。外部端子120可以耦合到外部设备。因此，外部信号可以经由外部端子120传输到衬底焊盘110和从衬底焊盘110传输。
第一半导体芯片200可以在衬底100上。第一半导体芯片200可以包括集成电路部分210和内部布线215。在附图中，第一半导体芯片200内的实线示意性地指示内部布线215。在实现中，集成电路部分210可以包括缓冲电路，并且第一半导体芯片200可以用作缓冲芯片。当在平面图中观察时，第一半导体芯片200可以具有第一区域R1和第二区域R2。第一半导体芯片200的第一区域R1可以与第一半导体芯片200的第一侧表面200b相邻。第一半导体芯片200的第二区域R2可以比第一区域R1更靠近第一半导体芯片200的第二侧表面200c。第一半导体芯片200的第二侧表面200c可以与第一侧表面200b相对地直立。在本描述中，第一方向D1和第二方向D2可以平行于衬底100的顶表面。第二方向D2可以与第一方向D1相交。第三方向D3可以与第一方向D1和第二方向D2相交。第一半导体芯片200的第一侧表面200b和第二侧表面200c可以平行于第三方向D3。
第一半导体芯片200可以包括第一焊盘P1、第二焊盘P2和第三焊盘P3，第一焊盘P1、第二焊盘P2和第三焊盘P3可以设置在第一半导体芯片200的顶表面200a(例如，背离衬底100的表面)上。第一焊盘至第三焊盘P1、P2和P3之间的电连接可以与上面参考图1所讨论的电连接基本相同。第一焊盘至第三焊盘P1、P2和P3可以彼此间隔开。在实现中，第一焊盘P1和第二焊盘P2可以设置在第一半导体芯片200的第一区域R1的顶表面200a上。第一焊盘P1和第二焊盘P2可以被第二半导体芯片300暴露(例如，可以不被第二半导体芯片300覆盖)。当在平面图中观察时，第二焊盘P2可以比第一焊盘P1更靠近第一半导体芯片200的第一侧表面200b。在实现中，第三焊盘P3可以位于第一半导体芯片200的第二区域R2的顶表面200a上。第三焊盘P3可以通过集成电路部分210电连接到第一焊盘P1和第二焊盘P2，如上面参考图1所讨论的。第一焊盘至第三焊盘P1、P2和P3可以包括诸如铜或铝的金属。
如图2A所示，第一焊盘P1可以设置为多个。第一焊盘P1可以构成或布置成在与第二方向D2平行的行中。第二焊盘P2可以设置为多个。第二焊盘P2可以构成或布置成在与第二方向D2平行的行中。第三焊盘P3可以设置为多个。第三焊盘P3可以构成或布置成在与第二方向D2平行的行中。为了简化描述，下面说明其中第一焊盘至第三焊盘P1、P2和P3中的每一个被描述为单个的示例。
第二半导体芯片300可以在第一半导体芯片200的第二区域R2的顶表面200a上。当在平面图中观察时，第二半导体芯片300可以在第一方向D1上从第一半导体芯片200的第一侧表面200b移位或偏移。第二半导体芯片300可以暴露第一半导体芯片200的第一区域R1的顶表面200a。第二半导体芯片300可以执行与第一半导体芯片200的功能不同的功能。在实现中，第二半导体芯片300可以用作存储器芯片。在实现中，半导体封装1可以包括多个堆叠的第二半导体芯片300。在实现中，可以包括合适数量的第二半导体芯片300。第二半导体芯片300的顶表面可以是有源表面。例如，每个第二半导体芯片300可以具有在其顶表面上暴露的芯片焊盘310。第二半导体芯片300可以通过第一导体360彼此电连接。第一导体360可以是接合线。接合线可以包括例如金或银的金属。第二半导体芯片300可以堆叠在第一半导体芯片200上，这种布置可以帮助减小半导体封装1的大小。
第三半导体芯片400可以堆叠在第二半导体芯片300上。第三半导体芯片400和第二半导体芯片300可以是相同类型的。在实现中，第三半导体芯片400可以是存储器芯片。在实现中，第三半导体芯片400可以具有与第二半导体芯片300相同的大小和存储容量。半导体封装1可以包括多个堆叠的第三半导体芯片400。第三半导体芯片400可以通过第二导体460彼此电连接。第二导体460可以是接合线。第三半导体芯片400中的最下面一个可以在与第一方向D1相反的方向上从第二半导体芯片300中的最上面一个或相对于其移位(例如，偏移或未对准)。第三半导体芯片400可以在平面布置中进行各种改变。在实现中，最下面的第三半导体芯片400可以在第一方向D1上从最上面的第二半导体芯片300或相对于其移位或偏移。在实现中，最下面的第三半导体芯片400和最上面的第二半导体芯片300可以在第三方向D3上彼此对准(例如，芯片的边缘可以对准或共面)。在实现中，可以包括合适数量的第二半导体芯片300和第三半导体芯片400。以下详细描述半导体封装1的电连接。
第一连接器350可以设置在第二半导体芯片300中的一个上，并且可以耦合到第一焊盘P1和第二半导体芯片300中的一个的芯片焊盘310。第二半导体芯片300可以通过第一连接器350和第一焊盘P1耦合到第一半导体芯片200的集成电路部分210。第一连接器350可以是接合线。在实现中，第一导体360可以耦合到第一焊盘P1和第二半导体芯片300中的另一个的芯片焊盘310。
第二连接器450可以设置在第三半导体芯片400中的一个上，并且可以耦合到第二焊盘P2和第三半导体芯片400中的一个的芯片焊盘410。第三半导体芯片400可以通过第二连接器450和第二焊盘P2耦合到第一半导体芯片200的集成电路部分210。第二连接器450可以是接合线。在实现中，第二导体460可以耦合到第二焊盘P2和第三半导体芯片400中的另一个的芯片焊盘410。
第三连接器150可以设置在第一半导体芯片200的第二区域R2上，并且可以耦合到第三焊盘P3和衬底焊盘110。因此，第三焊盘P3可以电连接到外部端子120。第三连接器150可以是接合线。第二半导体芯片300和第三半导体芯片400可以与第三焊盘P3通信信号，该信号可以分别分配到第一焊盘P1和第二焊盘P2。然后，半导体封装1可以提高操作速度。
如果第一半导体芯片200的第一区域R1将被第二半导体芯片300覆盖，则可能难以将第一连接器350和第二连接器450分别直接连接到第一焊盘P1和第二焊盘P2。在实现中，第一半导体芯片200的第一区域R1可以被暴露，使得第一连接器350可以直接连接到第一焊盘P1。同样地，第二连接器450可以直接连接到第二焊盘P2。由于第一半导体芯片200与第二半导体芯片300之间以及第一半导体芯片200与第三半导体芯片400之间的电路径的减小，半导体封装1的操作速度可以相应地增加。
密封剂700可以设置在第一半导体芯片200和第二半导体芯片300之间，并且覆盖第一半导体芯片200的第二区域R2。密封剂700可以覆盖第三焊盘P3。密封剂700可以暴露第一半导体芯片200的第一区域R1。密封剂700可以进一步设置在第一半导体芯片200的第二侧表面200c上，并填充衬底100与第二半导体芯片300中的最下面一个之间的间隙。在这种情况下，密封剂700可以帮助支撑第二半导体芯片300。密封剂700可以包括绝缘聚合物。
粘合层710可以***在衬底100和第一半导体芯片200之间，在各第二半导体芯片300之间，在最上面的第二半导体芯片300和最下面的第三半导体芯片400之间，以及在各第三半导体芯片400之间。粘合层710可以包括绝缘聚合物。
衬底100可以包括覆盖第一半导体芯片200、第二半导体芯片300和位于其上的第三半导体芯片400的模制层800。例如，模制层800可以覆盖第一半导体芯片200的第一区域R1。模制层800可以与第一半导体芯片200的第二区域R2的顶表面200a间隔开(例如，模制层800可以不接触第一半导体芯片200的第二区域R2的顶表面200a)。模制层800可以包括绝缘聚合物(例如，环氧树脂基模塑料)。
在实现中，半导体封装1可以包括单个第二半导体芯片300。在实现中，半导体封装1可以包括单个第三半导体芯片400。在实现中，半导体封装1还可以包括堆叠在第三半导体芯片400上的附加半导体芯片。在这种情况下，第四焊盘可以进一步设置在第一半导体芯片200的顶表面200a上并且电连接到附加的半导体芯片。
图3A示出了示出根据示例性实施例的半导体封装的平面图。图3B示出了沿着图3A的线I-II截取的横截面图。在下文中可以省略与前述内容重复的描述。
参照图1、图3A和图3B，半导体封装2可以包括衬底100、第一半导体芯片200、第二半导体芯片300、第三半导体芯片400、密封剂700和模制层800。衬底100、第一半导体芯片200、第二半导体芯片300、第三半导体芯片400、密封剂700和模制层800可以与上面参考图2A和图2B讨论的那些基本相同。第一焊盘P1、第一连接器350、第三焊盘P3和第三连接器150的布置和电连接可以与上面参考图2A和图2B所讨论的布置和电连接基本相同。
第一连接焊盘161和第二连接焊盘162可以设置在衬底100的顶表面上。当在平面图中观察时，第一连接焊盘161和第二连接焊盘162可以与第一半导体芯片200的第一区域R1相邻并且被第一半导体芯片200暴露。第二连接焊盘162可以比第一连接焊盘161更靠近第一半导体芯片200(例如，第二连接焊盘162可以在第一连接焊盘161和第一连接芯片200之间)。连接线160可以设置在衬底100中，并且可以耦合到第一连接焊盘161和第二连接焊盘162。连接线160可以与衬底焊盘110、导电线130和外部端子120绝缘。
第二连接器450可以耦合到第一连接焊盘161和第三半导体芯片400中的一个的芯片焊盘410。第一连接焊盘161可以通过连接线160电连接到第二连接焊盘162。第四连接器250可以设置在第一半导体芯片200的第一区域R1的顶表面200a上，并且可以耦合到第二焊盘P2和第二连接焊盘162。因此，第三半导体芯片400可以通过第三连接器150、第一连接焊盘161、连接线160、第二连接焊盘162和第四连接器250电连接到第二焊盘P2。第四连接器250可以是接合线。
图4A示出了示出根据示例性实施例的半导体封装的平面图。图4B示出了沿着图4A的线I-II截取的横截面图。在下文中可以省略与前述内容重复的描述。
参照图1、图4A和图4B，半导体封装3可以包括衬底100、第一半导体芯片200、第二半导体芯片300、第三半导体芯片400、密封剂700和模制层800。衬底100、第一半导体芯片200、第二半导体芯片300、第三半导体芯片400、密封剂700和模制层800可以与上面参考图2A和图2B讨论的那些基本相同。第一焊盘P1和第一连接器350的布置和电连接可以与上面参考图2A和图2B所讨论的布置和电连接基本相同。
第二焊盘P2可以设置在第一半导体芯片200的第二区域R2的顶表面200a上。第二连接器450可以耦合到第一连接焊盘161和第三半导体芯片400中的一个的芯片焊盘410。第一连接焊盘161可以通过连接线160电连接到第二连接焊盘162。第二连接焊盘162可以与第一半导体芯片200的第二区域R2相邻。第四连接器250可以设置在第一半导体芯片200的第二区域R2的顶表面200a上，并且可以耦合到第二焊盘P2和第二连接焊盘162。第三半导体芯片400可以通过第二连接器450、第一连接焊盘161、连接线160、第二连接焊盘162和第四连接器250电连接到第二焊盘P2。
第三焊盘P3可以设置在第一半导体芯片200的第一区域R1的顶表面200a上。当在平面图中观察时，第二焊盘P2可以比第一焊盘P1更靠近第一半导体芯片200的第二侧表面200c。第三连接器150可以设置在第一半导体芯片200的第一区域R1上，并且可以耦合到第三焊盘P3和衬底焊盘110。第三焊盘P3可以通过集成电路部分210电连接到第一焊盘P1和第二焊盘P2。
图5A示出了示出根据示例性实施例的半导体封装的平面图。图5B示出了沿着图5A的线I-II截取的横截面图。图6A示出了示出根据示例性实施例的半导体封装的平面图。图6B示出了沿着图6A的线I-II截取的横截面图。在下文中可以省略与前述内容重复的描述。
参照图1、图5A、图5B、图6A和图6B，半导体封装4和半导体封装5中的每一个可以包括衬底100、第一半导体芯片200、第二半导体芯片300、第三半导体芯片400、密封剂700和模制层800。衬底100、第一半导体芯片200、第二半导体芯片300、第三半导体芯片400、密封剂700和模制层800可以与上面参考图2A和图2B讨论的那些基本相同。如参考图2A和图2B所讨论的，第一焊盘P1可以设置在第一半导体芯片200的第一区域R1的顶表面200a上。第二半导体芯片300可以通过第一连接器350耦合到第一焊盘P1。
第二焊盘P2可以设置在第一半导体芯片200的第二区域R2的顶表面200a上。第二焊盘P2、第二连接器450、第一连接焊盘161、第二连接焊盘162、连接线160和第三连接器150的布置和电连接可以与参考图4A和图4B所讨论的布置和电连接基本相同。例如，第三半导体芯片400可以通过第二连接器450、第一连接焊盘161、连接线160、第二连接焊盘162和第四连接器250电连接到第二焊盘P2。
第三焊盘P3可以设置在第一半导体芯片200的第二区域R2的顶表面200a上。第三连接器150可以设置在第一半导体芯片200的第二区域R2上，并且可以耦合到第三焊盘P3和衬底焊盘110。
参照图5A和图5B，当在平面图中观察时，第二焊盘P2可以比第三焊盘P3更靠近第一半导体芯片200的第二侧表面200c。第二连接焊盘162与第一半导体芯片200的第二侧表面200c之间的距离可以小于衬底焊盘110与第一半导体芯片200的第二侧表面200c之间的距离。
参照图6A和图6B，当在平面图中观察时，第三焊盘P3可以比第二焊盘P2更靠近第一半导体芯片200的第二侧表面200c。衬底焊盘110可以比第二连接焊盘162更靠近第一半导体芯片200的第二侧表面200c。
图7示出了示出根据示例性实施例的半导体封装的沿着图2A的线I-II截取的横截面图。在下文中可以省略与前述内容重复的描述。
参照图1、图2A和图7，除了衬底100、第一半导体芯片200、第二半导体芯片300、第三半导体芯片400、密封剂700和模制层800之外，半导体封装6还可以包括支撑结构290。
支撑结构290可以***在衬底100和最下面的第二半导体芯片300之间，从而支撑第二半导体芯片300。支撑结构290可以与第一半导体芯片200的第二侧表面200c间隔开。支撑结构290可以暴露衬底焊盘110。支撑结构290可以不电连接到衬底100、第一半导体芯片200、第二半导体芯片300和第三半导体芯片400中的任一个(例如，可以电隔离)。虚设间隔物芯片可以用作支撑结构290。
密封剂700可以***在衬底100和最下面的第二半导体芯片300之间。
衬底100、第一半导体芯片200、第二半导体芯片300、第三半导体芯片400和模制层800可以与上面参考图2A和图2B讨论的那些基本相同。第一焊盘至第三焊盘P1、P2和P3的布置和电连接可以与上面参考图2A和图2B所讨论的布置和电连接基本相同。在实现中，第一焊盘至第三焊盘P1、P2和P3的布置和电连接可以与上面参考图3A和图3B、图4A和图4B、图5A和图5B或图6A和图6B所讨论的示例的布置和电连接基本相同。
图8示出了示出根据示例性实施例的半导体封装的横截面图。在下文中可以省略与前述内容重复的描述。
参照图1和图8，半导体封装7可以包括衬底100、第一半导体芯片200、第二半导体芯片300、第三半导体芯片400、密封剂700和模制层800。衬底100、第一半导体芯片200、第二半导体芯片300、第三半导体芯片400、密封剂700和模制层800可以与上面参考图2A和图2B讨论的那些基本相同。第一焊盘P1和第一连接器350的布置和电连接可以与上面参考图2A和图2B所讨论的布置和电连接基本相同。
第二焊盘P2可以设置在第一半导体芯片200的底表面上。第一半导体芯片200的底表面可以与第一半导体芯片200的顶表面200a相对。第三半导体芯片400可以通过第二连接器450、第一连接焊盘161、连接线160、第二连接焊盘162和第四连接器250电连接到第二焊盘P2。第一连接焊盘161可以被第一半导体芯片200暴露，并且当在平面图中观察时，第二连接焊盘162可以与第一半导体芯片200重叠或位于第一半导体芯片200之下。第四连接器250可以***在第二连接焊盘162和第二焊盘P2之间。第四连接器250可以包括凸块、焊料和柱中的一种或多种。
第三焊盘P3可以设置在第一半导体芯片200的底表面上。第三连接器150可以***在衬底100和第一半导体芯片200之间，从而连接到衬底焊盘110和第三焊盘P3。第三连接器150可以包括凸块、焊料和柱中的一种或多种。第三焊盘P3可以通过集成电路部分210电连接到第一焊盘P1和第二焊盘P2。在实现中，第一半导体芯片200可以包括贯穿电极。
在实现中，第二焊盘P2和第三焊盘P3中的一个可以设置在第一半导体芯片200的顶表面200a上。当第二焊盘P2设置在第一半导体芯片200的顶表面200a上时，接合线可以用作第四连接器250。当第三焊盘P3设置在第一半导体芯片200的顶表面200a上时，接合线可以用作第三连接器150。
图9示出了示出根据示例性实施例的半导体封装的横截面图。在下文中可以省略与前述内容重复的描述。
参照图1和图9，除了衬底100、第一半导体芯片200、第二半导体芯片300、第三半导体芯片400、密封剂700和模制层800之外，半导体封装8还可以包括第四半导体芯片500、第五半导体芯片600和第六半导体芯片1200。衬底100、第一半导体芯片200、第二半导体芯片300、第三半导体芯片400、第一焊盘P1、第二焊盘P2和第三焊盘P3可以与上面参考图2A和图2B讨论的那些基本相同。在实现中，第一焊盘至第三焊盘P1、P2和P3的布置和电连接可以与上面参考图3A和图3B、图4A和图4B、图5A和图5B或图6A和图6B所讨论的示例的布置和电连接基本相同。
多个第四半导体芯片500可以堆叠在第三半导体芯片400上。第四半导体芯片500可以是存储器芯片。第四半导体芯片500可以通过第三导体660彼此电连接。第三导体660可以是接合线。多个第五半导体芯片600可以堆叠在第四半导体芯片500上。第五半导体芯片600可以是存储器芯片。第五半导体芯片600可以通过第四导体760彼此电连接。第四连接器760可以是接合线。
第六半导体芯片1200可以设置在衬底100的顶表面上。第六半导体芯片1200可以与第一半导体芯片200间隔开。第六半导体芯片1200可以用作缓冲芯片。第六半导体芯片1200可以具有第一导电焊盘Pal、第二导电焊盘Pa2和第三导电焊盘Pa3，第一导电焊盘至第三导电焊盘Pa1、Pa2和Pa3可以设置在第六半导体芯片1200的顶表面上。第一导电焊盘至第三导电焊盘Pa1、Pa2和Pa3可以彼此间隔开。第一导电焊盘至第三导电焊盘Pa1、Pa2和Pa3可以包括金属。第一导电焊盘Pa1和第二导电焊盘Pa2可以通过集成电路部分1210电连接到第三导电焊盘Pa3。
第五连接器650可以设置在第四半导体芯片500中的一个上，并且可以耦合到第一导电焊盘Pa1和第四半导体芯片500中的一个的芯片焊盘510。第四半导体芯片500可以通过第五连接器650电连接到第六半导体芯片1200。第五连接器650可以是接合线。在实现中，第五连接器650可以通过衬底100耦合到第一导电焊盘Pal，作为上面参考图3A和图3B讨论的第二连接器450和第二焊盘P2之间的连接。
第一导电连接焊盘1161和第二导电连接焊盘1162可以设置在衬底100的顶表面上。第六连接器750可以设置在第五半导体芯片600中的一个上，并且可以耦合到第一导电连接焊盘1161和第五半导体芯片600中的一个的芯片焊盘610。导电连接线1160可以设置在衬底100中，并且可以电连接到第一导电连接焊盘116I和第二导电连接焊盘1162。导电连接器1250可以耦合到第二导电连接焊盘1162和第二导电焊盘Pa2。导电连接器1250可以是接合线。然后，第五半导体芯片600可以电连接到第二导电焊盘Pa2。
导电衬底焊盘1110可以设置在衬底100的顶表面上。外部导电端子1120可以设置在衬底100的底表面上。传输到外部导电端子1120和从外部导电端子1120传输的信号可以与传输到外部端子120和从外部端子120传输的信号无关。外部导电端子1120可以与外部端子120绝缘。外部导电端子1120可以通过衬底100内的导电线130电连接到导电衬底焊盘1110。导电衬底焊盘1110可以与衬底焊盘110间隔开并且与衬底焊盘110电绝缘。
第七连接器1150可以设置在第六半导体芯片1200上，并且可以耦合到第三导电焊盘Pa3和导电衬底焊盘1110。因此，第三导电焊盘Pa3可以电连接到外部导电端子1120。第七连接器1150可以是接合线。第四半导体芯片500和第五半导体芯片600可以与第三导电焊盘Pa3通信信号，该信号可以分别分配到第一导电焊盘Pa1和第二导电焊盘Pa2。然后，半导体封装8可以提高操作速度。
第四半导体芯片500和第五半导体芯片600可以通过与用于操作第二半导体芯片300和第三半导体芯片400的信道不同的信道进行操作。第四半导体芯片500和第五半导体芯片600可以电连接到第六半导体芯片1200的集成电路部分1210。第四半导体芯片至第六半导体芯片500、600和1200可以独立于第一半导体芯片至第三半导体芯片200、300和400操作。
粘合层710可以进一步***在衬底100和第六半导体芯片1200之间，在最上面的第三半导体芯片400和最下面的第四半导体芯片500之间，在各第四半导体芯片500之间，在最上面的第四半导体芯片500和最下面的第五半导体芯片600之间，以及在各第五半导体芯片600之间。如参考图8所讨论的，衬底100和最下面的第二半导体芯片300之间可以设置有支撑结构290。在实现中，半导体封装8可以包括单个第四半导体芯片500或单个第五半导体芯片600。
如本领域中常见的，以功能块、单元和/或模块为单位在附图中描述并示出了实施例。本领域技术人员将理解，这些块、单元和/或模块通过诸如逻辑电路、分立组件、微处理器、硬连线电路、存储器元件、布线连接等的电子(或光学)电路物理地实现，其中所述电子(或光学)电路可以使用基于半导体的制造技术或其它制造技术来形成。在块、单元和/或模块由微处理器等实现的情况下，它们可以使用软件(例如，微代码)来编程以执行本文讨论的各种功能，并且可以可选地由固件和/或软件驱动。备选地，每个块、单元和/或模块可以通过专用硬件实现或实现为执行一些功能的专用硬件和执行其他功能的处理器(例如，一个或多个编程的微处理器和相关联的电路)的组合。此外，在不脱离本文的范围的情况下，实施例的每个块、单元和/或模块可以物理地分成两个或更多个交互和分立的块、单元和/或模块。此外，在不脱离本文的范围的情况下，实施例的块、单元和/或模块可以物理地组合成更复杂的块、单元和/或模块。
通过总结和回顾，半导体封装可以配置为使得半导体芯片安装在印刷电路板(PCB)上，并且接合线或凸块可以用于将半导体芯片电连接到印刷电路板。随着电子工业的发展，集成电路可以具有高性能和紧凑性。
根据实施例，第二半导体芯片和第三半导体芯片可以堆叠在第一半导体芯片上。因此，半导体封装的尺寸可以相应地变得大小紧凑。第一焊盘可以设置在被第二半导体芯片暴露的第一半导体芯片的顶表面上。第二半导体芯片可以耦合到第一焊盘而不穿过衬底。然后可以减小第一半导体芯片和第二半导体芯片之间的电路径的长度。第二半导体芯片和第三半导体芯片可以与第一半导体芯片的集成电路部分通信信号和/或数据，该信号和/或数据可以分配到相应的第一焊盘和第二焊盘。半导体封装可具有增加的操作速度。
实施例可以提供包括堆叠的半导体芯片在内的半导体封装。
实施例可以提供紧凑的半导体封装。
实施例可以提供能够高速操作的半导体封装。
本文已经公开了示例实施例，并且尽管采用了特定术语，但是它们仅用于且将被解释为一般的描述性意义，而不是为了限制的目的。在一些情况下，截至本申请递交之时，本领域技术人员清楚，除非另有明确说明，否则结合特定实施例描述的特征、特性和/或元素可以单独使用或与结合其他实施例描述的特征、特性和/或元素相结合。因此，本领域技术人员将理解，在不脱离如所附权利要求中阐述的本发明的精神和范围的前提下，可以进行形式和细节上的各种改变。

Claims (20)

1.一种半导体封装，包括：
包括外部端子的衬底；
所述衬底上的第一半导体芯片，在平面图中所述第一半导体芯片具有第一区域和第二区域；
所述第一半导体芯片的第二区域上的至少一个第二半导体芯片，所述至少一个第二半导体芯片暴露所述第一半导体芯片的第一区域的顶表面；以及
所述至少一个第二半导体芯片上的至少一个第三半导体芯片，
其中：
所述第一半导体芯片包括：
第一焊盘，电连接到所述至少一个第二半导体芯片；
第二焊盘，电连接到所述至少一个第三半导体芯片；以及
第三焊盘，电连接到所述外部端子，
所述第一焊盘在所述第一区域的顶表面上，并且
所述第二焊盘和所述第三焊盘中的至少一个在所述第二区域的顶表面上。
2.根据权利要求1所述的半导体封装，其中：
所述第一半导体芯片中包括集成电路部分，并且
所述第一焊盘和所述第二焊盘通过所述集成电路部分而电连接到所述第三焊盘。
3.根据权利要求2所述的半导体封装，其中，信号能够通过所述第三焊盘传输到所述第一焊盘和所述第二焊盘以及从所述第一焊盘和所述第二焊盘传输。
4.根据权利要求1所述的半导体封装，还包括所述至少一个第三半导体芯片上的第二连接器，所述第二连接器耦合到所述第二焊盘和所述至少一个第三半导体芯片的芯片焊盘，
其中，所述第二焊盘在所述第一半导体芯片的第一区域的顶表面E。
5.根据权利要求1所述的半导体封装，还包括：
所述衬底上的第一连接焊盘；
所述至少一个第三半导体芯片上的第二连接器，所述第二连接器耦合到所述第一连接焊盘和所述至少一个第三半导体芯片的芯片焊盘，
所述衬底中的连接线，电连接到所述第一连接焊盘；
所述衬底上的第二连接焊盘，电连接到所述连接线；以及
所述第一半导体芯片上的第三连接器，所述第三连接器耦合到所述第二连接焊盘和所述第二焊盘。
6.根据权利要求5所述的半导体封装，其中，所述第二焊盘在所述第一半导体芯片的第二区域的顶表面上。
7.根据权利要求1所述的半导体封装，还包括：第一连接器，在所述至少一个第二半导体芯片的顶表面上并且耦合到所述第一焊盘。
8.根据权利要求1所述的半导体封装，还包括所述衬底与所述至少一个第二半导体芯片之间的支撑结构，
其中，所述支撑结构与所述第一半导体芯片间隔开。
9.根据权利要求1所述的半导体封装，还包括：所述第一半导体芯片与所述至少一个第二半导体芯片之间的密封剂，
其中，所述密封剂暴露所述第一半导体芯片的第一区域的顶表面。
10.根据权利要求9所述的半导体封装，其中，所述密封剂延伸到所述第一半导体芯片的侧表面上，并且填充所述衬底与所述至少一个第二半导体芯片之间的间隙。
11.根据权利要求1所述的半导体封装，其中：
所述第一半导体芯片中包括缓冲电路，
所述至少一个第二半导体芯片包括存储器芯片，并且
所述至少一个第三半导体芯片包括存储器芯片。
12.根据权利要求1所述的半导体封装，其中：
所述至少一个第二半导体芯片包括多个堆叠的第二半导体芯片，并且
所述第一焊盘电连接到所述多个堆叠的第二半导体芯片。
13.根据权利要求1所述的半导体封装，其中：
所述至少一个第三半导体芯片包括多个堆叠的第三半导体芯片，
所述第二焊盘电连接到所述多个堆叠的第三半导体芯片。
14.根据权利要求1所述的半导体封装，还包括：所述衬底上的模制层，覆盖所述第一半导体芯片和所述至少一个第二半导体芯片，
其中，所述模制层覆盖所述第一半导体芯片的第一区域，并且与所述第一半导体芯片的第二区域的顶表面间隔开。
15.一种半导体封装，包括：
衬底；
所述衬底上的第一半导体芯片，包括第一焊盘、第二焊盘和第三焊盘，所述第一焊盘、所述第二焊盘和所述第三焊盘在所述第一半导体芯片的顶表面上；
所述第一半导体芯片上的至少一个第二半导体芯片，所述至少一个第二半导体芯片部分地暴露所述第一半导体芯片的顶表面；以及
所述至少一个第二半导体芯片上的至少一个第三半导体芯片，
其中：
所述第一焊盘电连接到所述至少一个第二半导体芯片，
所述第二焊盘电连接到所述至少一个第三半导体芯片，
所述第三焊盘电连接到所述第一焊盘和所述第二焊盘，并且
所述至少一个第二半导体芯片暴露所述第一焊盘，并且覆盖所述第二焊盘和所述第三焊盘中的至少一个。
16.根据权利要求15所述的半导体封装，其中：
所述衬底在其底表面上包括外部端子，并且
所述第三焊盘通过衬底耦合到所述外部端子。
17.根据权利要求15所述的半导体封装，其中，信号能够通过所述第三焊盘传输到所述第一焊盘和所述第二焊盘以及从所述第一焊盘和所述第二焊盘传输。
18.根据权利要求15所述的半导体封装，还包括所述衬底与所述第二半导体芯片之间的支撑结构。
19.根据权利要求15所述的半导体封装，其中：
所述至少一个第二半导体芯片包括多个堆叠的第二半导体芯片，并且
所述至少一个第三半导体芯片包括多个堆叠的第三半导体芯片。
20.根据权利要求15所述的半导体封装，还包括：
所述至少一个第二半导体芯片上的第一接合线，耦合到所述第一焊盘；
所述至少一个第三半导体芯片上的第二接合线，耦合到所述第二焊盘；以及
所述第一半导体芯片上的第三接合线，耦合到所述第三焊盘。
CN201910088560.XA 2018-02-05 2019-01-29 半导体封装 Pending CN110120387A (zh)

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