CN110119331B

CN110119331B - Clock switching method and device, server and clock system

Info

Publication number: CN110119331B
Application number: CN201810123462.0A
Authority: CN
Inventors: 黄子龙; 郑庆宗
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-02-07
Filing date: 2018-02-07
Publication date: 2021-10-01
Anticipated expiration: 2038-02-07
Also published as: CN110119331A

Abstract

The embodiment of the application provides a clock switching method, a clock switching device, a server and a clock system, wherein the method comprises the steps of receiving a standby clock signal through a standby clock signal input port of a switching circuit when a master clock signal is detected to be abnormal; reconstructing the phase of the standby clock signal and generating a reconstructed clock signal, wherein the phase of the reconstructed clock signal is consistent with the phase of the main clock signal before the abnormality; compensating the phase of the reconstructed clock signal according to the standby clock signal and the preset phase adjusting speed, generating a compensated clock signal, outputting the compensated clock signal through a clock signal output port of the switching circuit, wherein the phase of the compensated clock signal is consistent with the phase of the standby clock signal. The clock switching method provided by the embodiment of the application can ensure that the phases of the clock signals of the TSCs provided for the processors are consistent, and ensure the normal work of the operating system of the server.

Description

Clock switching method and device, server and clock system

Technical Field

The present application relates to the field of computers, and in particular, to a clock switching method, apparatus, server, and clock system.

Background

The server includes a processor, and a timestamp Counter (TSC) is located internal to the processor for providing a clock signal for an operating system running on the server. In a clock system, a clock source of the TSC adopts a redundancy design, and the clock source is provided for the TSC through a main clock plate and a standby clock plate. When the main clock board fails, the switching circuit corresponding to the processor switches the clock source of the TSC provided for the processor to the standby clock board, and the standby clock board replaces the main clock board to continue working, so that the processing service of the server is prevented from being influenced. Because there may be a phase difference between the clock signal provided by the standby clock board and the clock signal provided by the main clock board, the clock signal provided by the TSC for the operating system of the server is unstable, and further stable operation of the server is affected. In order to solve the problem of inconsistent phases of the master and slave clock signals, the switching circuit usually reconstructs the phase of the slave clock signal provided by the slave clock board according to the phase difference between the clock signals provided by the master and slave clock boards, and the reconstructed phase of the clock signal is consistent with the phase of the master clock signal provided by the master clock board.

For a multiprocessor server, the TSCs of the processors all provide high-precision clock signals for the same operating system kernel. The TSCs in the processors have the same counting frequency and phase, and the operating system of the multiprocessor server can normally work. It is ensured that the clock signals of the TSCs provided to the processors in the clock system are of uniform phase and frequency. In a multiprocessor server, processing deviations when different switching circuits reconstruct the same clock signal are different, so that phase deviations exist between clock signals obtained after different switching circuits perform phase reconstruction on standby clock signals, and may also be different, which causes the phase deviations of clock signals of TSCs provided for each processor to be different, thereby affecting the normal operation of an operating system of the server.

Disclosure of Invention

The embodiment of the application provides a clock switching method, a clock switching device, a server and a clock system, which can ensure that clock signals provided for TSCs of processors in a multiprocessor server are consistent, and ensure that an operating system on the server can work normally.

In a first aspect, an embodiment of the present application provides a clock switching method, including: when a master clock signal is normal, a first circuit receives the master clock signal and then provides the master clock signal to a first load, and the master clock signal is provided by a master clock circuit connected with the first circuit. When the main clock signal is abnormal, the first circuit receives a standby clock signal, and the standby clock signal is provided by a standby clock circuit connected with the first circuit. And the first circuit reconstructs the phase of the standby clock signal to generate a first reconstructed clock signal, and the phase of the first reconstructed clock signal is consistent with the phase of the main clock signal before abnormality. The first circuit provides the first reconstructed clock signal to the first load. The first circuit continuously adjusts the phase of the first reestablished clock signal according to the standby clock signal and a preset phase adjustment speed to generate a plurality of adjustment clock signals, the phase of the adjustment clock signal generated last in the plurality of adjustment clock signals is equal to the phase of the standby clock signal, and except for the adjustment clock signal generated last, the phases of other adjustment clock signals in the plurality of adjustment clock signals are between the phase of the first reestablished clock signal and the phase of the standby clock signal. The first circuit provides the adjusted clock signal generated after adjustment to the first load after each adjustment.

The phase of the reconstructed clock signal is adjusted according to the preset phase adjusting speed, so that the clock signal with the phase consistent with the phase of the standby clock signal is generated, the phases of the clock signals adjusted by the first circuits are ensured to be changed slowly and consistent, the phases of the clock signals provided by the TSCs of the processors by the first circuits are consistent, the unstable operation of a multiprocessor operating system is avoided, and the accumulated error possibly caused by multiple times of clock switching is also avoided.

In a possible embodiment, the preset phase adjustment speed is in a range of 1-10 microseconds/second.

In one possible implementation, the clock switching method further includes: when the main clock signal is normal, the second circuit receives the main clock signal and then provides the main clock signal for the second load, and the main clock signal is provided by the main clock circuit connected with the second circuit. When the main clock signal is abnormal, the second circuit receives a standby clock signal, and the standby clock signal is provided by the standby clock circuit connected with the second circuit. And the second circuit reconstructs the phase of the standby clock signal to generate a second reconstructed clock signal, and the phase of the second reconstructed clock signal is consistent with the phase of the main clock signal before abnormality. The second circuit provides the second reconstructed clock signal to the second load. And the second circuit continuously adjusts the phase of the second reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of compensation clock signals, wherein the phase of the last generated compensation clock signal in the plurality of compensation clock signals is equal to the phase of the standby clock signal, and except for the last generated compensation clock signal, the phases of other compensation clock signals in the plurality of compensation clock signals are between the phase of the second reconstructed clock signal and the phase of the standby clock signal. The second circuit provides the compensation clock signal generated after adjustment to the second load after each adjustment.

Because processing deviation exists when the first circuit and the second circuit carry out phase reconstruction, the phase deviation exists between the first reconstruction clock signal and the second reconstruction clock signal, and the phase adjustment is respectively carried out on the first reconstruction clock signal and the second reconstruction clock signal, so that the phases of the finally generated compensation clock signal and the adjustment clock signal are consistent with the phase of the standby clock signal, and the phases of the compensation clock signal and the adjustment clock signal are consistent and have no deviation.

In one possible embodiment, the second circuit and the first circuit have the same structure; the first load may include one or more processors and the second load may also include one or more processors.

In one possible embodiment, the first circuit includes a first control circuit and a first phase-locked loop circuit, and the first control circuit is connected to the first phase-locked loop circuit. The clock switching method further comprises the following steps: when the main clock signal is abnormal, the first control circuit sets the working state of the first phase-locked loop circuit to be a phase reconstruction state. The first circuit reconstructs a phase of the standby clock signal to generate a first reconstructed clock signal, and includes: and when the working state of the first phase-locked loop circuit is a phase reconstruction state, reconstructing the phase of the standby clock signal to generate a first reconstruction clock signal. The clock switching method further comprises the following steps: the first control circuit determines that the first phase-locked loop circuit generates the first reconstructed clock signal, and sets the working state of the first phase-locked loop circuit to be a phase compensation state. The first circuit continuously adjusts the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjusted clock signals, and the method comprises the following steps: and when the working state of the first phase-locked loop circuit is a phase compensation state, continuously adjusting the phase of the first reestablished clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjustment clock signals.

The first circuit comprises a first control circuit and a first phase-locked loop circuit, the first phase-locked loop circuit is controlled to work in a phase reconstruction state to carry out phase reconstruction on the standby clock signal to generate a first reconstruction clock signal, and then the first phase-locked loop circuit is controlled to work in a phase compensation state to carry out phase adjustment on the first reconstruction clock signal, so that the phase of the finally generated adjusted clock signal is equal to the phase of the standby clock signal, and the circuit structure of the first circuit is simplified.

In one possible embodiment, the first control circuit writes phase reconstruction configuration information to an operating status register in the first phase-locked loop circuit when the master clock signal is abnormal. The phase reconstruction configuration information is used to indicate that the first phase-locked loop circuit is operating in a phase reconstruction state. And the first control circuit writes phase compensation configuration information into a working state register in the first phase-locked loop circuit after determining that the first phase-locked loop circuit generates the first reestablished clock signal. The phase compensation configuration information is used to indicate that the first phase-locked loop circuit is operating in a phase compensation state.

In one possible implementation, the first circuit provides a clock signal to the first load through a clock signal output port of the first circuit, the clock signal output port of the first circuit is connected to a feedback clock signal input port of the first circuit, and the feedback clock signal input port of the first circuit is connected to a feedback input port of the first phase-locked loop circuit. The clock switching method further comprises the following steps: before the first phase-locked loop circuit reconstructs the phase of the standby clock signal, the feedback input port of the first phase-locked loop circuit is closed, and the clock signal output by the clock signal output port of the first circuit is stopped from being received from the feedback input port of the first phase-locked loop circuit. The clock switching method further comprises the following steps: before the first phase-locked loop circuit continuously adjusts the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjusted clock signals, the oscillator feedback port of the first phase-locked loop circuit is closed, the clock signal provided by the oscillator is stopped being received from the oscillator feedback port of the first phase-locked loop circuit, and the feedback input port of the first phase-locked loop circuit is opened. When the working state of the first phase-locked loop circuit is a phase compensation state, continuously adjusting the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjusted clock signals, including: and when the working state of the first phase-locked loop circuit is a phase compensation state, continuously adjusting the phase of the first reestablished clock signal according to the standby clock signal, the clock feedback signal received from the feedback input port of the phase-locked loop circuit and the preset phase adjustment speed to generate a plurality of adjusted clock signals.

In the phase compensation process, the phase of the reconstructed clock signal is compensated according to the standby clock signal and the feedback clock signal output by the clock signal output port of the first circuit, so that the phase of the finally generated adjustment clock signal output by the clock signal output port of the first circuit is consistent with the phase of the standby clock signal, and the phases of the clock signals provided by all the first circuits to all the processors are completely consistent.

In one possible implementation, when the operating state is a phase reconstruction state, the first phase-locked loop circuit reconstructs a phase of the standby clock signal to generate a first reconstructed clock signal, including: and when the working state of the first phase-locked loop circuit is a phase reconstruction state, reconstructing the phase of the standby clock signal according to the phase difference to generate a first reconstruction clock signal, wherein the phase difference is the phase difference between the standby clock signal and the main clock signal before abnormality.

In one possible embodiment, the phase difference is a phase difference between the standby clock signal and a master clock signal last determined by the first circuit before the abnormality.

In a possible implementation, the frequency of the standby clock signal is determined according to an average value of the frequencies of the main clock signals provided by the main clock circuit in a preset time period.

By adopting the two clock circuits to supply power to the processors in the multiprocessor server system, the stability of the clock source is improved, the situation that a single stable accurate clock source is adopted to simultaneously provide clock signals for each processor through the main clock circuit and the standby clock circuit is avoided, and the clock cost of the clock system is reduced.

In a second aspect, an embodiment of the present application further provides a clock switching apparatus, which is used for executing the clock switching method of the first aspect, and has the same technical features and technical effects. This application will not be described in detail herein.

A second aspect of the embodiments of the present application provides a clock switching apparatus, including a first circuit, where the first circuit is connected to a master clock circuit, a standby clock circuit, and a first load, respectively.

The first circuit is configured to provide a master clock signal to the first load after receiving the master clock signal when the master clock signal is normal, where the master clock signal is provided by the master clock circuit;

the first circuit is further configured to receive a standby clock signal when the master clock signal is abnormal, the standby clock signal being provided by the standby clock circuit.

The first circuit is further configured to reconstruct a phase of the standby clock signal to generate a first reconstructed clock signal, where the phase of the first reconstructed clock signal is consistent with a phase of the master clock signal before the abnormality.

The first circuit is further configured to provide the first reconstructed clock signal to the first load.

The first circuit is further configured to continuously adjust a phase of the first reconstructed clock signal according to the standby clock signal and a preset phase adjustment speed to generate a plurality of adjustment clock signals, where a phase of a last adjustment clock signal generated in the plurality of adjustment clock signals is equal to a phase of the standby clock signal, and except for the last adjustment clock signal generated in the plurality of adjustment clock signals, phases of other adjustment clock signals in the plurality of adjustment clock signals are between the phase of the first reconstructed clock signal and the phase of the standby clock signal;

the first circuit is further configured to provide the adjusted clock signal generated after adjustment to the first load after each adjustment.

In a possible implementation, the clock switching apparatus further includes: a second circuit; the second circuit is respectively connected with the main clock circuit, the standby clock circuit and a second load;

the second circuit is configured to provide the master clock signal to the second load after receiving the master clock signal when the master clock signal is normal, where the master clock signal is provided by the master clock circuit;

the second circuit is further configured to receive a standby clock signal when the master clock signal is abnormal, the standby clock signal being provided by the standby clock circuit;

the second circuit is further configured to reconstruct a phase of the standby clock signal to generate a second reconstructed clock signal, where the phase of the second reconstructed clock signal is consistent with the phase of the master clock signal before the abnormality;

the second circuit is further configured to provide the second reconstructed clock signal to the second load;

the second circuit is further configured to continuously adjust a phase of the second reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of compensation clock signals, a phase of a last generated compensation clock signal of the plurality of compensation clock signals is equal to a phase of the standby clock signal, and except for the last generated compensation clock signal, phases of other compensation clock signals of the plurality of compensation clock signals are between the phase of the second reconstructed clock signal and the phase of the standby clock signal;

the second circuit is further configured to provide the compensated clock signal generated after the adjustment to the second load after each adjustment.

In one possible embodiment, the first circuit includes a first control circuit and a first phase-locked loop circuit, and the first control circuit is connected to the first phase-locked loop circuit;

the first control circuit is used for setting the working state of the first phase-locked loop circuit to be a phase reconstruction state when the main clock signal is abnormal;

the first phase-locked loop circuit is used for reconstructing the phase of the standby clock signal to generate a first reconstructed clock signal when the working state is a phase reconstruction state;

the first control circuit is further configured to determine that the first phase-locked loop circuit generates the first reconstructed clock signal, and set an operating state of the first phase-locked loop circuit to a phase compensation state;

and the first phase-locked loop circuit is further configured to, when the operating state is the phase compensation state, continuously adjust the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjustment clock signals.

In one possible implementation, the first circuit provides a clock signal to the first load through a clock signal output port of the first circuit, the clock signal output port of the first circuit is connected to a feedback clock signal input port of the first circuit, and the feedback clock signal input port of the first circuit is connected to a feedback input port of the first phase-locked loop circuit;

the first phase-locked loop circuit is further configured to close a feedback input port of the first phase-locked loop circuit before reconstructing a phase of the standby clock signal, and stop receiving the clock signal output by the clock signal output port of the first circuit from the feedback input port of the first phase-locked loop circuit;

the first phase-locked loop circuit is further configured to, before continuously adjusting the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjusted clock signals, close an oscillator feedback port of the first phase-locked loop circuit, stop receiving the clock signal provided by the oscillator from the oscillator feedback port of the first phase-locked loop circuit, and open a feedback input port of the first phase-locked loop circuit;

the first phase-locked loop circuit is further configured to, when the operating state is the phase compensation state, continuously adjust the phase of the first reconstructed clock signal according to the standby clock signal, a clock feedback signal received from a feedback input port of the phase-locked loop circuit, and the preset phase adjustment speed to generate a plurality of adjusted clock signals.

In a possible implementation manner, the first phase-locked loop circuit is specifically configured to, when the operating state is a phase reconstruction state, reconstruct a phase of the standby clock signal according to a phase difference, so as to generate a first reconstructed clock signal, where the phase difference is a phase difference between the standby clock signal and the master clock signal before the abnormality.

In a third aspect, an embodiment of the present application further provides a clock switching apparatus, configured to execute the clock switching method according to the first aspect, and have the same technical features and technical effects. This application will not be described in detail herein.

A third aspect of the embodiments of the present application provides a clock switching apparatus, including:

the first clock signal acquisition module is used for receiving a main clock signal and then providing the main clock signal to a first load when the main clock signal is normal, wherein the main clock signal is provided by a main clock circuit connected with the first clock signal acquisition module;

the first clock signal acquisition module is further configured to receive a standby clock signal when the main clock signal is abnormal, where the standby clock signal is provided by a standby clock circuit connected to the first clock signal acquisition module;

the first reconstruction module is used for reconstructing the phase of the standby clock signal to generate a first reconstructed clock signal, and the phase of the first reconstructed clock signal is consistent with the phase of the main clock signal before abnormality; providing the first recreated clock signal to the first load;

a first adjusting module, configured to continuously adjust a phase of the first reconstructed clock signal according to the standby clock signal and a preset phase adjustment speed to generate a plurality of adjusted clock signals, where a phase of a last generated adjusted clock signal among the plurality of adjusted clock signals is equal to a phase of the standby clock signal, and except for the last generated adjusted clock signal, phases of other adjusted clock signals among the plurality of adjusted clock signals are between the phase of the first reconstructed clock signal and the phase of the standby clock signal; providing the adjusted clock signal generated after adjustment to the first load after each adjustment.

In a possible implementation, the clock switching apparatus further includes:

the second clock signal acquisition module is used for receiving the main clock signal and then providing the main clock signal to a second load when the main clock signal is normal, wherein the main clock signal is provided by a main clock circuit connected with the second clock signal acquisition module;

the second clock signal acquisition module is further configured to receive a standby clock signal when the master clock signal is abnormal, where the standby clock signal is provided by a standby clock circuit connected to the second clock signal acquisition module;

the second reconstruction module is used for reconstructing the phase of the standby clock signal to generate a second reconstructed clock signal, and the phase of the second reconstructed clock signal is consistent with the phase of the main clock signal before abnormality; providing the second reconstructed clock signal to the second load;

a second adjusting module, configured to continuously adjust a phase of the second reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of compensation clock signals, where a phase of a last generated compensation clock signal among the plurality of compensation clock signals is equal to a phase of the standby clock signal, and except for the last generated compensation clock signal, phases of other compensation clock signals among the plurality of compensation clock signals are between the phase of the second reconstructed clock signal and the phase of the standby clock signal; providing the compensated clock signal generated after adjustment to the second load after each adjustment.

In a possible embodiment, the second reconstruction module is the same as the first reconstruction module, and the second adjustment module is the same as the first adjustment module; the first load may include one or more processors and the second load may also include one or more processors.

In a possible implementation, the clock switching apparatus further includes:

the first control module is used for setting the first reconstruction module to be in a working state when the main clock signal is abnormal;

the first control module is further configured to set the first adjustment module to a working state after it is determined that the first reconstruction module generates the first reconstruction clock signal.

In a possible implementation manner, the clock switching device provides a clock signal to the first load through a clock signal output port of the clock switching device, the clock signal output port of the clock switching device is connected with a feedback clock signal input port of the clock switching device, and the feedback clock signal input port of the clock switching device is connected with the feedback input port of the first adjusting module;

the first control module is further configured to close the feedback input port of the first adjustment module before the first reconstruction module reconstructs the phase of the standby clock signal, and stop receiving the clock signal output by the clock signal output port of the clock switching device from the feedback input port of the first adjustment module;

the first control module is further configured to close an adjustment feedback port of the first adjustment module, stop receiving the clock signal provided by the first adjustment module from the adjustment feedback port of the first adjustment module, and open a feedback input port of the first adjustment module before the first adjustment module continuously adjusts the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjustment clock signals;

the first adjusting module is further configured to continuously adjust the phase of the first reconstructed clock signal according to the standby clock signal, a clock feedback signal received from a feedback input port of the first adjusting module, and the preset phase adjustment speed to generate a plurality of adjusted clock signals.

In a possible implementation manner, the first reconstructing module is further configured to reconstruct a phase of the standby clock signal according to a phase difference, so as to generate a first reconstructed clock signal, where the phase difference is a phase difference between the standby clock signal and the master clock signal before the abnormality.

In a possible implementation, the clock switching apparatus further includes: and the second control module is used for setting the second modeling block to be in a working state when the main clock signal is abnormal. The second control module is further configured to set the second adjusting module to a working state after determining that the second reconstruction clock signal is generated by the second reconstruction module. The communication modes of the second control module, the second adjusting module and the second reconstructing module are the same as the communication modes of the first control module, the first adjusting module and the first reconstructing module, and the communication modes of the second control module, the second adjusting module and the second reconstructing module can refer to the communication modes of the first control module, the first adjusting module and the first reconstructing module, and details are not repeated here.

In a fourth aspect, an embodiment of the present application further provides a server, which includes one or more loads, and includes one or more clock switching devices that are equal to all the loads in number, all the loads are connected to all the clock switching devices in a one-to-one correspondence, where the clock switching devices are the clock switching devices described in any one of the possible implementations of the second aspect, and a clock signal output port of each clock switching device is connected to a corresponding load to provide a clock signal for the corresponding load.

In a fifth aspect, an embodiment of the present application further provides a clock system, which includes a master clock circuit, a standby clock circuit, and at least one server according to the fourth aspect, where all clock switching devices of all servers are connected to the master clock circuit and the standby clock circuit.

In a possible embodiment, the load of the server comprises at least one processor, or the load of the server comprises at least one processor and one node controller, all processors and the node controllers of the load are connected with the clock switching device corresponding to the load, and all node controllers of all servers of the system are connected with each other.

In a sixth aspect, an embodiment of the present application further provides a clock system, including a first node server, a master clock circuit, and a standby clock circuit, where the first node server includes a first clock switching device and a first processor; the first clock switching means is the clock switching means described in any one of the possible embodiments of the second aspect above. The first clock switching device is respectively connected with the master clock circuit and the standby clock circuit and is used for receiving a master clock signal provided by the master clock circuit and a standby clock signal provided by the standby clock circuit. The first clock switching device is also connected with the first processor and used for providing a clock signal for the first processor.

In a possible implementation, the first node server further includes a second clock switching device and a second processor; the second clock switching means is the clock switching means described in any one of the possible embodiments of the second aspect. The second clock switching device is respectively connected with the master clock circuit and the standby clock circuit and is used for receiving a master clock signal provided by the master clock circuit and a standby clock signal provided by the standby clock circuit. The second clock switching device is also connected with the second processor and used for providing a clock signal for the second processor.

In a possible implementation manner, the first node server further includes a third processor and a first node controller, and the third processor and the first node controller are respectively connected to the first clock switching device and receive the clock signal provided by the first clock switching device. The first node server further comprises a fourth processor and a second node controller, the fourth processor and the second node controller are respectively connected with the second clock switching device, and the first node controller is connected with the second node controller and receives the clock signal provided by the second clock switching device.

In a possible embodiment, the clock system further comprises a second node server, the second node server comprising a third clock switching device and a fifth processor; the third clock switching means is the clock switching means described in any one of the possible embodiments of the second aspect. The third clock switching device is respectively connected with the master clock circuit and the standby clock circuit and is used for receiving a master clock signal provided by the master clock circuit and a standby clock signal provided by the standby clock circuit. The third clock switching device is further connected with the fifth processor and is used for providing a clock signal for the fifth processor.

In a possible implementation, the second node server further includes a fourth clock switching device and a sixth processor; the fourth clock switching means is the clock switching means described in any one of the possible embodiments of the second aspect. The fourth clock switching device is respectively connected to the master clock circuit and the standby clock circuit, and is configured to receive a master clock signal provided by the master clock circuit and a standby clock signal provided by the standby clock circuit. The fourth clock switching device is further connected with the sixth processor and is used for providing a clock signal for the sixth processor.

In a possible implementation manner, the second node server further includes a seventh processor and a third node controller, and the seventh processor and the third node controller are respectively connected to the fourth clock switching device. The second node server further comprises an eighth processor and a fourth node controller, the eighth processor and the fourth node controller are respectively connected with the fourth clock switching device, and the first node controller, the second node controller, the third node controller and the fourth node controller are connected.

Drawings

Fig. 1 is a schematic diagram of a clock system according to an embodiment of the present disclosure;

fig. 2 is a schematic flowchart of a clock switching method according to an embodiment of the present application;

FIG. 3 is a timing diagram of clock signals according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a clock switching device according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a clock switching device according to a second embodiment of the present application;

fig. 6 is a schematic flowchart of a clock switching method according to a second embodiment of the present application;

fig. 7 is a schematic structural diagram of a clock switching device according to a third embodiment of the present application.

Detailed Description

The technical solution in the embodiments of the present application is described below with reference to the drawings in the embodiments of the present application.

In order to ensure that the operation of the node server is not affected when a clock source fails, the clock system provided by the embodiment of the application adopts a redundant design of the clock source, uses the main clock circuit and the standby clock circuit as the clock source of the node server, provides clock signals for the node server through the main clock circuit and the standby clock circuit, and receives the clock signal provided by the other clock circuit when the clock signal provided by one clock circuit is abnormal. Referring to fig. 1, fig. 1 is a schematic diagram of an architecture of a clock system according to an embodiment of the present disclosure. As shown in fig. 1, the clock system includes at least a master clock circuit 101, a standby clock circuit 102, and at least one node server 103. When the clock system is normal, the node server 103 is configured to obtain a master clock signal from the master clock circuit 101, and when detecting that the master clock signal provided by the master clock circuit is abnormal, the node server is configured to obtain a standby clock signal from the standby clock circuit 102. At least one node server 103 in the clock system may be a single processor server or a multi-processor server. If the node server 103 is a single processor server, the node server 103 includes a processor 105. If the node server 103 is a multiprocessor server, the node server 103 includes a plurality of processors 105. If the clock system includes at least two node servers 103, all of the node servers 103 are combined into a multiprocessor service system, running an operating system.

The node server carries out phase reconstruction on the switched standby clock signal through the switching circuit according to the phase difference between the standby clock signal and the main clock signal before the abnormity, and the phase of the reconstructed clock signal is consistent with the phase of the main clock signal provided by the main clock circuit before the abnormity. In a specific implementation, as shown in fig. 1, the node server 103 includes a processor 105 and a switching circuit 104 corresponding to the processor 105, the processor 105 is connected to the corresponding switching circuit 104, and the switching circuit 104 is connected to the master clock circuit 101 and the slave clock circuit 102, respectively. When the master clock signal supplied from the master clock circuit 101 is abnormal, the node server 103 switches the clock source by the switching circuit 104, and acquires the backup clock signal from the backup clock circuit 102. After acquiring the standby clock signal, the node server 103 determines a phase difference between the standby clock signal and the main clock signal before the abnormality according to the pre-recorded main clock signal before the abnormality, and performs phase reconstruction on the switched standby clock signal according to the phase difference.

The clock system may include a plurality of processors and at least two switching circuits, for example, the clock system includes a multiprocessor server and at least two switching circuits, wherein at least one processor in the multiprocessor server corresponds to one switching circuit; or the clock system comprises a multiprocessor service system consisting of at least two node servers and at least two switching circuits, wherein at least one processor in each node server corresponds to one switching circuit in the node server. In a clock system including multiple processors, the TSCs of each processor provide a high precision clock signal to the same operating system core. The counting frequency and the phase of the TSCs in each processor are consistent, and the operating system of the node server where the processor is located can normally work.

In the existing clock system comprising a plurality of processors and at least two switching circuits, the processing deviations of different switching circuits when the same clock signal is reconstructed are different, so that the phase deviations exist among the clock signals obtained after the phase reconstruction is performed on the standby clock signals by the different switching circuits, possibly the phase deviations are also different, so that the phases of the clock signals of the TSCs provided for the processors are different, and the normal operation of an operating system of a server is influenced.

In the clock system provided in the embodiment of the present application, for a clock system including a plurality of processors and at least two switching circuits, in order to solve the problem that processing deviations are different when different switching circuits reconstruct the same standby clock signal, which results in inconsistent phases of clock signals of TSCs provided to the processors, the switching circuits reconstruct the standby clock signal, generate a reconstructed clock signal, and then compensate the phase of the reconstructed clock signal according to the standby clock signal and a preset phase adjustment speed, so as to generate a compensated clock signal, because the phase of the compensated clock signal is consistent with the phase of the standby clock signal, the problem that a phase deviation exists between clock signals obtained after the switching circuits perform phase reconstruction on the same standby clock signal is solved.

In a specific implementation of the clock system provided in the embodiment of the present application, referring to fig. 1, the node server 103 may include at least one switching circuit 104 and at least one processor 105. Each switching circuit 104 is connected to one or more processors 105. The switching circuit 104 is connected to the main clock circuit 101 and the standby clock circuit 102, respectively, and is configured to receive the main clock signal provided by the main clock circuit 101 and supply the main clock signal to the processor 105 connected to the switching circuit 104 when the main clock signal provided by the main clock circuit 101 is normal; when the master clock signal supplied from the master clock circuit 101 is abnormal, the master clock signal received from the master clock circuit 101 is switched to the slave clock circuit 102, the phase of the slave clock signal is reconstructed and supplied to the processor 105 connected to the switching circuit 104, and the phase of the reconstructed clock signal is identical to the phase of the clock signal supplied from the master clock circuit.

For example, in the clock system shown in fig. 1, the master and standby clock circuits and the switching circuits may be implemented by cables or synchronous ethernet. The master clock circuit and the standby clock circuit adopt a biplane networking structure, the standby clock circuit realizes the synchronization of the master clock and the standby clock through an interlocking path, and the interlocking path between the master clock circuit and the standby clock circuit can be realized through a cable, a back plate or a synchronous Ethernet mode. If the synchronous Ethernet mode is adopted to realize the connection between the main clock circuit and the standby clock circuit and the switching circuit, the problems of complex wire arrangement, high cost and the like caused by the adoption of a cable connection mode can be solved.

Illustratively, in the clock system shown in fig. 1, the clock source of the master clock circuit 101 is provided by a phase-locked loop of the master clock circuit 101 by a local oscillator free oscillation included in the master clock circuit 101, and the slave clock circuit 102 tracks the frequency of the clock signal provided by the master clock circuit 101 through an interlock path, so that the frequency of the clock signal provided by the slave clock circuit 102 is identical to the frequency of the clock signal provided by the master clock circuit 101. Therefore, no extra high-precision clock source equipment is needed in the clock system to provide clock signals for the main clock circuit and the standby clock circuit, and the local clock oscillation of each clock circuit freely oscillates to provide a clock source for the phase-locked loop of the clock circuit, so that the requirements on communication, computer equipment cost and data center machine room deployment are reduced. And, illustratively, one node server may be one physical node server, such as one server rack cluster. When one node server is a server cabinet, considering that the cost of connecting all processors on the whole cabinet to the same backboard is high, a plurality of processors can be connected to one backboard, and the plurality of backplanes are connected with each other. A node controller and at least one processor are arranged on one backboard. Node Controllers (NC) are used to manage and control processors on one backplane, and Node controllers on different backplanes are interconnected by cables or optical fibers. By interconnecting node controllers on different node servers or different backplanes, remote memory access by the processor may be achieved. In specific implementation, all node controllers are connected through a cross-frame high-speed interconnection bus by cables or optical fibers. Clock signals provided by the switching circuits are in the same source, so that the clock frequencies and phases at two ends of an interconnection bus between the interconnected node controllers are the same, the transmission delay on the interconnection bus is reduced, and the remote memory access performance between different processors is ensured. And, the processor may be, for example, an arithmetic core and a control core (control unit) of a multiprocessor server. One or more processor cores (cores) may be included in a processor. The processor may be an ultra-large scale integrated circuit. It is understood that, in the embodiment of the present application, the Core in the processor may be, for example, a Central Processing Unit (CPU), or may be Another Specific Integrated Circuit (ASIC). Illustratively, as shown in FIG. 1, the switching circuit 104 may distribute the clock signal to different processors 105, node controllers 106, or other devices through fan-out expanders 107. Illustratively, for devices belonging to a cache coherent bus domain, the same switching circuit 104 provides the clock signal through fan-out expander 107.

As shown in fig. 1, the node server 103 includes at least two switching circuits 104, and when the master clock signal provided by the master clock circuit 101 is abnormal, the plurality of switching circuits 104 simultaneously perform clock switching and phase reconstruction of the clock signal. At this time, since there are unavoidable device differences between the switching circuits 104, there is a phase deviation between the clock signals obtained by the switching circuits 104 after performing phase reconstruction on the slave clock signal provided by the slave clock circuit 102, which causes phase inconsistency of the clock signals of the TSCs provided to the processors 105, and affects normal operation of the operating system of the server. Further, when the clock signal provided by the standby clock circuit 102 is abnormal, the switching circuit 104 performs clock switching and phase reconstruction of the clock signal again, and the phase of the clock signal reconstructed by the switching circuit 104 this time is consistent with the phase of the clock signal reconstructed by the previous switching circuit, but phase deviation still exists between different switching circuits during phase reconstruction. Therefore, as the number of clock switching by the switching circuits 104 increases, the phase deviation between the phases of the clock signals of the TSCs provided to the processors 105 by the respective switching circuits 104 becomes larger. For example, the main clock circuit 101 provides a main clock signal clk1, the standby clock circuit 102 provides a standby clock signal clk2, when clk1 is abnormal, the first switching circuit performs phase reconstruction on clk2 according to clk1 to obtain clk2_1, the second switching circuit performs phase reconstruction on clk2 according to clk1 to obtain clk2_2, and a phase deviation Δ 1 exists between clk2_1 and clk2_ 2. When clk2 is abnormal, the switching circuit receives repaired clk1 again, at this time, the first switching circuit performs phase reconstruction on clk1 according to clk2_1 to obtain clk3_1, the second switching circuit performs phase reconstruction on clk1 according to clk2_2 to obtain clk3_2, and phase deviation Δ 1+ Δ 2 exists between clk3_1 and clk3_ 2. When clk1 is abnormal again, the switching circuit receives repaired clk2 again, at this time, the first switching circuit performs phase reconstruction on clk2 according to clk3_1 to obtain clk4_1, the second switching circuit performs phase reconstruction on clk2 according to clk3_2 to obtain clk4_2, and phase deviation Δ 1+ Δ 21+ Δ 3 exists between clk4_1 and clk4_ 2.

In order to solve the above problem, in the clock switching method provided in the embodiments of the present application, the switching circuit 104 reconstructs the standby clock signal, generates the reconstructed clock signal, and performs phase compensation on the reconstructed clock signal, so that the phase of the compensated clock signal is consistent with the phase of the standby clock signal, thereby solving the problem of phase deviation between the clock signals obtained after the switching circuits perform phase reconstruction on the standby clock signal.

The following describes the clock switching method provided in the embodiments of the present application in detail with reference to specific embodiments. An embodiment of the present application provides a clock switching method. Fig. 2 is a schematic flowchart of a clock switching method according to an embodiment of the present disclosure. As shown in fig. 2, the clock switching method provided in this embodiment is applied to the node server 103 in the clock system shown in fig. 1, and the execution subject may be the switching circuit 104. In this embodiment, when the switching circuit 104 switches the clock signal, it first performs phase reconstruction on the standby clock signal provided by the standby clock circuit 102, and then performs phase compensation on the reconstructed clock signal, so that the phase of the adjusted clock signal is consistent with the phase of the standby clock signal provided by the standby clock circuit 102, thereby avoiding phase difference between the reconstructed clock signals possibly caused by device difference between different switching circuits 104. As shown in fig. 2, the clock switching method provided in this embodiment includes:

s201, when the main clock signal is detected to be abnormal, the standby clock signal is received through the standby clock signal input port of the switching circuit.

The master clock signal is provided by a master clock circuit connected with the switching circuit, and the standby clock signal is provided by a standby clock circuit connected with the switching circuit.

Illustratively, when the master clock signal is normal, the first circuit receives the master clock signal and then provides the master clock signal to the first load, and the master clock signal is provided by a master clock circuit connected with the first circuit. When the main clock signal is abnormal, the first circuit receives the standby clock signal, and the standby clock signal is provided by the standby clock circuit connected with the first circuit. The first circuit may be the switching circuit 104 in fig. 1, and the first load may be one or more processors 105 in fig. 1.

Illustratively, the switching circuit begins clock switching when the switching circuit detects an anomaly in the master clock signal. Illustratively, the master clock signal may be considered to be abnormal when the switching circuit detects or receives a fault of the master clock circuit, a fault of a connection line between the master clock circuit and the switching circuit, a fault of a connection line between the standby clock circuit and the master clock circuit, a frequency difference between the master clock signal and the standby clock signal exceeding a preset range, and the like. Illustratively, when the switching circuit receives a clock switching command, the main clock signal is considered to be abnormal, and the clock switching is started. The switching circuit receives a standby clock signal provided by the standby clock circuit when switching the clock. Illustratively, the switching circuit also stops receiving the master clock signal provided by the master clock circuit and prompts a user to troubleshoot the master clock circuit. In this case, the standby clock circuit is used as a new master clock circuit, and when the master clock circuit returns to normal, the standby clock circuit is used as a new standby clock circuit, and the processing mode of clock switching is not changed.

Illustratively, when the main clock signal provided by the main clock circuit is not abnormal and the standby clock signal provided by the standby clock circuit is abnormal, clock switching is not performed, and only a user is reminded to perform fault maintenance, so that the standby clock circuit recovers to work normally again.

S202, reconstructing the phase of the standby clock signal and generating a reconstructed clock signal, wherein the phase of the reconstructed clock signal is consistent with the phase of the main clock signal before abnormality.

Illustratively, the first circuit reconstructs a phase of the standby clock signal to generate a first reconstructed clock signal, and the phase of the first reconstructed clock signal is consistent with a phase of the master clock signal before the abnormality; the first circuit provides a first reconstructed clock signal to a first load.

For example, fig. 3 is a timing diagram of clock signals provided in an embodiment of the present application. Fig. 3 shows a phase difference between the standby clock signal provided by the standby clock circuit and the main clock signal provided by the main clock circuit. When the switching circuit stops receiving the main clock signal provided by the main clock circuit and receives the standby clock signal provided by the standby clock circuit, the phase of the clock signal may change greatly. In this embodiment, the switching circuit performs phase reconstruction on the received standby clock signal to generate a reconstructed clock signal, where the phase of the reconstructed clock signal is consistent with the phase of the main clock signal provided by the main clock circuit before the abnormality, so as to avoid instability of the processor caused by a phase difference between the standby clock signal and the main clock signal.

For example, fig. 3 takes an example that a phase of a standby clock signal provided by the standby clock circuit lags a phase of a main clock signal provided by the main clock circuit as an example, and it is understood by those skilled in the art that the phase of the standby clock signal provided by the standby clock circuit may also lead the phase of the main clock signal provided by the main clock circuit, which is not limited in the embodiment of the present application.

Optionally, the process of performing phase reconstruction by the switching circuit may specifically include:

the switching circuit reconstructs the phase of the standby clock signal according to the phase difference, and generates a reconstructed clock signal, wherein the phase difference is the phase difference between the standby clock signal and the main clock signal before the abnormality.

For example, when performing phase reconstruction, the switching circuit may reconstruct a phase of the standby clock signal according to a phase difference between the main clock signal before the abnormality and the standby clock signal received by the switching circuit after the abnormality, where the phase of the reconstructed clock signal depends on the phase of the standby clock signal and the phase difference. For example, when performing phase reconstruction, a phase difference is first obtained and stored according to a master clock signal before an abnormality and a standby clock signal received by a switching circuit after the abnormality. Since different switching circuits may not be completely consistent, there may be a deviation in the calculation process of the phase difference between the switching circuits, and meanwhile, in the process of phase reconstruction according to the phase difference, the reconstruction circuits may not be completely consistent, and the phase deviation may be further enlarged.

And S203, compensating the phase of the reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed, generating a compensated clock signal, outputting the compensated clock signal through a clock signal output port of the switching circuit, wherein the phase of the compensated clock signal is consistent with the phase of the standby clock signal.

Illustratively, the first circuit generates a plurality of adjusted clock signals by continuously adjusting the phase of the first reconstructed clock signal according to the standby clock signal and a preset phase adjustment speed, wherein the phase of the last generated adjusted clock signal in the plurality of adjusted clock signals is equal to the phase of the standby clock signal, and the phases of other adjusted clock signals in the plurality of adjusted clock signals are between the phase of the first reconstructed clock signal and the phase of the standby clock signal except for the last generated adjusted clock signal; the first circuit provides the adjusted clock signal generated after adjustment to the first load after each adjustment.

For example, in consideration that there is a phase deviation between phases of reconstructed clock signals obtained after the phases are reconstructed by different switching circuits, and the phase deviation may be accumulated along with the increase of the switching times, in this embodiment, the phases of the reconstructed clock signals are subjected to phase compensation to generate compensated clock signals that are consistent with the phase of the standby clock signal, and since the phases of the compensated clock signals generated by the different switching circuits are all consistent with the phase of the standby clock signal provided by the standby clock circuit, it is ensured that the phases of the clock signals provided by the switching circuits for the TSCs of the processors are consistent. Meanwhile, when the switching circuit performs switching a plurality of times, the switching circuit generates a clock signal that matches the standby clock signal supplied from the standby clock circuit every time the clock is switched, and therefore even if the clock is switched a plurality of times, there is no case where the skew is accumulated. For example, the main clock circuit provides a main clock signal clk1, the standby clock circuit provides a standby clock signal clk2, when clk1 is abnormal, the first switching circuit performs phase reconstruction and compensation on clk2 according to clk1 to obtain clk2, the second switching circuit performs phase reconstruction and compensation on clk2 according to clk1 to obtain clk2, and there is no phase deviation between the clock signals provided by the two switching circuits after clock switching. When clk2 is abnormal, the switching circuit receives the repaired clk1 again, at this time, the first switching circuit performs phase reconstruction and compensation on clk1 according to clk2 to obtain clk1, the second switching circuit performs phase reconstruction and compensation on clk1 according to clk2 to obtain clk1, and the two switching circuits do not have phase deviation between clock signals provided after clock switching. For example, as shown in fig. 3, the switching circuit adjusts the reconstructed clock signal into the standby clock signal according to the standby clock circuit and the preset phase adjustment speed, and on the premise that the phase of the clock signal is not changed suddenly, it is also ensured that the phase change of the clock signal output by each switching circuit is consistent in the clock switching stage. Optionally, the value range of the preset phase adjustment speed is 1-10 microseconds/second.

The clock switching method provided by the embodiment of the application is applied to a server comprising a switching circuit, when the switching circuit detects that a main clock signal is abnormal, the switching circuit receives a standby clock signal through a standby clock signal input port of the switching circuit, reconstructs the phase of the standby clock signal and generates a reconstructed clock signal, and the phase of the reconstructed clock signal is consistent with the phase of the main clock signal before the abnormality; compensating the phase of the reconstructed clock signal according to the standby clock signal and the preset phase adjusting speed, generating a compensated clock signal, outputting the compensated clock signal through a clock signal output port of the switching circuit, wherein the phase of the compensated clock signal is consistent with the phase of the standby clock signal. The phase compensation is carried out on the phase of the reconstructed clock signal according to the preset phase adjustment speed, so that the clock signal with the phase consistent with the phase of the standby clock signal is generated, the slow change and the consistent change of the phases of the clock signals compensated by the plurality of switching circuits are ensured, the phases of the clock signals provided by the TSCs of the processors by the switching circuits are consistent, the unstable operation of a multiprocessor operating system is avoided, and the accumulated error possibly caused by the clock switching for many times is also avoided.

Illustratively, on the basis of the embodiment shown in fig. 2, the embodiment of the present application further provides a clock switching method. The method is applied to a clock system as shown in fig. 1, the clock system includes a first node server, the first node server includes a first switching circuit and a second switching circuit, and a load connected to each switching circuit, and the load includes at least one processor. The first switching circuit is configured to execute the clock switching method shown in fig. 2, and the clock switching method executed by the second switching circuit includes:

s11, when the master clock signal is normal, the second circuit receives the master clock signal and then provides the master clock signal to the second load, and the master clock signal is provided by the master clock circuit connected with the second circuit;

s12, when the main clock signal is abnormal, the second circuit receives the standby clock signal, and the standby clock signal is provided by the standby clock circuit connected with the second circuit;

s13, the second circuit reconstructs the phase of the standby clock signal to generate a second reconstructed clock signal, and the phase of the second reconstructed clock signal is consistent with the phase of the main clock signal before abnormality;

s14, the second circuit provides a second reconstructed clock signal for the second load;

s15, the second circuit continuously adjusts the phase of the second reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of compensation clock signals, the phase of the last generated compensation clock signal in the plurality of compensation clock signals is equal to the phase of the standby clock signal, and except the last generated compensation clock signal, the phases of other compensation clock signals in the plurality of compensation clock signals are between the phase of the second reconstructed clock signal and the phase of the standby clock signal;

and S16, providing the compensation clock signal generated after adjustment to the second load after each adjustment by the second circuit.

The second circuit may be exemplarily the second switching circuit in fig. 1, and the second load may be exemplarily the second processor and/or the fourth processor in fig. 1.

In the clock switching method provided by the embodiment of the application, the two switching circuits perform phase compensation on the phase of the reconstructed clock signal according to the preset phase adjustment speed to generate the clock signal with the phase consistent with the phase of the standby clock signal, so that the phase consistency of the finally generated adjustment clock signal and the compensation clock signal is ensured, the slow phase change and the consistent phase change of the clock signals compensated by the multiple switching circuits are ensured, the phases of the clock signals provided by the TSCs of the processors by the switching circuits are consistent, the unstable operation of a multiprocessor operating system is avoided, and the accumulated error possibly caused by multiple times of clock switching is also avoided.

Another aspect of the present embodiment provides a clock switching apparatus, configured to perform the clock switching method in the embodiment shown in fig. 2, and have the same or similar technical effects.

The clock switching device comprises a first circuit such as the first switching circuit in fig. 1, wherein the first circuit is respectively connected with a main clock circuit 101, a standby clock circuit 102 and a first load; the first load may exemplarily be the first processor and/or the third processor in fig. 1.

The first circuit is used for providing a main clock signal to the first load after receiving the main clock signal when the main clock signal is normal, and the main clock signal is provided by the main clock circuit;

the first circuit is also used for receiving a standby clock signal when the main clock signal is abnormal, and the standby clock signal is provided by the standby clock circuit;

the first circuit is also used for reconstructing the phase of the standby clock signal to generate a first reconstructed clock signal, and the phase of the first reconstructed clock signal is consistent with the phase of the main clock signal before abnormality;

the first circuit is further configured to provide a first reconstructed clock signal to a first load;

the first circuit is further configured to continuously adjust a phase of the first reconstructed clock signal according to the standby clock signal and a preset phase adjustment speed to generate a plurality of adjustment clock signals, wherein a phase of a last adjustment clock signal generated in the plurality of adjustment clock signals is equal to a phase of the standby clock signal, and except for the last adjustment clock signal generated, phases of other adjustment clock signals in the plurality of adjustment clock signals are between the phase of the first reconstructed clock signal and the phase of the standby clock signal;

the first circuit is further configured to provide an adjusted clock signal generated after adjustment to the first load after each adjustment.

Optionally, the clock switching apparatus further includes a second circuit such as the second switching circuit in fig. 1; the second circuit is connected to the master clock circuit 101, the standby clock circuit 102, and a second load, which may be, for example, a second processor and/or a fourth processor in fig. 1.

The second circuit is used for providing a main clock signal to the second load after receiving the main clock signal when the main clock signal is normal, and the main clock signal is provided by the main clock circuit;

the second circuit is also used for receiving the standby clock signal when the main clock signal is abnormal, and the standby clock signal is provided by the standby clock circuit;

the second circuit is also used for reconstructing the phase of the standby clock signal to generate a second reconstructed clock signal, and the phase of the second reconstructed clock signal is consistent with the phase of the main clock signal before abnormality;

the second circuit is further configured to provide a second reconstructed clock signal to a second load;

the second circuit is further configured to continuously adjust a phase of the second reconstructed clock signal according to the standby clock signal and a preset phase adjustment speed to generate a plurality of compensation clock signals, wherein a phase of a last generated compensation clock signal of the plurality of compensation clock signals is equal to a phase of the standby clock signal, and except for the last generated compensation clock signal, phases of other compensation clock signals of the plurality of compensation clock signals are between the phase of the second reconstructed clock signal and the phase of the standby clock signal;

the second circuit is further configured to provide the adjusted generated compensated clock signal to the second load after each adjustment.

Another aspect of the present embodiment provides a clock switching apparatus, configured to execute the clock switching method in the foregoing embodiment. Fig. 4 is a schematic structural diagram of a clock switching device according to an embodiment of the present application. The clock switching device in the present embodiment may be exemplified by the switching circuit 104 in fig. 1. As shown in fig. 4, the clock switching apparatus 400 includes: a control circuit 401 and a phase-locked loop circuit 402; the control circuit 401 is respectively connected with a main clock signal input port, a standby clock signal input port of the clock switching device and a reference input port of the phase-locked loop circuit 402, and an output port of the phase-locked loop circuit 402 is connected with a clock signal output port of the clock switching device; the control circuit 401 is connected to the phase-locked loop circuit 402; wherein,

when detecting that the master clock signal is abnormal, the control circuit 401 receives the standby clock signal through the standby clock signal input port of the clock switching device 400, and sets the working state of the phase-locked loop circuit 402 to a phase reconstruction state;

when the working state of the phase-locked loop circuit 402 is a phase reconstruction state, reconstructing the phase of the standby clock signal and generating a reconstructed clock signal, wherein the phase of the reconstructed clock signal is consistent with the phase of the master clock signal before the abnormality;

when the phase-locked loop circuit 402 generates the reconstructed clock signal, the control circuit 401 sets the operating state of the phase-locked loop circuit 402 to a phase compensation state;

when the operating state of the phase-locked loop circuit 402 is the phase compensation state, the phase of the reconstructed clock signal is compensated according to the standby clock signal and the preset phase adjustment speed, and a compensated clock signal is generated.

Illustratively, as shown in fig. 4, the clock switching device 400 includes a control circuit 401 and a phase-locked loop circuit 402. The control circuit 401 is connected to the main clock signal input port and the standby clock signal input port of the clock switching device 400, respectively, and receives a main clock signal provided by the main clock circuit and a standby clock signal provided by the standby clock circuit. The control circuit 401 is further connected to a reference input port of the phase-locked loop circuit 402, and is configured to select a clock signal from the main and standby clock signals and send the selected clock signal to the reference input port of the phase-locked loop circuit 402. The exemplary control circuit 401 is further configured to monitor the master clock signal, and when the master clock signal is monitored to be abnormal, the control circuit 401 stops receiving the master clock signal, receives the standby clock signal through the standby clock signal input port of the clock switching device 400, and sends the standby clock signal to the phase-locked loop circuit 402.

For example, when the control circuit 401 monitors that the master clock signal is abnormal and the clock switching is required, the control circuit 401 controls the phase-locked loop circuit 402 to be in different working states in sequence, so that the phase-locked loop circuit 402 respectively performs phase reconstruction and phase compensation on the clock signal. Illustratively, the pll circuit 402 is provided with a register, and the register is used for storing configuration parameters of the pll circuit 402, and different configuration parameters correspond to different operating states of the pll circuit 402. The control circuit 401 may control the phase-locked loop circuit 402 to be in different operating states by modifying configuration parameters in registers of the phase-locked loop circuit 402.

For example, when the control circuit 401 detects that the master clock signal is required to be abnormal, it first controls the phase-locked loop circuit 402 to be in the phase reconstruction operating state.

When the phase-locked loop circuit 402 is in a phase reconstruction operating state, the phase-locked loop circuit 402 receives the standby clock signal through the reference input port, and meanwhile, a feedback path between an oscillator and a phase frequency/phase discriminator arranged inside the phase-locked loop circuit 402 provides a main clock signal before abnormality to the phase-locked loop circuit 402, the phase-locked loop circuit 402 acquires and stores a phase difference between the clock signal and the main clock signal before abnormality, and gradually adjusts the phase of the standby clock signal received by the phase-locked loop circuit 402 according to the stored phase difference, so that the phase of the clock signal output by the output end of the phase-locked loop circuit 402 is consistent with the phase of the main clock signal before abnormality.

Illustratively, the phase-locked loop circuit 402 detects a phase difference between a phase of a clock signal provided by the output port and a phase of a standby clock signal received by the phase-locked loop circuit 402 in real time, and determines whether a difference between the phase difference obtained by the real-time detection and a phase difference stored when the main clock signal is abnormal is within a preset range, and if so, confirms that the phase reconstruction is finished.

At this time, the control circuit 401 reconfigures the configuration parameters of the phase-locked loop circuit 402, and controls the phase-locked loop circuit 402 to operate in the phase compensation state. When the operating state of the pll circuit 402 is the phase compensation state, the pll circuit 402 performs phase compensation on the reconstructed clock signal fed back to the frequency/phase discriminator by the oscillator according to the received standby clock signal, so that the phase of the clock signal output by the oscillator gradually approaches the phase of the standby clock signal until the phase of the clock signal output by the oscillator is the same as the phase of the standby clock signal.

The clock switching device provided by the embodiment comprises a control circuit and a phase-locked loop circuit, wherein the control circuit is used for controlling the working state of the phase-locked loop circuit, the phase-locked loop circuit is used for carrying out phase reconstruction on the phase of a standby clock signal according to a main clock signal and the standby clock signal before abnormality when the working state is a phase reconstruction state to obtain the reconstructed clock signal, so that the sudden change of the phase of the clock signal during clock switching is avoided, after the phase reconstruction is finished, the working state of the phase-locked loop circuit is changed into a phase compensation state, the phase of the reconstructed clock signal is gradually changed into be consistent with the standby clock signal by the phase-locked loop circuit, so that the phases of the clock signals provided by the TSCs of the processors by the switching circuits are consistent, the clock switching device realizes the phase reconstruction and the phase compensation of the clock signal by one phase-locked loop circuit in a mode of adopting the control circuit to control the phase-locked loop circuit to work in different working states, the switching circuit has a simple structure.

Exemplarily, on the basis of the embodiment shown in fig. 4, the embodiment of the present application further provides a clock switching device. Fig. 5 is a schematic structural diagram of a clock switching device according to a second embodiment of the present application. As shown in fig. 5, in the clock switching device provided in this embodiment, the clock signal output port of the clock switching device is further connected to the feedback clock signal input port of the clock switching device, and the feedback clock signal input port of the clock switching device is connected to the feedback input port of the phase-locked loop circuit, so as to form a zero-delay feedback path of the clock switching device. Correspondingly, with reference to the embodiment shown in fig. 5, on the basis of the embodiment shown in fig. 2, the embodiment of the present application further provides a clock switching method, in which a clock switching device receives a feedback clock signal output by a clock signal output port, and performs phase compensation on a reconstructed clock signal according to the feedback clock signal, so that the phases of the clock signal output by the clock signal output port of the clock switching device and a standby clock signal are completely consistent. Fig. 6 is a flowchart illustrating a clock switching method according to a second embodiment of the present application. As shown in fig. 6, the clock switching method includes:

s601, when detecting that the main clock signal is abnormal, the control circuit receives a standby clock signal through a standby clock signal input port of the clock switching device; the phase-locked loop circuit stops receiving the feedback clock signal through the feedback input port of the phase-locked loop circuit, and the feedback clock signal is the clock signal input by the feedback clock signal input port of the clock switching device.

Illustratively, the control circuit disconnects the zero-delay feedback path upon detecting an anomaly in the master clock signal. Specifically, the control circuit sets the operating state of the phase-locked loop circuit, so that the phase-locked loop circuit stops receiving the feedback clock signal through the feedback input port of the phase-locked loop circuit, that is, stops receiving the clock signal output by the clock signal output port of the clock switching device. Illustratively, a register is arranged in the phase-locked loop circuit, and the information stored in the register is an enable signal of whether the phase-locked loop circuit opens the zero-delay feedback path. When the control circuit controls the conduction of the zero-delay feedback path, the control circuit writes a first numerical value into the register, and when the phase-locked loop circuit reads that the numerical value read by the register is the first numerical value, the conduction of the zero-delay feedback path is enabled. When the control circuit controls the zero-delay feedback path to be disconnected, the control circuit writes a second numerical value into the register, and when the phase-locked loop circuit reads that the numerical value read in the register is the second numerical value, the zero-delay feedback path cannot be enabled to be connected, namely the zero-delay feedback path is disconnected.

S602, the phase of the standby clock signal is reconstructed by the phase-locked loop circuit, a reconstructed clock signal is generated, and the phase of the reconstructed clock signal is consistent with the phase of the main clock signal before abnormality.

For example, S602 in this embodiment is the same as S202 in the embodiment shown in fig. 2, and details thereof are not repeated herein.

S603, the pll circuit stops receiving the clock signal provided by the oscillator of the pll circuit, and receives the feedback clock signal through the feedback input port of the pll circuit.

For example, in an actual clock switching apparatus, a deletion expander, a buffer, and the like may exist between the output terminal of the phase-locked loop circuit and the clock signal output port of the clock switching apparatus, so that the phase of the clock signal output from the clock signal output port of the clock switching apparatus is not consistent with the phase of the clock signal output from the output terminal of the phase-locked loop circuit. Although the phase-locked loop circuits of the clock switching devices can control the clock signals at the output ends of the phase-locked loop circuits to be consistent with the standby clock signals after performing phase compensation, since the devices between the output ends of the phase-locked loop circuits and the clock signal output ports of the clock switching devices are not completely the same, phase inconsistency may exist between the clock signals output by the clock signal output ports of different clock switching devices. Therefore, after the phase-locked loop circuit generates the reconstructed clock signal, the phase-locked loop circuit disconnects a feedback path inside the phase-locked loop circuit, and performs phase compensation on the phase of the reconstructed clock signal output by the clock signal output port of the clock switching device according to the zero-delay feedback path, so that the phase of the clock signal output by the clock signal output port of the clock switching device is consistent with the phase of the standby clock signal, thereby ensuring that the clock signals output by the clock signal output ports of the clock switching devices are consistent with the standby clock signal at different times and no phase inconsistency exists between the clock signals.

S604, the phase-locked loop circuit compensates the phase of the reconstructed clock signal according to the standby clock signal, the feedback clock signal and the preset phase adjustment speed, generates a compensated clock signal, outputs the compensated clock signal through a clock signal output port of the clock switching device, and the phase of the compensated clock signal is consistent with the phase of the standby clock signal.

Illustratively, the phase-locked loop circuit compensates the phase of the reconstructed clock signal output by the clock signal output port of the clock switching device according to the standby clock signal, the feedback clock signal output by the clock signal output port of the clock switching device, and the preset phase adjustment speed, and generates a compensated clock signal having a phase consistent with the phase of the standby clock signal.

Illustratively, when the control circuit detects an abnormality in the standby clock signal, the control circuit receives the master clock signal from the repaired master clock circuit and disconnects the zero-delay feedback path. Illustratively, the control circuit further controls the phase-locked loop circuit to start receiving a clock signal provided by an oscillator of the phase-locked loop circuit to perform phase reconstruction again.

According to the clock switching method provided by the embodiment of the application, in the phase compensation process, the phase of the reconstructed clock signal is compensated according to the standby clock signal and the feedback clock signal output by the clock signal output port of the clock switching device, and the compensated clock signal is generated, so that the phase of the compensated clock signal is consistent with that of the standby clock signal, and therefore the phases of the clock signals provided by all the clock switching devices to the processor are completely consistent.

Optionally, on the basis of any of the above-described embodiments, the frequency of the first clock signal provided by the standby clock circuit may be determined according to an average value of the frequencies of the clock signals provided by the master clock circuit within a preset time period.

For example, as shown in fig. 1, the standby clock circuit monitors the frequency of the clock signal provided by the main clock circuit through the interlock path, and obtains the average value of the frequency of the clock signal provided by the main clock circuit in the preset time period as the frequency of the standby clock signal, with the preset time period as a cycle. By adopting the two clock circuits to supply power for the processors of the processors in the multiprocessor server system, the stability of the clock source is improved, the situation that a single stable accurate clock source is adopted to simultaneously provide clock signals for each processor through the main clock circuit and the standby clock circuit is avoided, and the clock cost of the clock system is reduced.

Optionally, on the basis of any of the above embodiments, the exemplary case where the switching circuit detects an abnormality of the master clock signal may be any of the following: the switching circuit receives fault indication information of a main clock circuit sent by a standby clock circuit; or, the switching circuit detects the interruption of the main clock signal; alternatively, the switching circuit receives a clock switching instruction.

For example, when the main clock circuit fails or a connection line between the main clock circuit and the switching circuit fails, the switching circuit may detect that the main clock signal sent by the main clock circuit is interrupted, and at this time, the switching circuit considers that the main clock signal is abnormal and needs to perform clock switching.

Optionally, when the standby clock circuit detects that the clock signal on the interlock path is lost or detects that the frequency offset exceeds the preset threshold, the standby clock circuit sends the main clock circuit fault indication information to the switching circuit.

For example, the standby clock circuit monitors a clock signal provided by the main clock circuit through the interlock path, and when the standby clock circuit monitors that no clock signal exists on the interlock path, the standby clock circuit determines that the main clock circuit fails, or when the standby clock circuit monitors that a frequency deviation between a frequency of the clock signal provided by the main clock circuit and a frequency of the clock signal provided by the standby clock circuit is greater than a preset threshold, the standby clock circuit also determines that the main clock circuit fails, and at this time, the standby clock circuit sends main clock circuit failure indication information to the switching circuit.

For example, the clock switching method provided by the embodiments of the present application is also applicable to other distributed structures that need to guarantee simultaneous clock sources. For example, in a multiprocessor server composed of a plurality of ARM processors, the clock source between different ARM processors needs to be kept consistent. For another example, in a network memory system composed of a plurality of memory cells, the clock source between the memory cells needs to be consistent. Illustratively, the clock switching method provided in each embodiment of the present application can avoid the problems of large-amplitude transient of the clock signal phase, phase discontinuity, and the like in the clock switching process, and thus is also suitable for any device that needs a stable clock source and has a high requirement on the clock phase accuracy, such as a computer, a server, a router, a base station, and other network devices.

Another aspect of the embodiments of the present application further provides a clock switching apparatus, configured to implement the clock switching method in any of the above embodiments, having the same technical effects, which is not described herein again.

The embodiment of the application provides a clock switching device. Fig. 7 is a schematic structural diagram of a clock switching device according to a third embodiment of the present application. As shown in fig. 7, the clock switching apparatus includes:

a first clock signal obtaining module 701, configured to provide a main clock signal to a first load after receiving the main clock signal when the main clock signal is normal, where the main clock signal is provided by a main clock circuit connected to the first clock signal obtaining module 701;

the first clock signal acquisition module 701 is further configured to receive a standby clock signal when the main clock signal is abnormal, where the standby clock signal is provided by a standby clock circuit connected to the first clock signal acquisition module 701;

a first reconstructing module 702, configured to reconstruct a phase of a standby clock signal to generate a first reconstructed clock signal, where the phase of the first reconstructed clock signal is consistent with a phase of a master clock signal before an anomaly; providing a first reconstructed clock signal to a first load;

a first adjusting module 703, configured to continuously adjust the phase of the first reconstructed clock signal according to the standby clock signal and a preset phase adjustment speed to generate a plurality of adjusted clock signals, where the phase of the adjusted clock signal generated last among the plurality of adjusted clock signals is equal to the phase of the standby clock signal, and except for the adjusted clock signal generated last, the phases of other adjusted clock signals among the plurality of adjusted clock signals are between the phase of the first reconstructed clock signal and the phase of the standby clock signal; each adjustment provides an adjusted clock signal generated after the adjustment to the first load.

Optionally, as shown in fig. 7, the clock switching apparatus further includes:

a second clock signal obtaining module 704, configured to provide a master clock signal to the second load after receiving the master clock signal when the master clock signal is normal, where the master clock signal is provided by a master clock circuit connected to the second clock signal obtaining module 704;

the second clock signal obtaining module 704 is further configured to receive a standby clock signal when the main clock signal is abnormal, where the standby clock signal is provided by a standby clock circuit connected to the second clock signal obtaining module 704;

a second reconstruction modeling block 705, configured to reconstruct a phase of the standby clock signal to generate a second reconstructed clock signal, where the phase of the second reconstructed clock signal is consistent with the phase of the master clock signal before the abnormality; providing a second reconstructed clock signal to a second load;

a second adjusting module 706, configured to continuously adjust a phase of the second reconstructed clock signal according to the standby clock signal and a preset phase adjustment speed to generate a plurality of compensation clock signals, where a phase of a last generated compensation clock signal of the plurality of compensation clock signals is equal to a phase of the standby clock signal, and except for the last generated compensation clock signal, phases of other compensation clock signals of the plurality of compensation clock signals are between the phase of the second reconstructed clock signal and the phase of the standby clock signal; each adjustment provides an adjusted generated compensated clock signal to the second load.

Optionally, as shown in fig. 7, the clock switching apparatus further includes: a first control module 707, configured to set the first rebuilding module 702 to an operating state when the master clock signal is abnormal. The first control module 707 is further configured to set the first adjusting module 703 to an operating state after determining that the first reconstructing module 702 generates the first reconstructed clock signal.

Optionally, the clock switching device provides a clock signal to the first load through a clock signal output port of the clock switching device, the clock signal output port of the clock switching device is connected to a feedback clock signal input port of the clock switching device, and the feedback clock signal input port of the clock switching device is connected to the feedback input port of the first adjusting module 703.

The first control module 707 is further configured to close the feedback input port of the first adjusting module 703 and stop receiving the clock signal output by the clock signal output port of the clock switching apparatus from the feedback input port of the first adjusting module 703 before the first reconstructing module 702 reconstructs the phase of the standby clock signal.

The first control module 707 is further configured to close the adjustment feedback port of the first adjustment module 703, stop receiving the clock signal provided by the first adjustment module 703 from the adjustment feedback port of the first adjustment module 703, and open the feedback input port of the first adjustment module 703 before the first adjustment module 703 continuously adjusts the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjustment clock signals.

The first adjusting module 703 is further configured to continuously adjust the phase of the first reconstructed clock signal according to the standby clock signal, the clock feedback signal received from the feedback input port of the first adjusting module 703, and a preset phase adjustment speed to generate a plurality of adjusted clock signals.

Optionally, the first reconstructing module 702 is further configured to reconstruct a phase of the standby clock signal according to a phase difference, so as to generate a first reconstructed clock signal, where the phase difference is a phase difference between the standby clock signal and the master clock signal before the abnormality.

In a possible implementation, the clock switching apparatus further includes:

the second control module is used for setting the second modeling block to be in a working state when the main clock signal is abnormal;

the second control module is further configured to set the second adjusting module to a working state after determining that the second reconstruction clock signal is generated by the second reconstruction module. The communication modes of the second control module, the second adjusting module and the second reconstructing module are the same as the communication modes of the first control module, the first adjusting module and the first reconstructing module, and the communication modes of the second control module, the second adjusting module and the second reconstructing module can refer to the communication modes of the first control module, the first adjusting module and the first reconstructing module, and details are not repeated here.

Another aspect of the embodiments of the present application provides a server. The server comprises one or more loads and one or more clock switching devices with the same number as that of all the loads, wherein all the loads are connected with all the clock switching devices in a one-to-one correspondence mode, the clock switching devices are the clock switching devices in any one of the embodiments, and the clock signal output ports of the clock switching devices are connected with the corresponding loads to provide clock signals for the corresponding loads.

Illustratively, the server may be the node server 103 in fig. 1, the load in the server may be the processor 105 in fig. 1, and the clock switching device may be the switching circuit 104 in fig. 1.

Optionally, another aspect of the embodiments of the present application further provides a clock system, as shown in fig. 1, including a master clock circuit 101, a standby clock circuit 102, and at least one server as in the above embodiments, where all clock switching devices of all servers are connected to the master clock circuit 101 and the standby clock circuit 102. The server may be, for example, the node server 103 in fig. 1.

Alternatively, as shown in fig. 1, the load of the server includes at least one processor 105, or the load of the server includes at least one processor 105 and one node controller 106, all the processors 105 and node controllers 106 of the load are connected to the clock switching device corresponding to the load, and all the node controllers 106 of all the servers of the system are connected to each other.

In another aspect, an embodiment of the present invention further provides a clock system, as shown in fig. 1, including a first node server, a master clock circuit 101, and a standby clock circuit 102, where the first node server includes a first clock switching device and a first processor; the first clock switching device is the clock switching device in any one of the above possible embodiments. The first clock switching device is respectively connected with the main clock circuit and the standby clock circuit and used for receiving a main clock signal provided by the main clock circuit and a standby clock signal provided by the standby clock circuit. The first clock switching device is also connected with the first processor and used for providing a clock signal for the first processor.

Optionally, the first node server further includes a second clock switching device and a second processor; the second clock switching device is the clock switching device in any one of the above possible embodiments. The second clock switching device is respectively connected with the main clock circuit and the standby clock circuit and used for receiving a main clock signal provided by the main clock circuit and a standby clock signal provided by the standby clock circuit. The second clock switching device is also connected with the second processor and used for providing a clock signal for the second processor.

Optionally, the first node server further includes a third processor and a first node controller, where the third processor and the first node controller are respectively connected to the first clock switching device, and receive the clock signal provided by the first clock switching device. The first node server further comprises a fourth processor and a second node controller, the fourth processor and the second node controller are respectively connected with the second clock switching device, and the first node controller is connected with the second node controller and receives the clock signal provided by the second clock switching device.

Optionally, the clock system further includes a second node server, where the second node server includes a third clock switching device and a fifth processor; the third clock switching device is the clock switching device in any one of the possible embodiments described above. The third clock switching device is respectively connected with the main clock circuit and the standby clock circuit and used for receiving a main clock signal provided by the main clock circuit and a standby clock signal provided by the standby clock circuit. The third clock switching device is also connected with the fifth processor and is used for providing a clock signal for the fifth processor.

Optionally, the second node server further includes a fourth clock switching device and a sixth processor; the fourth clock switching means is the clock switching means in any one of the possible embodiments described above. The fourth clock switching device is respectively connected with the main clock circuit and the standby clock circuit and used for receiving a main clock signal provided by the main clock circuit and a standby clock signal provided by the standby clock circuit. The fourth clock switching means is further connected to the sixth processor for providing the clock signal to the sixth processor. Optionally, the second node server further includes a seventh processor and a third node controller, and the seventh processor and the third node controller are respectively connected to the fourth clock switching device. The second node server also comprises an eighth processor and a fourth node controller, the eighth processor and the fourth node controller are respectively connected with the fourth clock switching device, and the first node controller, the second node controller, the third node controller and the fourth node controller are connected.

It should be noted that the examples provided in this application are only illustrative. It will be clear to those skilled in the art that, for convenience and brevity of description, the description of each embodiment has been given with emphasis on the description of the embodiments, and some parts not described in detail in a certain embodiment may be referred to the related description of other embodiments. The features disclosed in the embodiments and figures of the present application may exist independently or in combination. Features described in the embodiments of the present application in hardware may be implemented by software and vice versa. And are not limited herein.

Those of ordinary skill in the art will appreciate that the various illustrative method steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a variety of non-transitory (non-transitory) machine-readable medium that can store program code, such as magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., compact disks), or semiconductor media (e.g., solid-state drives (SSDs)).

In addition, it should be noted that the division of the modules of the above master clock circuit, standby clock circuit and clock synchronization switching circuit is only a division of logic functions, and there may be other division ways in actual implementation, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, in the present application, each functional unit may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit. It should be noted that the examples provided in this application are only illustrative. It will be clear to those skilled in the art that, for convenience and brevity of description, the description of each embodiment has been given with emphasis on the description of the embodiments, and some parts not described in detail in a certain embodiment may be referred to the related description of other embodiments. The features disclosed in the embodiments and figures of the present application may exist independently or in combination. Features described in the embodiments of the present application in hardware may be implemented by software and vice versa. And are not limited herein.

Claims

1. A clock switching method, the method comprising:

when a main clock signal is normal, a first circuit receives the main clock signal and then provides the main clock signal to a first load, wherein the main clock signal is provided by a main clock circuit connected with the first circuit;

when the main clock signal is abnormal, the first circuit receives a standby clock signal, and the standby clock signal is provided by a standby clock circuit connected with the first circuit;

the first circuit reconstructs the phase of the standby clock signal to generate a first reconstructed clock signal, and the phase of the first reconstructed clock signal is consistent with the phase of the main clock signal before abnormality;

the first circuit provides the first reconstructed clock signal to the first load;

the first circuit continuously adjusts the phase of the first reestablished clock signal according to the standby clock signal and a preset phase adjustment speed to generate a plurality of adjustment clock signals, the phase of the adjustment clock signal generated last in the plurality of adjustment clock signals is equal to the phase of the standby clock signal, and except for the adjustment clock signal generated last, the phases of other adjustment clock signals in the plurality of adjustment clock signals are between the phase of the first reestablished clock signal and the phase of the standby clock signal;

the first circuit provides the adjusted clock signal generated after adjustment to the first load after each adjustment.

2. The method of claim 1, further comprising:

when a master clock signal is normal, a second circuit receives the master clock signal and then provides the master clock signal for a second load, wherein the master clock signal is provided by the master clock circuit connected with the second circuit;

when the main clock signal is abnormal, the second circuit receives a standby clock signal, and the standby clock signal is provided by the standby clock circuit connected with the second circuit;

the second circuit reconstructs the phase of the standby clock signal to generate a second reconstructed clock signal, and the phase of the second reconstructed clock signal is consistent with the phase of the main clock signal before abnormality;

the second circuit provides the second reconstructed clock signal to the second load;

the second circuit continuously adjusts the phase of the second reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of compensation clock signals, the phase of the last generated compensation clock signal in the plurality of compensation clock signals is equal to the phase of the standby clock signal, and except the last generated compensation clock signal, the phases of other compensation clock signals in the plurality of compensation clock signals are between the phase of the second reconstructed clock signal and the phase of the standby clock signal;

the second circuit provides the compensation clock signal generated after adjustment to the second load after each adjustment.

3. The method of claim 1 or 2, wherein the first circuit comprises a first control circuit and a first phase-locked loop circuit, the first control circuit being connected to the first phase-locked loop circuit;

the method further comprises the following steps: when the main clock signal is abnormal, the first control circuit sets the working state of the first phase-locked loop circuit to be a phase reconstruction state;

the first circuit reconstructs a phase of the standby clock signal to generate a first reconstructed clock signal, and includes:

when the working state of the first phase-locked loop circuit is a phase reconstruction state, reconstructing the phase of the standby clock signal to generate a first reconstruction clock signal;

the method further comprises the following steps: the first control circuit determines that the first phase-locked loop circuit generates the first reestablished clock signal, and sets the working state of the first phase-locked loop circuit to be a phase compensation state;

the first circuit continuously adjusts the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjusted clock signals, and the method comprises the following steps:

and when the working state of the first phase-locked loop circuit is a phase compensation state, continuously adjusting the phase of the first reestablished clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjustment clock signals.

4. The method of claim 3, wherein the first circuit provides a clock signal to the first load through a clock signal output port of the first circuit, wherein the clock signal output port of the first circuit is connected to a feedback clock signal input port of the first circuit, and wherein the feedback clock signal input port of the first circuit is connected to a feedback input port of the first phase-locked loop circuit;

the method further comprises the following steps: before the first phase-locked loop circuit reconstructs the phase of the standby clock signal, closing a feedback input port of the first phase-locked loop circuit, and stopping receiving the clock signal output by a clock signal output port of the first circuit from the feedback input port of the first phase-locked loop circuit;

the method further comprises the following steps:

before the first phase-locked loop circuit continuously adjusts the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjusted clock signals, closing an oscillator feedback port of the first phase-locked loop circuit, stopping receiving the clock signal provided by the oscillator from the oscillator feedback port of the first phase-locked loop circuit, and opening a feedback input port of the first phase-locked loop circuit;

when the working state of the first phase-locked loop circuit is a phase compensation state, continuously adjusting the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjusted clock signals, including:

and when the working state of the first phase-locked loop circuit is a phase compensation state, continuously adjusting the phase of the first reestablished clock signal according to the standby clock signal, the clock feedback signal received from the feedback input port of the phase-locked loop circuit and the preset phase adjustment speed to generate a plurality of adjusted clock signals.

5. The method of claim 3, wherein the first phase-locked loop circuit reconstructs the phase of the standby clock signal to generate a first reconstructed clock signal when the operating state is a phase reconstruction state, and comprises:

and when the working state of the first phase-locked loop circuit is a phase reconstruction state, reconstructing the phase of the standby clock signal according to the phase difference to generate a first reconstruction clock signal, wherein the phase difference is the phase difference between the standby clock signal and the main clock signal before abnormality.

6. A method according to claim 1 or 2, wherein the frequency of the standby clock signal is determined from an average of the frequencies of the master clock signals provided by the master clock circuit over a predetermined period of time.

7. A clock switching device is characterized by comprising a first circuit, a second circuit and a third circuit, wherein the first circuit is respectively connected with a main clock circuit, a standby clock circuit and a first load;

the first circuit is further configured to receive a standby clock signal when the master clock signal is abnormal, the standby clock signal being provided by the standby clock circuit;

the first circuit is further configured to reconstruct a phase of the standby clock signal to generate a first reconstructed clock signal, where the phase of the first reconstructed clock signal is consistent with a phase of the master clock signal before the abnormality;

the first circuit is further configured to provide the first reconstructed clock signal to the first load;

8. The apparatus of claim 7, further comprising: a second circuit; the second circuit is respectively connected with the main clock circuit, the standby clock circuit and a second load;

9. The apparatus of claim 7 or 8, wherein the first circuit comprises a first control circuit and a first phase-locked loop circuit, the first control circuit being connected to the first phase-locked loop circuit;

10. The apparatus of claim 9, wherein the first circuit provides a clock signal to the first load through a clock signal output port of the first circuit, wherein the clock signal output port of the first circuit is connected to a feedback clock signal input port of the first circuit, and wherein the feedback clock signal input port of the first circuit is connected to a feedback input port of the first phase-locked loop circuit;

11. The apparatus of claim 9, wherein the first phase-locked loop circuit is specifically configured to, when the operating state is a phase reconstruction state, reconstruct a phase of the standby clock signal according to a phase difference between the standby clock signal and the master clock signal before the abnormality to generate a first reconstructed clock signal.

12. The apparatus of claim 7 or 8, wherein the frequency of the standby clock signal is determined according to an average value of the frequencies of the master clock signals provided by the master clock circuit in a preset time period.

13. A server, comprising one or more loads, and comprising one or more clock switching devices having the same number as that of all the loads, all the loads being connected to all the clock switching devices in a one-to-one correspondence, the clock switching devices being as claimed in any one of claims 7 to 12, a clock signal output port of the clock switching device being connected to the corresponding load to provide a clock signal to the corresponding load.

14. A clock system comprising a master clock circuit, a standby clock circuit and at least one server as claimed in claim 13, all clock switching means of all servers being connected to said master clock circuit and said standby clock circuit.

15. The system according to claim 14, wherein the load of the server comprises at least one processor, or the load of the server comprises at least one processor and one node controller, all processors and the node controllers of the load are connected to the clock switching device corresponding to the load, and all node controllers of all servers of the system are connected to each other.