CN115021857B

CN115021857B - Clock synchronization method and device, electronic equipment and storage medium

Info

Publication number: CN115021857B
Application number: CN202210944155.5A
Authority: CN
Inventors: 孔庆宇; 林湖; 黄歆; 徐康
Original assignee: China Automotive Innovation Corp
Current assignee: China Automotive Innovation Corp
Priority date: 2022-08-08
Filing date: 2022-08-08
Publication date: 2022-12-16
Anticipated expiration: 2042-08-08
Also published as: CN115021857A

Abstract

The embodiment of the disclosure provides a clock synchronization method, a clock synchronization device, an electronic device and a storage medium, wherein the method comprises the following steps: receiving and analyzing clock synchronization data sent by a programmable logic module to obtain a first clock signal and a second clock signal; the first clock signal and the second clock signal are used for providing references for standby to the plurality of clock application units for mutually synchronizing the clocks of the plurality of clock application units; obtaining difference information according to the second clock signal and the first clock signal; if the difference information meets the preset condition, sending a first deviation rectifying instruction to the FPGA module; the first deviation rectifying instruction is used for indicating the FPGA module to adjust the second clock signal to obtain a first deviation rectifying signal. Through the clock synchronization method of the embodiment of the disclosure, the calibration efficiency of the clock signal can be improved, and the reliability of the clock source is ensured.

Description

Clock synchronization method and device, electronic equipment and storage medium

Technical Field

The present invention relates to the field of signal processing, and in particular, to a clock synchronization method, apparatus, system, and storage medium.

Background

With the continuous development of the automatic driving technology, the functional complexity of the vehicle-mounted controller is higher and higher, and the existing electronic and electrical architecture of the automobile is gradually converted from discrete to centralized. The existing centralized scheme architecture generally needs to perform clock synchronization processing on video data, millimeter wave radar data, laser radar data, and the like, so that a relatively stable clock source is needed as a reference clock. In order to provide a stable clock source, a 1PPS (pulse per second) signal output by a GPS (Global Positioning System) module may be adopted to transmit in the whole System, and an edge thereof is used as a clock synchronization reference for each module of the System. However, since the central centralized architecture relates to modules or chips of multiple functional domains such as an autopilot domain, an intelligent cabin domain, a chassis control domain, and the like, a 1PPS signal has a scenario of multi-board and multi-chip transmission, and in the scenario, factors such as signal delay, signal loss, and the like in a transmission process may adversely affect clock signal synchronization of a system.

The existing scheme identifies and calibrates the phase difference generated by the 1PPS signal in the transmission process, and although the deviation rectification requirement of the clock signal can be met to a certain degree, the calibration efficiency is low, and the reliability of the clock source is insufficient.

Disclosure of Invention

To overcome the defects in the prior art, embodiments of the present disclosure provide a clock synchronization method, apparatus, system, and storage medium, which can improve the calibration efficiency of clock signals and ensure the reliability of clock sources.

The embodiment of the application provides a clock synchronization method, which comprises the following steps: receiving and analyzing clock synchronization data sent by a programmable logic module to obtain a first clock signal and a second clock signal; the first clock signal and the second clock signal are used for providing references for standby to the plurality of clock application units for mutually synchronizing the clocks of the plurality of clock application units; obtaining difference information according to the second clock signal and the first clock signal; if the difference information meets the preset condition, sending a first deviation rectifying instruction to the programmable logic module; the first deviation rectifying instruction is used for indicating the programmable logic module to adjust the second clock signal to obtain a first deviation rectifying signal.

Optionally, the second clock signal is obtained by shifting the first clock signal back by one cycle by the programmable logic module; the difference information includes a first deviation value that characterizes a deviation between a rising edge of the second period of the first clock signal and a rising edge of the first period of the second clock signal; if the difference information meets the preset condition, a first deviation rectifying instruction is sent to the programmable logic module, and the method comprises the following steps: if the first deviation value meets a first preset deviation condition, sending a first deviation rectifying instruction to the programmable logic module; the first deviation rectifying instruction comprises a first deviation value.

Optionally, if the difference information meets the preset condition, after sending the first deviation rectifying instruction to the programmable logic module, the method further includes: receiving a first deviation rectifying signal sent by a programmable logic module; determining a target clock signal according to the first clock signal or the first deviation correcting signal; and sending the target clock signal to the clock application module.

Optionally, determining the target clock signal according to the first clock signal or the first deviation rectifying signal includes: determining a reference clock signal according to the first clock signal or the first deviation correcting signal; if the first deviation correcting signal is detected to have a missing period, determining a supplementary clock signal from the reference clock signal; the complementary clock signal is used for complementing the information on the missing period; sending a signal supplement instruction to the programmable logic module; the signal supplement instruction comprises a supplement clock signal and is used for instructing the programmable logic module to supplement the first deviation correction signal according to the supplement clock signal to obtain a target supplement signal; receiving a target supplementary signal sent by a programmable logic module; a target clock signal is determined based on the first clock signal or the target supplemental signal.

Optionally, determining the target clock signal according to the first clock signal or the first deviation rectifying signal includes: determining a reference clock signal according to the first clock signal or the first deviation correcting signal; obtaining a second deviation value based on the first deviation correcting signal and the reference clock signal; the second deviation value represents a deviation between a rising edge of a second period of the first deviation correcting signal and a rising edge of the first period or the second period of the reference clock signal; if the second deviation value meets a second preset deviation condition, a second deviation rectifying instruction is sent to the programmable logic module; the second deviation rectifying instruction comprises a second deviation value and is used for indicating the programmable logic module to adjust the first deviation rectifying signal according to the second deviation value to obtain a second deviation rectifying signal; receiving a second deviation rectifying signal sent by the programmable logic module; and determining a target clock signal according to the first clock signal or the second deviation correcting signal.

Optionally, after determining the target clock signal, the method further includes: and carrying out jitter removal and averaging operation on the target clock signal to obtain an application clock signal. Sending the target clock signal to a clock application module, comprising: sending the application clock signal to the clock application module.

Optionally, the number of the main control modules is multiple; the clock application module is used for receiving a plurality of target clock signals sent by the plurality of main control modules and determining a main clock signal from the plurality of target clock signals according to the clock priority.

Correspondingly, the application also provides a clock synchronization device, which comprises:

the receiving module is used for receiving and analyzing the clock synchronization data sent by the programmable logic module to obtain a first clock signal and a second clock signal; the first clock signal and the second clock signal are used for providing reference for standby to the plurality of clock application units so as to enable the plurality of clock application units to be clock-synchronized;

the determining module is used for obtaining difference information according to the second clock signal and the first clock signal;

the sending module is used for sending a first deviation rectifying instruction to the programmable logic module if the difference information meets the preset condition; the first deviation rectifying instruction is used for indicating the programmable logic module to adjust the second clock signal to obtain a first deviation rectifying signal.

Optionally, the second clock signal is obtained by shifting the first clock signal back by one cycle by the programmable logic module; the difference information includes a first deviation value that characterizes a deviation between a rising edge of the second cycle of the first clock signal and a rising edge of the first cycle of the second clock signal. The sending module is further used for sending a first deviation rectifying instruction to the programmable logic module if the first deviation value meets a first preset deviation condition; the first deviation rectifying instruction comprises a first deviation value.

Optionally, the apparatus further includes an application module, configured to receive a first deviation rectifying signal sent by the programmable logic module; determining a target clock signal according to the first clock signal or the first deviation correcting signal; and sending the target clock signal to the clock application module.

Optionally, the determining module is further configured to determine a reference clock signal according to the first clock signal or the first deviation correcting signal; if the first deviation correcting signal is detected to have a missing period, determining a supplementary clock signal from the reference clock signal; the complementary clock signal is used for complementing the information on the missing period; sending a signal supplement instruction to the programmable logic module; the signal supplementing instruction comprises a supplementing clock signal and is used for indicating the programmable logic module to supplement the first deviation correcting signal according to the supplementing clock signal to obtain a target supplementing signal; receiving a target supplement signal sent by a programmable logic module; a target clock signal is determined based on the first clock signal or the target supplemental signal.

Optionally, the determining module is further configured to determine the reference clock signal according to the first clock signal or the first deviation correcting signal; obtaining a second deviation value based on the first deviation correcting signal and the reference clock signal; the second deviation value represents the deviation between the rising edge of the second period of the first deviation correcting signal and the rising edge of the first period or the second period of the reference clock signal; if the second deviation value meets a second preset deviation condition, a second deviation rectifying instruction is sent to the programmable logic module; the second deviation rectifying instruction comprises a second deviation value and is used for indicating the programmable logic module to adjust the first deviation rectifying signal according to the second deviation value to obtain a second deviation rectifying signal; receiving a second deviation rectifying signal sent by the programmable logic module; and determining a target clock signal according to the first clock signal or the second deviation rectifying signal.

Optionally, the determining module is further configured to perform debounce and mean value operation on the target clock signal after determining the target clock signal, so as to obtain an application clock signal. The sending module may also be configured to send the application clock signal to the clock application module.

Accordingly, an embodiment of the present disclosure provides an electronic device, which includes a processor and a memory, where at least one instruction, at least one program, a code set, or an instruction set is stored in the memory, and the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement the clock synchronization method.

Accordingly, embodiments of the present disclosure provide a computer-readable storage medium having at least one instruction, at least one program, set of codes, or set of instructions stored therein, which is loaded and executed by a processor to implement the clock synchronization method described above.

The embodiment of the application has the following beneficial effects:

by adopting the first clock signal as a reference and carrying out feedback calibration on the second clock signal, the efficiency and the accuracy of clock signal calibration can be improved;

the second clock signal is obtained by shifting the first clock signal backward by one cycle, the first deviation value can be conveniently determined no matter under the condition that the phase of the second clock signal shifts forwards or backwards, and the error generated in the transmission process is eliminated according to the first deviation value, so that the second clock signal is accurately controlled and adjusted, and the second rising edge of the first clock signal received and obtained by the subsequent main control module and the first rising edge of the second clock signal received and analyzed keep synchronous or are controlled within a preset range;

the second clock signal which is shifted backwards by one period is sent in the form of an Ethernet message, so that the time delay of the second clock signal in the Ethernet forwarding, AD sampling and decoding processes can be reduced, and the accuracy of the calibration of the second clock signal is ensured;

through the digital processing of clock signals and the mutual backup of clocks of a plurality of main control modules, the clock source can be ensured to be kept stable in each module and each unit of the whole central computing platform;

by determining the reference clock signal and carrying out real-time verification, leakage detection and defect filling according to the reference clock signal, the efficiency and the accuracy of clock signal verification can be improved;

data interaction is realized through Ethernet, PCIE, CAN bus and the like, and under a central computing architecture, clock synchronization and cross-domain intercommunication of an intelligent driving domain, an intelligent cabin domain and a ground control domain CAN be realized;

the main control unit executes the distribution and scheduling processing of the data to be processed in the plurality of computing units, so that the resource sharing of the computing units in the whole system can be realized, and the computing resources can be reasonably distributed, thereby improving the utilization rate of the computing power of the system;

the first clock signal and the second clock signal are backups of each other, and the target clock signals determined by the plurality of main control modules are backups of each other, so that the reliability of the clock source can be improved.

Drawings

In order to more clearly illustrate the technical solutions and advantages of the embodiments of the present application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic view of an application scenario of a clock synchronization method according to an embodiment of the present application;

fig. 2 is a first flowchart of a clock synchronization method according to an embodiment of the present disclosure;

fig. 3 is a second flowchart of a clock synchronization method according to an embodiment of the present application;

fig. 4 is a third flowchart of a clock synchronization method according to an embodiment of the present disclosure;

fig. 5 is a fourth flowchart illustrating a clock synchronization method according to an embodiment of the present application;

fig. 6a is a schematic structural diagram of a first module of a clock synchronization method according to an embodiment of the present application;

FIG. 6b is a schematic diagram of a first signal waveform of a clock synchronization method according to an embodiment of the present application;

fig. 6c is a schematic structural diagram of a second module of a clock synchronization method according to an embodiment of the present application;

FIG. 7 is a diagram illustrating a second signal waveform of a clock synchronization method according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a third module of a clock synchronization method according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a clock synchronization apparatus according to an embodiment of the present application;

fig. 10 is a block diagram of a hardware structure of a server of a clock synchronization method according to an embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings. It should be apparent that the described embodiment is only one embodiment of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making creative efforts shall fall within the protection scope of the present application.

An "embodiment" as referred to herein relates to a particular feature, structure, or characteristic that may be included in at least one implementation of the present application. In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "top", "bottom", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only used for convenience in describing the present application and simplifying the description, and do not indicate or imply that the devices/systems or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be taken as limiting the present application. The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in other sequences than described or illustrated herein. Furthermore, the terms "comprises," "comprising," and "having"/"is," and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, system/apparatus, article, or apparatus that comprises a list of steps or elements/modules is not necessarily limited to those steps or elements/modules expressly listed, but may include other steps or elements/modules not expressly listed or inherent to such process, method, article, or apparatus.

An exemplary scenario of a clock synchronization method provided by the present application is described below.

In an optional implementation manner, an application scenario of the present application may include at least one of a main control module, a clock application module, a programmable logic module, and a GPS module. Optionally, the Programmable logic module may include an FPGA (Field Programmable Gate Array) module; optionally, the Programmable Logic module may further include other Programmable Logic modules such as a CPLD (Complex Programmable Logic Device), which is not limited in this application, and in other optional embodiments, the Programmable Logic module may further include other modules with Programmable Logic capability. Optionally, the clock application module may include a force calculation module, and the main control module may receive and analyze the clock synchronization data sent by the FPGA module to obtain a first clock signal and a second clock signal; the first clock signal and the second clock signal are used for providing reference for the plurality of force calculation modules for standby mutually so as to enable the plurality of clock application units to be in clock synchronization; obtaining difference information according to the second clock signal and the first clock signal; if the difference information meets the preset condition, sending a first deviation rectifying instruction to the FPGA module; the first deviation rectifying instruction is used for indicating the FPGA module to adjust the second clock signal to obtain a first deviation rectifying signal. The FPGA can determine a first clock signal and a second clock signal based on the clock signal sent by the GPS module, and send the first clock signal and the second clock signal to the main control module.

Optionally, the main control module is used as a management plane and a core module of a central computing decision, and may be responsible for device management, fault detection, and further analysis and operation of a computation result of a computing unit of the entire vehicle central computing platform, and may also be responsible for work such as forwarding of PCIE (peripheral component interconnect express, high-speed serial computer extended bus standard) data, ethernet data, CAN (Controller Area Network ) data, and data intercommunication of a corresponding command. Optionally, the main control module includes a CPU (Central Processing Unit) module and an MCU (micro controller Unit) module, and may be used as hardware bearers of an AP (Adaptive Platform) middleware and a CP (Classic Platform) middleware, respectively. The CPU can optionally execute the application functions of equipment management, data distribution and complex decision making by means of the AP middleware; the MCU can optionally execute the control of vehicle control decision by means of the CP middleware, and is used for further carrying out command issuing and the like with an external area controller and a vehicle control execution unit.

Optionally, the computation module may be used as an important computation module of the autopilot domain, and may include resources such as a NPU (neural-network processor), a GPU (Graphics Processing Unit), a CPU, and a DSP (Digital Signal Processing) for deep learning and data analysis. The calculation result output by the calculation force module can be selectively transmitted to the main control module for further decision calculation, and the main control module can issue a command to an external execution unit to perform vehicle control execution action.

Optionally, the FPGA module may be configured to perform data preprocessing on external sensing data, send the original or data preprocessed data to the main control module through the PCIE and the ethernet, and distribute the data to the corresponding computing module or cockpit unit by the main control module, so as to perform further video analysis and data operation. The sensing data may include data collected by a camera, a millimeter wave radar, a laser radar, and the like. Optionally, the FPGA module may receive a clock signal generated by the system and issued by the GPS module, where the clock signal may be a 1PPS clock signal. The FPGA module may generate digitized ethernet information based on the clock signal, and distribute the digitized ethernet information to each computing module through the main control module by using a TSN (Time-Sensitive Network) ethernet switch chip of the central computing unit. Optionally, the FPGA module may also send the ethernet information to other clock application modules, such as a cockpit module.

Fig. 1 is a schematic view of a scenario of a clock synchronization method according to an embodiment of the present application. An application scenario of the clock synchronization method provided by the present application is further described below based on fig. 1. In the application scenario, the calculation force module can comprise calculation force 0, calculation force 1, calculation force 2, calculation force 3, calculation force 4, calculation force 5, calculation force 6 and calculation force 7, the main control module can comprise main control 0 and main control 1, and the FPGA module can comprise FPGA preprocessing module 0 and FPGA preprocessing module 1.

Optionally, the application scenario of the clock synchronization method may further include an intelligent cockpit module. The intelligent cockpit module can be selectively connected with a camera in the cockpit to realize main functions of the cockpit on one hand, and can selectively forward data to the force calculation module through the main control module to perform complex algorithm operation of a DMS (Driver Monitor System) and other systems on the other hand, and corresponding operation results can be transmitted back to the cockpit module through the main control module, so that the cockpit module can perform further display operation and human-computer interaction action based on the operation results.

Optionally, the number of the master control modules may be multiple. In the application scenario, a plurality of main control modules or a plurality of computing modules can also be networked in a master-slave networking mode, so that system-level redundancy backup is realized. In particular, the plurality of master modules may have a master priority order, wherein a module with a lower priority may act as a backup module for a module with a higher priority.

In an alternative embodiment, as illustrated in fig. 1, master 0 may be the highest priority master module. In a normal state, the master control 0 may be connected to each computation force module, the cockpit module, and the FPGA module through a data path, and may perform operations such as device management, data distribution, computation backtransmission, and the like based on the highest master-slave priority. Alternatively, master 1 may have a lower priority than master 0. The main control 1 also performs data intercommunication with the above modules through the data path. When the master control 0 is abnormal, the data path can be switched to the standby data path where the master control 1 is located, so that the system-level functional safety redundancy backup is adopted to perform real-time redundancy backup switching, and real-time hot switching is realized.

Optionally, the multiple main control modules may perform data synchronization, data intercommunication, and other interactions through PCIE and ethernet, so as to ensure that the multiple main control modules keep synchronization in real time.

Optionally, the modules may be interconnected and intercommunicated with each other through backplane, cable, board-to-board connector, and other forms.

Optionally, the application scenario may further include a power module, where the power module includes a power supply 0 and a power supply 1. The whole clock synchronization system can adopt double-power redundancy backup, namely a power supply 1 and a power supply 0, so as to provide the working stability of the system.

An exemplary flow of a clock synchronization method provided by the present application is described below. Fig. 2 is a first flowchart of a clock synchronization method provided in an embodiment of the present application, and the present specification provides a method or a flowchart with operation steps as shown in the embodiment or the flowchart, but may include more or less operation steps based on conventional or non-inventive labor. The sequence of steps recited in the embodiments is only one of many execution sequences, and does not represent the only execution sequence, and in actual execution, the steps can be executed according to the method or the flow sequence shown in the embodiment or the figure, or executed in parallel (for example, in the environment of a parallel processor or a multi-thread processing). In an alternative embodiment, the execution subject of the clock synchronization method may be an active module. Specifically, as shown in fig. 2, an exemplary process includes:

step S201: and receiving and analyzing clock synchronization data sent by the programmable logic module to obtain a first clock signal and a second clock signal.

Optionally, the first clock signal and the second clock signal may be used to provide references to the plurality of clock application units alternately for synchronizing the plurality of clock application units clocks.

Optionally, the clock synchronization data may be data obtained by converting the first clock signal and the second clock signal by the programmable logic module. The programmable logic module may send clock synchronization data to the master control module. Optionally, the programmable logic module may be an FPGA module.

Step S201 is further explained below based on fig. 6 c.

Fig. 6c is a schematic structural diagram of a second module of the clock synchronization method according to the embodiment of the present application. As illustrated in fig. 6c, the master module may include master 0 and master 1. The master control 0 and the master control 1 may respectively receive clock synchronization data sent by the FPGA, and optionally, the clock synchronization data may include a first clock signal and an ethernet packet with 1PPS data of a second clock signal. The master 1 and the master 0 may respectively analyze the clock synchronization data to obtain a first clock signal and a second clock signal.

In an optional implementation manner, data synchronization and data interaction may be performed between the master control 1 and the master control 2 through ethernet, PCIE, CAN bus, and the like, so as to ensure that the first clock signals in the respective two master control modules are consistent, and the second clock signals are also consistent. Optionally, if the two main control modules detect that the first clock signal or the second clock signal in the two modules is inconsistent through data interaction, the signals in the main control module with the low priority are adjusted through data interaction, that is, the first clock signal or the second clock signal of the main control 1 is adjusted to be consistent with the corresponding first clock signal or the corresponding second clock signal in the main control 0.

Step S202: and obtaining difference information according to the second clock signal and the first clock signal.

Optionally, the difference information may characterize a difference between the second clock signal and the first clock signal.

Step S203: and if the difference information meets the preset condition, sending a first deviation rectifying instruction to the programmable logic module.

Optionally, the first deviation rectifying instruction may be used to instruct the programmable logic module to adjust the second clock signal to obtain the first deviation rectifying signal. The second clock signal may be obtained by the programmable logic module shifting the first clock signal one cycle backward.

An exemplary process of generating and transmitting the first clock signal and the second clock signal by the programmable logic module is further described below based on fig. 6a, 6b, and 6 c.

Fig. 6a is a schematic block diagram of a first module structure of a clock synchronization method according to an embodiment of the present disclosure.

As illustrated in fig. 6a, the GPS module may generate a clock synchronization signal and send the clock synchronization signal into the FPGA module. Wherein the clock synchronization signal may be a 1PPS clock signal.

Optionally, the FPGA module may receive the clock synchronization signal, and copy and transparently transmit the clock synchronization signal into multiple clock signals. As illustrated in fig. 6a, the FPGA may copy and pass through the received 1PPS clock signal as a first clock signal. Optionally, the FPGA module may perform data caching corresponding to the clock synchronization signal through an internal or external RAM including an SRAM (Static Random-Access Memory) or a DRAM (Dynamic Random-Access Memory). The signals sent by the FPGA may include a first clock signal and a second clock signal, the first clock signal may be obtained by the FPGA module copying the clock synchronization signal, and the second clock signal may be obtained by the FPGA module shifting the first clock signal backward by one cycle. The FPGA may send the first clock signal in a 1PPS clock signal and send the second clock signal in an ethernet packet.

Fig. 6b is a schematic diagram of a first signal waveform of a clock synchronization method according to an embodiment of the present application. As illustrated in fig. 6b, TR0' may be a pulse waveform corresponding to the first clock signal, and TR0 ″ may be a pulse waveform corresponding to the second clock signal. Because the clock signals including the 1PPS clock signal have higher requirements on the precision, for the scheme of carrying out the clock synchronization of the whole system by adopting the 1PPS clock signal, the requirements on the rising edge time and the jitter of the signal waveform edge are higher, and the requirement needs to reach an ns level, for example, the jitter deviation is controlled within 10 ns. Therefore, in order to ensure that the data recovery of the rising edge and the falling edge can be effectively analyzed and carried out when the Ethernet message is received by the subsequent stage, and reduce the delay caused by forwarding, AD sampling and decoding in the middle Ethernet, the FPGA module can process the clock synchronization signal in the following way.

Optionally, the pulse of the clock synchronization signal sent by the GPS module and received by the FPGA module may be divided into P0, P1, P2, \ 8230, PN, according to a period. The first clock signal pulse that the FPGA module copies and distributes the clock synchronization signal may be P0', P1', P2', \8230;, PN' includes P0', P1', P2', P3' illustrated in fig. 6 b. For the second clock signal, the FPGA module may delay the clock synchronization signal converted into the ethernet packet by one clock cycle to transmit when performing AD sampling and converting into the ethernet packet, that is, it shifts back by one clock cycle with respect to P0' to forward, so as to obtain forwarded packets as P0 ", P1", P2 ", 8230, PN", including P0 ", P1", P2 ", and P3" shown in fig. 6 b. Where the rising edge of P0 'may remain synchronized in time with the rising edge of P1', the rising edge of P1 'may remain synchronized in time with the rising edge of P2', and so on. In an alternative embodiment, step S202 may include: the deviation of the rising edge of P0' ' from the rising edge of P1' is determined as difference information.

In the embodiment of the present application, the second rising edge of the First clock signal and the First rising edge of the second clock signal can be controlled to keep synchronous by shifting the First clock signal or the clock synchronization signal backward to obtain the second clock signal, so that when the module at the subsequent stage performs comparison feedback in conjunction with a FIFO (First Input First Output) in a RAM of the FPGA module, the First clock signal can be positioned in the First clock signal to a position corresponding to the rising edge of the First period of the second clock signal, regardless of whether the phase of the second clock signal is shifted forward or backward, so as to determine the First deviation value more conveniently, and eliminate an error generated in a transmission process according to the First deviation value, so as to accurately control and adjust the second clock signal, so that the second rising edge of the First clock signal and the First rising edge of the second clock signal received and analyzed by the subsequent main control module keep synchronous or are controlled within a preset range; and the second clock signal which is shifted backwards by one period is sent in the form of an Ethernet message, so that the time delay of the second clock signal in the Ethernet forwarding, AD sampling and decoding processes can be reduced, and the accuracy of the calibration of the second clock signal is ensured.

This is explained below on the basis of fig. 6 c.

As illustrated in fig. 6c, in this embodiment, the master control module of the central computing unit may include a master control 0 and a master control 1, and the FPGA module may include an FPGA interface board module 0.

The FPGA interface board module 0 may send clock synchronization data to the main control 1 and the main control 0, where the clock synchronization data may include data in an ethernet message form and 1PPS clock signals. Optionally, the FPGA module may transmit the first clock signal to the main control module, and convert the second clock signal into an ethernet packet with TSN characteristics by using an internal logic circuit and an internal or external AD (analog-to-Digital) module, and send the ethernet packet to the main control module through the ethernet switching chip. Optionally, in the whole clock synchronization system, the clock signal may be distributed or processed through an ethernet and a form supporting TSN (Time scale Network).

The following proceeds to the explanation of step S203 based on fig. 2.

In the above-described embodiment in which the second clock signal is obtained by the FPGA module shifting the first clock signal backward by one cycle, the difference information may include a first deviation value, and the first deviation value may represent a deviation between a rising edge of the second cycle of the first clock signal and a rising edge of the first cycle of the second clock signal. In this embodiment, if the difference information satisfies the preset condition, sending a first deviation rectifying instruction to the FPGA module may include: if the first deviation value meets a first preset deviation condition, sending a first deviation rectifying instruction to the FPGA module; the first deviation rectifying command comprises a first deviation value. Optionally, the first preset deviation condition may be that the first deviation value is greater than a preset value, and the preset value may be 0.05 cycles, 0.1 cycles, and the like; optionally, the first preset deviation condition may be that the first deviation value is within a preset range, for example, within a range of 0.1 cycle to 0.9 cycle. The FPGA module can receive the first deviation rectifying instruction and adjust the second clock signal based on the first deviation value. Optionally, the second clock signal may be shifted by a number of cycles corresponding to the first offset value.

Optionally, after receiving the first deviation correcting instruction, the RAM of the FPGA module may adjust the FIFO stack according to the first deviation value, thereby implementing adjustment of the phase of the second clock signal, and obtaining the first deviation correcting signal.

According to the clock synchronization method, the first clock signal can be used as a reference, the second clock signal can be subjected to feedback calibration, and the efficiency and accuracy of clock signal calibration can be improved.

A clock synchronization method provided in the embodiment of the present application is further described below based on fig. 3.

Fig. 3 is a second flowchart of a clock synchronization method according to an embodiment of the present application. As illustrated in particular in fig. 3, an exemplary process may include:

step S301: and receiving and analyzing clock synchronization data sent by the programmable logic module to obtain a first clock signal and a second clock signal.

Step S302: and obtaining difference information according to the second clock signal and the first clock signal.

Step S303: and if the difference information meets the preset condition, sending a first deviation rectifying instruction to the programmable logic module.

For the relevant content of step S301 to step S303, reference may be made to the above description about step S201 to step S203, and details are not described here again.

Step S304: and receiving a first deviation rectifying signal sent by the programmable logic module.

Step S304 is further explained below based on fig. 6 c. As illustrated in fig. 6c, the master module may include master 0 and master 1. The master control 0 and the master control 1 may respectively receive clock synchronization data, and optionally, the clock synchronization data may include a first clock signal and an ethernet packet of 1PPS data with a first deskew signal. The master control 1 and the master control 0 can respectively analyze the clock synchronization data to obtain a first clock signal and a first deviation rectifying signal.

In an optional implementation manner, data synchronization and data interaction CAN be performed between the main control module 1 and the main control module 2 through ethernet, PCIE, CAN bus, and the like, so as to ensure that the first clock signals in the respective main control modules are consistent, and the first deviation rectification signals are also consistent. Optionally, if the two main control modules detect that the first clock signal or the first deviation-correcting signal in the two modules is inconsistent through data interaction, the signals in the main control module with the low priority are adjusted through data interaction, that is, the first clock signal or the first deviation-correcting signal of the main control 1 is adjusted to be consistent with the corresponding first clock signal or the corresponding first deviation-correcting signal in the main control 0.

Step S305: and determining a target clock signal according to the first clock signal or the first deviation correcting signal.

Optionally, the first clock signal and the first deviation rectifying signal may be backup to each other. If the first clock signal is detected to be in an abnormal state, determining a target clock signal according to the first deviation correcting signal; if the first deviation correcting signal is detected to be in an abnormal state, the target clock signal can be determined according to the first clock signal.

In an optional implementation manner, after determining the target clock signal, the method may further include: and carrying out jitter removal and averaging operation on the target clock signal to obtain an application clock signal. Optionally, after receiving the target clock signal of the preset period, the target clock signal may be subjected to debouncing and averaging to obtain the application clock signal. Alternatively, the application clock signal may be a low jitter clock signal.

Step S305 is further explained below based on fig. 4.

Fig. 4 is a schematic diagram of a third flow of a clock synchronization method according to an embodiment of the present application. Specifically as illustrated in fig. 4, an exemplary flow may include:

step S401: and determining a reference clock signal according to the first clock signal or the first deviation correcting signal.

In an alternative embodiment, step S401 may be performed after the main control module and the programmable logic module compare and correct the second clock signal to determine the reference clock signal. The reference clock signal may be used as a reference for comparison, so that the main control module performs correction or backup supplementation on the first clock signal, the first correction signal, or loss, interruption, or misrepresentation of the clock synchronization data based on the reference clock signal, and optionally, after receiving the first clock signal or the first correction signal of a preset period, the first clock signal or the first correction signal may be subjected to debouncing and averaging to obtain the reference clock signal. Alternatively, the reference clock signal may be a low jitter clock signal.

Optionally, the first clock signal and the first deviation rectifying signal may be backup to each other. If the first clock signal is detected to be in an abnormal state, determining a reference clock signal according to the first deviation correcting signal; if the first deviation correcting signal is detected to be in an abnormal state, the reference clock signal can be determined according to the first clock signal.

Step S402: and if the first deviation rectifying signal is detected to have a missing period, determining a supplementary clock signal from the reference clock signal.

Optionally, a supplemental clock signal may be used to supplement the information on the missing period.

In an optional implementation manner, whether the first deviation correcting signal has a missing period may be detected, and if the first deviation correcting signal has the missing period, the first deviation correcting signal may be directly clipped according to waveform information of the reference clock signal, so as to complement the first deviation correcting signal, that is, a waveform portion corresponding to the missing period in the reference clock signal is determined as a complementary clock signal.

In an optional implementation manner, step S402 may further include: and detecting whether the first clock signal has a missing period, if so, directly cutting the missing clock signal according to the waveform information of the reference clock signal so as to complement the first clock signal, namely determining the waveform part corresponding to the missing period in the reference clock signal as a complementary clock signal.

Step S403: and sending a signal supplement instruction to the programmable logic module.

Optionally, the signal supplement instruction may include a supplement clock signal.

In an optional implementation manner, the signal supplement instruction may be used to instruct the FPGA module to supplement the first deviation correction signal according to the supplement clock signal, so as to obtain a target supplement signal.

In the embodiment of the application, the complementary clock signal is cut from the reference clock signal and supplemented to the first deviation correcting signal, so that the target complementary signal can be obtained through signal supplementation under the condition that the first deviation correcting signal is not complete, the integrity of the reference signal is ensured, and the subsequent influence on clock synchronization reference judgment of the clock application module is avoided.

In the embodiment described above where step S402 includes detecting whether there is a missing period in the first clock signal, the signal supplementing instruction may be further configured to instruct the FPGA module to supplement the first clock signal according to the supplementing clock signal, so as to obtain the supplemented first clock signal.

Step S404: and receiving the target supplement signal sent by the programmable logic module.

Step S404 is further explained below based on fig. 6 c. As illustrated in fig. 6c, the master module may include master 0 and master 1. The master 0 and the master 1 may respectively receive clock synchronization data, and optionally, the clock synchronization data may include a first clock signal and an ethernet packet of 1PPS data with a target complementary signal. The master 1 and the master 0 may analyze the clock synchronization data, respectively, to obtain a first clock signal and a target complementary signal.

In an optional implementation manner, data synchronization and data interaction may be performed between the main control 1 and the main control 2 through ethernet, PCIE, CAN bus, and the like, so as to ensure that the first clock signals in the two main control modules are consistent, and the target complementary signals are also consistent. Optionally, if the two main control modules detect that the first clock signals or the target complementary signals in the two modules are inconsistent through data interaction, the signals in the main control module with the low priority are adjusted through data interaction, that is, the first clock signal or the target complementary signal of the main control 1 is adjusted to be consistent with the corresponding first clock signal or the corresponding target complementary signal in the main control 0.

Step S405: a target clock signal is determined based on the first clock signal or the target supplemental signal.

Optionally, the first clock signal and the target complementary signal may be alternative to each other. If the first clock signal is detected to be in an abnormal state, determining a target clock signal according to the target supplement signal; if the target supplement signal is detected to be in an abnormal state, the target clock signal can be determined according to the first clock signal.

In an optional implementation, after determining the target clock signal, the method may further include: and carrying out debouncing and mean value taking operations on the target clock signal to obtain an application clock signal. Optionally, after receiving the target clock signal of the preset period, the target clock signal may be subjected to debounce and averaging to obtain the application clock signal. Alternatively, the application clock signal may be a low jitter clock signal.

Step S305 is further explained below based on fig. 5.

Fig. 5 is a fourth flowchart illustrating a clock synchronization method according to an embodiment of the present application. Specifically as illustrated in fig. 5, an exemplary flow may include:

step S501: and determining a reference clock signal according to the first clock signal or the first deviation correcting signal.

In an alternative embodiment, the step S501 may be performed after the main control module and the FPGA module compare and correct the second clock signal to determine the reference clock signal. The reference clock signal may be used as a reference for comparison, so that the main control module performs correction or backup supplementation on the first clock signal, the first correction signal, or loss, interruption, or misrepresentation of the clock synchronization data based on the reference clock signal, and optionally, after receiving the first clock signal or the first correction signal of a preset period, the first clock signal or the first correction signal may be subjected to debouncing and averaging to obtain the reference clock signal. Alternatively, the reference clock signal may be a low jitter clock signal.

Optionally, the first clock signal and the first deviation rectifying signal may be mutually standby. If the first clock signal is detected to be in an abnormal state, determining a reference clock signal according to the first deviation correcting signal; if the first deviation correcting signal is detected to be in an abnormal state, the reference clock signal can be determined according to the first clock signal.

Step S502: and obtaining a second deviation value based on the first deviation correcting signal and the reference clock signal.

Optionally, the second deviation value may be obtained by comparing a rising edge of the first deviation correcting signal with a rising edge of the reference clock signal. The second deviation value may be indicative of a deviation between a rising edge of a second cycle of the first deskew signal and a rising edge of the first cycle or the second cycle of the reference clock signal.

Two embodiments for obtaining the second deviation value based on the first deviation correcting signal and the reference clock signal are described as follows:

in a first optional implementation manner, if the reference clock signal is determined based on the first clock signal, step S502 may include: and comparing the rising edge of the second period of the first deviation correcting signal with the rising edge of the first period of the reference clock signal. The second deviation value may be indicative of a deviation between a rising edge of the second period of the first deskew signal and a rising edge of the first period of the reference clock signal.

In a second alternative embodiment, if the reference clock signal is determined based on the first deviation rectifying signal, step S502 may include: and comparing the rising edge of the second period of the first deviation correcting signal with the rising edge of the second period of the reference clock signal. The second deviation value may be indicative of a deviation between a rising edge of the second period of the first deskew signal and a rising edge of the second period of the reference clock signal.

Optionally, step S502 may further include: a second offset value is derived based on the first clock signal and the reference clock signal. The second deviation value may be indicative of a deviation between a rising edge of the first or second cycle of the first clock signal and a rising edge of the first cycle of the reference clock signal.

Two embodiments for obtaining the second deviation value based on the first clock signal and the reference clock signal are described below:

in a first alternative implementation, if the reference clock signal is determined based on the first clock signal, step S502 may include: the rising edge of the first period of the first clock signal is compared with the rising edge of the first period of the reference clock signal. The second deviation value may characterize a deviation between a rising edge of the first cycle of the first clock signal and the first cycle of the reference clock signal.

In a second alternative embodiment, if the reference clock signal is determined based on the first deviation correcting signal, step S502 may include: the rising edge of the second period of the first clock signal is compared with the rising edge of the first period of the reference clock signal. The second deviation value may be indicative of a deviation between a rising edge of the second cycle of the first clock signal and a rising edge of the first cycle of the reference clock signal.

Step S503: and if the second deviation value meets a second preset deviation condition, sending a second deviation rectifying instruction to the programmable logic module.

Optionally, the second deviation rectifying instruction may include a second deviation value. The second deviation rectifying instruction can be used for instructing the FPGA module to adjust the first deviation rectifying signal according to the second deviation value to obtain a second deviation rectifying signal.

In an alternative embodiment, the second preset deviation condition may be that the second deviation value is greater than a preset value, and the preset value may be 0.05 cycles, 0.1 cycles, and the like; optionally, the second preset deviation condition may be that the second deviation value is within a preset range, for example, within a range of 0.1 cycle to 0.9 cycle. The FPGA module can receive a second deviation rectifying instruction and adjust the first deviation rectifying signal based on the second deviation value. Optionally, the first deviation correcting signal may be shifted by a cycle number corresponding to the second deviation value.

In the embodiment described above where step S502 includes obtaining the second deviation value based on the first clock signal and the reference clock signal, the FPGA module may receive the second deviation rectifying instruction and adjust the first clock signal based on the second deviation value. Optionally, the first clock signal may be shifted by a number of cycles corresponding to the second offset value.

Step S503 is further explained below based on fig. 7.

Fig. 7 is a schematic diagram of a second signal waveform of a clock synchronization method according to an embodiment of the present application. As illustrated in fig. 7, the second predetermined deviation condition may be that the second deviation value is greater than or equal to the predetermined threshold Δ TH, C0 in fig. 7 represents the reference clock signal, a first D ″ represents the first deviation correcting signal in the first embodiment, and a second D ″ represents the first deviation correcting signal in the second embodiment. Two embodiments are specifically described below.

In the first embodiment, as illustrated in fig. 7, the waveform of the first deviation correcting signal is advanced in phase from the waveform of the reference clock signal, and the second deviation value is Δ T1. When the absolute value of delta T1| > = | delta TH |, the second deviation value meets a second preset deviation condition, namely the edge jitter of the current first deviation correcting signal is considered to exceed the warning threshold range, and a second deviation correcting instruction is sent to the FPGA module so as to adjust the first deviation correcting signal through feedback.

In the second embodiment, as illustrated in fig. 7, the second deviation value is Δ T2 after the phase of the waveform of the first deviation correcting signal is compared with the waveform of the reference clock signal. When | Δ T2| > = | Δ TH |, the second deviation value meets a second preset deviation condition, which is equivalent to that the edge jitter of the current first deviation correction signal exceeds the warning threshold range, and a second deviation correction instruction is sent to the FPGA module so as to adjust the first deviation correction signal through feedback.

Optionally, after receiving the second deviation rectifying instruction, the RAM of the FPGA module may adjust the FIFO stack according to the second deviation value, thereby implementing adjustment of the phase of the first deviation rectifying signal, and obtaining the second deviation rectifying signal.

Optionally, while sending the second deviation rectifying instruction to the FPGA, the execution module may also perform alarm recording, and know the RAM of the FPGA interface module, adjust the FIFO stack, and adjust the output D ″ phase.

Step S504: and receiving a second deviation rectifying signal sent by the programmable logic module.

Step S404 is further explained below based on fig. 6 c. As illustrated in fig. 6c, the master module may include master 0 and master 1. The master control 0 and the master control 1 may respectively receive clock synchronization data, and optionally, the clock synchronization data may include a first clock signal and an ethernet packet of 1PPS data with a second deviation correcting signal. The master control 1 and the master control 0 may respectively analyze the clock synchronization data to obtain a first clock signal and a second deviation correction signal.

In an optional implementation manner, data synchronization and data interaction CAN be performed between the main control module 1 and the main control module 2 through ethernet, PCIE, CAN bus, and the like, so as to ensure that the first clock signals in the respective main control modules are consistent, and the second deviation rectification signals are also consistent. Optionally, if the two main control modules detect that the first clock signal or the second deviation-correcting signal in the two modules is inconsistent through data interaction, the signals in the main control module with the low priority are adjusted through data interaction, that is, the first clock signal or the second deviation-correcting signal of the main control 1 is adjusted to be consistent with the corresponding first clock signal or the second deviation-correcting signal in the main control 0.

In an alternative embodiment, steps S503 to S504 may be: and if the second deviation value meets a second preset deviation condition, adjusting the first deviation correcting signal based on the second deviation value by using the memory resource through the CPU of the main control module to obtain a second deviation correcting signal. In such an embodiment, there is no need to communicate with the FPGA module, nor to perform feedback interaction.

Step S505: and determining a target clock signal according to the first clock signal or the second deviation correcting signal.

Optionally, the first clock signal and the second deskew signal may be backup to each other. If the first clock signal is detected to be in an abnormal state, determining a target clock signal according to the second deviation correcting signal; if the second deviation correcting signal is detected to be in an abnormal state, the target clock signal can be determined according to the first clock signal.

In an optional implementation, after determining the target clock signal, the method may further include: and carrying out jitter removal and averaging operation on the target clock signal to obtain an application clock signal. Optionally, after receiving the target clock signal of the preset period, the target clock signal may be subjected to debounce and averaging to obtain the application clock signal. Alternatively, the application clock signal may be a low jitter clock signal.

The following description is continued on the basis of fig. 3:

step S306: and sending the target clock signal to the clock application module.

In an alternative embodiment, in the embodiment of obtaining the application clock signal set forth above, step S306 may include: sending the application clock signal to the clock application module.

Step S306 is further explained below based on fig. 8.

Fig. 8 is a schematic structural diagram of a third module of a clock synchronization method according to an embodiment of the present application. As illustrated in fig. 8, the clock application module may include a computing unit 0 and a computing unit 1, the main control module may include a main control 0 and a main control 1, and the FPGA module may include an FPGA interface board module 0.

Wherein, master 0 may have the highest master priority, and the target clock signal may be sent from master 0 to compute unit 0, compute unit 1. The clock application module is not limited to the category, and in other alternative embodiments, the clock application module may also be any module that requires a reference clock, such as a vehicle control module, other computing power module, a cockpit module, and the like. Master 1 has a lower master priority than master 0. The master 1, as a standby master, may also send the target clock signal to the computing unit 0 and the computing unit 1.

Optionally, the master control 1 and the master control 0 may perform data interaction, so as to ensure that target clock signals of the master control 1 and the master control 0 are consistent or synchronous. After the target clock signal of master 0 is abnormal or lost, the target clock signal of master 1 can be used as a standby clock for switching. Taking the computing unit 0 as an example, the computing unit may receive a target clock signal sent by the master control 0 and a target clock signal sent by the master control 1, where the target clock signals sent by the two carry the priority information of the 0-level clock and the priority information of the 1-level clock respectively; after receiving the target clock signals transmitted by the two, the computing unit 0 may determine the target clock signal transmitted by the master 0 as the reference clock signal based on the 0-level clock priority information. An exemplary process of determining the reference clock signal by the calculating unit 1 may refer to the process of determining the reference clock signal by the calculating unit 0 described above, and is not described herein again.

The explanation of step S306 is continued based on fig. 3.

In an alternative embodiment, the number of the master control modules may be multiple. The clock application module may be configured to receive a plurality of target clock signals sent by the plurality of main control modules, and determine a master clock signal from the plurality of target clock signals according to the clock priority. In this application, not only first clock signal and second clock signal can be mutual backup to the target clock signal that a plurality of host system confirm can be mutual backup, can improve the reliability of clock source.

Optionally, the plurality of main control modules may perform data interaction and control with the plurality of computing units, the cabin unit, and the chassis control unit respectively through communication modes such as PCIE, ethernet (e.g., SGMII signal), CAN bus, I2C (Inter-Integrated Circuit, two-wire serial bus), GPIO (General Purpose Input/Output port), and the like. Meanwhile, each slave unit can identify the working state of the slave unit in time and report the working state to the master control module in forms of heartbeat, on-site and the like.

According to the clock synchronization method provided by the embodiment of the application, the clock source can be ensured to be stable in each module and each unit of the whole central computing platform through the digital processing of the clock signal and the mutual backup of the clocks of the plurality of main control modules; moreover, by determining the reference clock signal and carrying out real-time verification and leakage detection and defect filling according to the reference clock signal, the efficiency and the accuracy of clock signal verification can be improved; further, data interaction is realized through Ethernet, PCIE, CAN bus and the like, and under a central computing architecture, clock synchronization and cross-domain intercommunication of an intelligent driving domain, an intelligent cabin domain and a ground control domain CAN be realized; the main control unit executes the distribution and scheduling processing of the data to be processed in the plurality of computing units, so that the resource sharing of the computing units in the whole system can be realized, the computing resources can be reasonably distributed, and the computing power utilization rate of the system is improved.

Correspondingly, the application provides a clock synchronization device. Fig. 9 is a schematic structural diagram of a clock synchronization apparatus according to an embodiment of the present disclosure. As illustrated in fig. 9, the clock synchronization apparatus 900 for a master module may include:

a receiving module 901, configured to receive and analyze clock synchronization data sent by a programmable logic module, so as to obtain a first clock signal and a second clock signal; the first clock signal and the second clock signal are used for providing reference for standby to the plurality of clock application units so as to enable the plurality of clock application units to be clock-synchronized;

a determining module 902, configured to obtain difference information according to the second clock signal and the first clock signal;

a sending module 903, configured to send a first deviation rectifying instruction to the programmable logic module if the difference information meets a preset condition; the first deviation rectifying instruction is used for indicating the programmable logic module to adjust the second clock signal to obtain a first deviation rectifying signal.

Optionally, the second clock signal is obtained by shifting the first clock signal back by one cycle by the programmable logic module; the difference information includes a first deviation value that characterizes a deviation between a rising edge of the second cycle of the first clock signal and a rising edge of the first cycle of the second clock signal. The sending module 903 may also be configured to send a first deviation correcting instruction to the programmable logic module if the first deviation value meets a first preset deviation condition; the first deviation rectifying instruction comprises a first deviation value.

Optionally, the apparatus may further include an application module, configured to receive the first deviation rectifying signal sent by the programmable logic module; determining a target clock signal according to the first clock signal or the first deviation correcting signal; and sending the target clock signal to the clock application module.

Optionally, the determining module 902 may further be configured to determine the reference clock signal according to the first clock signal or the first deviation correcting signal; if the first deviation correcting signal is detected to have a missing period, determining a supplementary clock signal from the reference clock signal; the complementary clock signal is used for complementing the information on the missing period; sending a signal supplement instruction to the programmable logic module; the signal supplement instruction comprises a supplement clock signal and is used for instructing the programmable logic module to supplement the first deviation correction signal according to the supplement clock signal to obtain a target supplement signal; receiving a target supplementary signal sent by a programmable logic module; a target clock signal is determined based on the first clock signal or the target supplement signal.

Optionally, the determining module 902 may further be configured to determine the reference clock signal according to the first clock signal or the first deviation correcting signal; obtaining a second deviation value based on the first deviation correcting signal and the reference clock signal; the second deviation value represents the deviation between the rising edge of the second period of the first deviation correcting signal and the rising edge of the first period or the second period of the reference clock signal; if the second deviation value meets a second preset deviation condition, sending a second deviation rectifying instruction to the programmable logic module; the second deviation correcting instruction comprises a second deviation value and is used for instructing the programmable logic module to adjust the first deviation correcting signal according to the second deviation value to obtain a second deviation correcting signal; receiving a second deviation rectifying signal sent by the programmable logic module; and determining a target clock signal according to the first clock signal or the second deviation rectifying signal.

Optionally, the determining module 902 may further be configured to, after determining the target clock signal, perform debounce and mean operations on the target clock signal to obtain an application clock signal. The sending module 903 may also be configured to send an application clock signal to the clock application module.

Optionally, the number of the main control modules may be multiple; the clock application module may be configured to receive a plurality of target clock signals sent by the plurality of main control modules, and determine a master clock signal from the plurality of target clock signals according to the clock priority.

Embodiments of a clock synchronization apparatus of the present application may be based on the same concept as embodiments of a clock synchronization method of the present application.

Accordingly, an embodiment of the present disclosure further provides an electronic device, which includes a processor and a memory, where the memory stores at least one instruction, at least one program, a code set, or an instruction set, and the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement the clock synchronization method.

The method provided by the embodiment of the application can be executed in a computer terminal, a server or a similar operation device. Taking the example of running on a server, fig. 10 is a hardware structure block diagram of the server of the clock synchronization method provided in the embodiment of the present application. As shown in fig. 10, the server 1000 may have a relatively large difference due to different configurations or performances, and may include one or more Central Processing Units (CPUs) 1010 (the CPU 1010 may include but is not limited to a Processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 1030 for storing data, and one or more storage media 1020 (e.g., one or more mass storage devices) for storing applications 1023 or data 1022. Memory 1030 and storage media 1020 may be, among other things, transient or persistent storage. The program stored in the storage medium 1020 may include one or more modules, each of which may include a series of instruction operations for a server. Still further, the central processor 1010 may be configured to communicate with the storage medium 1020 and execute a series of instruction operations in the storage medium 1020 on the server 1000. The server 1000 may also include one or more power supplies 1050, one or more wired or wireless network interfaces 1050, one or more input-output interfaces 1040, and/or one or more operating systems 1021, such as Windows Server, mac OS XTM, unixTM, linuxTM, freeBSDTM, and so forth.

Input/output interface 1040 may be used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the server 1000. In one example, i/o Interface 1040 includes a Network adapter (NIC) that may be coupled to other Network devices via a base station to communicate with the internet. In one example, the input/output interface 1040 may be a Radio Frequency (RF) module, which is used for communicating with the internet in a wireless manner.

It will be understood by those skilled in the art that the structure shown in fig. 10 is merely illustrative and is not intended to limit the structure of the electronic device. For example, server 1000 may also include more or fewer components than shown in FIG. 10, or have a different configuration than shown in FIG. 10.

The present application provides a storage medium that can be disposed in a server to store at least one instruction, at least one program, a code set, or a set of instructions related to implementing a clock synchronization method in an embodiment of the method, where the at least one instruction, the at least one program, the code set, or the set of instructions is loaded and executed by the processor to implement the clock synchronization method.

Specifically, in this embodiment, the storage medium may be located in at least one network server of a plurality of network servers of a computer network. Optionally, in this embodiment, the storage medium may include, but is not limited to, a storage medium including: various media that can store program codes, such as a usb disk, a Read-only Memory (ROM), a removable hard disk, a magnetic disk, or an optical disk.

In the present invention, unless otherwise explicitly stated or limited, the terms "connected" and the like are to be understood broadly, and may be, for example, fixedly connected, detachably connected, or integrated; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in mutual relationship between the two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

It should be noted that: the foregoing sequence of the embodiments of the present application is for description only and does not represent the superiority and inferiority of the embodiments, and the specific embodiments are described in the specification, and other embodiments are also within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in the order of execution in different embodiments and achieve desirable results. Additionally, the processes depicted in the accompanying figures do not necessarily require a particular order to be shown or connected in order to achieve desirable results, and in some implementations, multitasking parallel processing may also be possible or may be advantageous.

All the embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment is described with emphasis on differences from other embodiments. In particular, for the embodiments of the apparatus/system, since they are based on embodiments similar to the method embodiments, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiments.

The foregoing is a preferred embodiment of the present invention, and it should be noted that it would be apparent to those skilled in the art that various modifications and enhancements can be made without departing from the principles of the invention, and such modifications and enhancements are also considered to be within the scope of the invention.

Claims

1. A clock synchronization method is applied to a master control module, and comprises the following steps:

receiving a first clock signal sent by a programmable logic module;

receiving and analyzing the Ethernet message sent by the programmable logic module to obtain a second clock signal; the first clock signal and the second clock signal are used for providing references for standby to a plurality of clock application units for mutually synchronizing the clocks of the plurality of clock application units;

obtaining difference information according to the second clock signal and the first clock signal;

if the difference information meets the preset condition, sending a first deviation rectifying instruction to the programmable logic module; the first deviation rectifying instruction is used for indicating the programmable logic module to adjust the second clock signal to obtain a first deviation rectifying signal;

the second clock signal is obtained by the programmable logic module by shifting the first clock signal back by one period;

the difference information includes a first deviation value characterizing a deviation between a rising edge of the second cycle of the first clock signal and a rising edge of the first cycle of the second clock signal;

if the difference information meets the preset condition, sending a first deviation rectifying instruction to the programmable logic module, wherein the first deviation rectifying instruction comprises the following steps:

if the first deviation value meets a first preset deviation condition, sending the first deviation rectifying instruction to the programmable logic module; the first deviation rectifying instruction comprises the first deviation value.

2. The method according to claim 1, wherein after sending a first deskew command to the programmable logic module if the difference information satisfies a predetermined condition, the method further comprises:

receiving the first deviation rectifying signal sent by the programmable logic module;

determining a target clock signal according to the first clock signal or the first deviation rectifying signal;

and sending the target clock signal to a clock application module.

3. The method of claim 2, wherein determining the target clock signal according to the first clock signal or the first de-skew signal comprises:

determining a reference clock signal according to the first clock signal or the first deviation rectifying signal;

if the first deviation correcting signal is detected to have a missing period, determining a supplementary clock signal from the reference clock signal; the complementary clock signal is used for supplementing the information on the missing period;

sending a signal supplement instruction to the programmable logic module; the signal supplement instruction comprises the supplement clock signal and is used for indicating the programmable logic module to supplement the first rectification signal according to the supplement clock signal to obtain a target supplement signal;

receiving the target supplementary signal sent by the programmable logic module;

determining the target clock signal according to the first clock signal or the target complementary signal.

4. The method of claim 2, wherein determining the target clock signal according to the first clock signal or the first de-skew signal comprises:

determining a reference clock signal according to the first clock signal or the first deviation correcting signal;

obtaining a second deviation value based on the first deviation correcting signal and the reference clock signal; the second deviation value represents a deviation between a rising edge of a second period of the first deviation correcting signal and a rising edge of the first period or the second period of the reference clock signal;

if the second deviation value meets a second preset deviation condition, sending a second deviation rectifying instruction to the programmable logic module; the second deviation rectifying instruction comprises the second deviation value, and the second deviation rectifying instruction is used for instructing the programmable logic module to adjust the first deviation rectifying signal according to the second deviation value to obtain a second deviation rectifying signal;

receiving the second deviation rectifying signal sent by the programmable logic module;

and determining the target clock signal according to the first clock signal or the second deviation rectifying signal.

5. The clock synchronization method according to any one of claims 2 to 4, wherein after determining the target clock signal, further comprising:

carrying out debouncing and mean value taking operations on the target clock signal to obtain an application clock signal;

the sending the target clock signal to the clock application module includes:

and sending the application clock signal to the clock application module.

6. The clock synchronization method according to claim 2, wherein the number of the master control modules is plural; the clock application module is configured to receive the plurality of target clock signals sent by the plurality of main control modules, and determine a primary clock signal from the plurality of target clock signals according to a clock priority.

7. A clock synchronization apparatus, the apparatus comprising:

the receiving module is used for receiving a first clock signal sent by the programmable logic module; receiving and analyzing an Ethernet message sent by the programmable logic module to obtain a second clock signal; the first clock signal and the second clock signal are used for providing references for standby to a plurality of clock application units for mutually synchronizing the clocks of the plurality of clock application units;

the sending module is used for sending a first deviation rectifying instruction to the programmable logic module if the difference information meets a preset condition; the first deviation rectifying instruction is used for indicating the programmable logic module to adjust the second clock signal to obtain a first deviation rectifying signal;

the second clock signal is obtained by the programmable logic module through shifting the first clock signal back by one cycle;

if the difference information meets a preset condition, sending a first deviation rectifying instruction to the programmable logic module, wherein the first deviation rectifying instruction comprises the following steps:

8. An electronic device comprising a processor and a memory, the memory having stored therein at least one instruction, at least one program, a set of codes, or a set of instructions, the at least one instruction, the at least one program, the set of codes, or the set of instructions being loaded and executed by the processor to implement the clock synchronization method of any of claims 1-6.

9. A computer readable storage medium having stored therein at least one instruction, at least one program, a set of codes, or a set of instructions, which is loaded and executed by a processor to implement the clock synchronization method of any of claims 1-6.