CN110112110A - Semiconductor package and preparation method thereof - Google Patents
Semiconductor package and preparation method thereof Download PDFInfo
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- CN110112110A CN110112110A CN201910482090.5A CN201910482090A CN110112110A CN 110112110 A CN110112110 A CN 110112110A CN 201910482090 A CN201910482090 A CN 201910482090A CN 110112110 A CN110112110 A CN 110112110A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Aerials With Secondary Devices (AREA)
Abstract
The present invention provides a kind of semiconductor package and preparation method thereof, and semiconductor package includes: re-wiring layer；Chip is bonded to the lower surface of re-wiring layer；Electric connection structure, positioned at the upper surface of re-wiring layer；Plastic packaging layer, positioned at the upper surface of re-wiring layer, and by electric connection structure plastic packaging；First antenna layer, positioned at the upper surface of plastic packaging layer；Frame structure positioned at the upper surface of plastic packaging layer, and is located at the periphery of first antenna layer；Lens jacket, positioned at the top of frame structure, lens jacket includes at least one lens；Second antenna stack, positioned at the lower surface of lens jacket, including at least one second antenna and the second antenna are correspondingly arranged with lens；Soldered ball convex block, positioned at the lower surface of re-wiring layer.Semiconductor package of the invention can effectively reduce the volume of encapsulating structure, help to improve device integration；And semiconductor package of the invention also has many advantages, such as that transmission signal path is short, transmission loss is low, antenna gain is high.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly to a kind of semiconductor package and its preparation side
Method.
Background technique
With the development of science and technology, mobile communication technology will also enter the 5G epoch, the covering of wireless base station is more and more wider, letter
Number intensity is also increasingly stronger.But economic fast development keeps the density of City Building increasing, thus signal of communication is passing
The barrier encountered during broadcasting is also more and more, this proposes the signal reception of mobile communication terminal higher and higher
It is required that.Existing portable mobile communication terminal is built-in with antenna structure usually to receive signal, and antenna structure usually will be more
A functional module (for example, active component and passive element) and antenna combination form, and more widespread practice is by each function
Module and antenna assemblies are on pcb board.And each functional module and antenna are arranged on the surface of pcb board in above structure, can be occupied
The biggish area of pcb board, so that there are the transmission paths of transmission signal is longer, antenna performance is poor, power consumption for entire encapsulating structure
The problems such as larger and encapsulation volume is larger.Simultaneously as electronic circuit is relatively more in printed wiring board, antenna and other metal wires
The problems such as there are electromagnetic interferences between road, or even there is also the risks that antenna and other metallic circuits are shorted.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of semiconductor package and its
Preparation method, route for solving transmission signal existing for encapsulating structure in the prior art is longer, electrical property and antenna performance compared with
Difference, the problems such as power consumption is larger and encapsulation volume is larger.
In order to achieve the above objects and other related objects, the present invention provides a kind of semiconductor package, the semiconductor
Encapsulating structure includes:
Re-wiring layer；
Chip is bonded to the lower surface of the re-wiring layer, and is electrically connected with the re-wiring layer；
Electric connection structure is electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；
Plastic packaging layer, positioned at the upper surface of the re-wiring layer, and by the electric connection structure plastic packaging；
First antenna layer is electrically connected positioned at the upper surface of the plastic packaging layer, and with the electric connection structure, and described first day
Line layer includes at least one first antenna；
Frame structure positioned at the upper surface of the plastic packaging layer, and is located at the periphery of the first antenna layer；
Lens jacket, positioned at the top of the frame structure, the lens jacket includes at least one lens；
Second antenna stack, positioned at the lower surface of the lens jacket, and with the first antenna layer have spacing, described second
Antenna stack includes that the lens of at least one second antenna and second antenna and the lens jacket are correspondingly arranged；
Soldered ball convex block is electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer.
Optionally, the quantity of the first antenna, second antenna and the lens is multiple and first day described
Line, second antenna and the lens correspond.
Optionally, the frame structure includes resinous framework structure, metal framework structure or ceramic frame configuration.
Optionally, the semiconductor package further includes Underfill layer, and the Underfill layer is located at the chip
Between the re-wiring layer.
Optionally, the lens are convex lens, and the lens jacket further includes planar portions, and the planar portions are located at the frame
The top of structure, the convex lens are located at the upper surface of the planar portions.
The present invention also provides a kind of preparation method of semiconductor package, the preparation method of the semiconductor package
Include the following steps:
Substrate is provided, the upper surface of Yu Suoshu substrate forms sacrificial layer；
Re-wiring layer is formed in the upper surface of the sacrificial layer；
Electric connection structure, the electric connection structure and the re-wiring layer are formed in the upper surface of the re-wiring layer
Electrical connection；
Plastic packaging layer is formed in the upper surface of the re-wiring layer, the plastic packaging layer is by the electric connection structure plastic packaging；
First antenna layer is formed in the upper surface of the plastic packaging layer, the first antenna layer is electrically connected with the electric connection structure
It connects, the first antenna layer includes at least one first antenna；
Frame structure is formed in the upper surface of the plastic packaging layer, the frame structure is located at the outer of the first antenna layer
It encloses；
Lens substrate is provided, a surface of the lens substrate is formed with the second antenna stack, and second antenna stack includes
At least one second antenna；The lens substrate is bonded to the top of the frame structure, second antenna stack after bonding
There is spacing positioned at the lower surface of the lens substrate, and with the first antenna layer；
The lens substrate is performed etching to form lens jacket, the lens jacket includes at least one lens, described
Mirror is corresponding up and down with second antenna；
Remove the substrate and the sacrificial layer；
Chip is provided, by the chip bonding in the lower surface of the re-wiring layer, the chip and the cloth again
The electrical connection of line layer；
Soldered ball convex block is formed in the lower surface of the re-wiring layer, the soldered ball convex block is electrically connected with the re-wiring layer
It connects.
Optionally, the upper surface of Yu Suoshu sacrificial layer forms the re-wiring layer and includes the following steps:
Bottom dielectric layer is formed in the upper surface of the sacrificial layer；
Capsulation material layer is formed in the upper surface of the bottom dielectric layer；
Seed layer is formed in the upper surface of the capsulation material layer；
Processing is patterned to the seed layer and the capsulation material layer；
Dielectric layer and metal conducting layer are formed in the upper surface of the bottom dielectric layer, the metal conducting layer is located at described
In dielectric layer, and it is electrically connected with the seed layer；The metal conducting layer includes the metal line layer and metal of Spaced arrangement
The adjacent metal line layer is electrically connected by plug, the metal plug between the adjacent metal line layer.
Optionally, the frame structure of formation includes resinous framework structure, metal framework structure or ceramic frame configuration；
The lens of the lens jacket are convex lens.
Optionally, the upper surface of Yu Suoshu plastic packaging layer forms the first antenna layer and includes the following steps:
First antenna metal layer is formed in the upper surface of the plastic packaging layer；
The first antenna metal layer is performed etching include to obtain multiple first antennas being intervally arranged institute
State first antenna layer；
Second antenna stack is formed in a surface of the lens substrate to include the following steps:
The second antenna metal layer is formed in a surface of the lens substrate；
The second antenna metal layer is performed etching include to obtain multiple second antennas being intervally arranged institute
The second antenna stack is stated, the first antenna is correspondingly arranged up and down one by one with second antenna.
It optionally, further include in the chip and institute after the lower surface of the re-wiring layer by the chip bonding
State the step of Underfill layer is formed between re-wiring layer.
Optionally, the lens jacket includes planar portions and the lens in the planar portions, and the planar portions are located at institute
State the top of frame structure, the lens and the first antenna and second antenna be the multiple and described first antenna,
Second antenna and the lens correspond.
As described above, semiconductor package and preparation method thereof of the invention, has the advantages that of the invention
Semiconductor package is by that can effectively reduce envelope for plastic packaging above and below lens jacket, first antenna layer, the second antenna stack and chip
The volume of assembling structure improves the integrated level of device；The radiated wave of antenna is focused by the lens of lens jacket, can effectively be mentioned
High antenna gain；Only has air insulated between first antenna layer and the second antenna stack, the dielectric loss of air is minimum, can reduce
The loss of signal of first antenna layer and the second antenna stack, and transmission signal path is shorter in semiconductor package of the invention,
Available better electrical property and antenna performance.Using preparation method of the invention, it is remarkably improved the semiconductor packages of preparation
The performance of structure, and advantageously reduce production cost.
Detailed description of the invention
Fig. 1 is shown as the flow chart of the preparation method of the semiconductor package provided in the embodiment of the present invention one.
Fig. 2 to 19 is shown as each step institute in the preparation method of the semiconductor package provided in the embodiment of the present invention one
Obtain the cross section structure schematic diagram of structure；Wherein, Figure 18 and Figure 19 is shown as the semiconductor packages provided in the embodiment of the present invention two
The cross section structure schematic diagram of structure.
Component label instructions
10 substrates
11 sacrificial layers
12 re-wiring layers
121 bottom dielectric layers
122 capsulation material layers
123 seed layers
124 dielectric layers
125 metal conducting layers
126 openings
13 electric connection structures
14 plastic packaging layers
15 first antenna layers
151 first antennas
16 frame structures
17 lens jackets
171 lens
172 planar portions
17a lens substrate
18 second antenna stacks
181 second antennas
19 soldered ball convex blocks
20 air chambers
21 chips
22 Underfill layers
S1~S11 step
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 1 is please referred to Figure 19.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only show in diagram with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present invention provides a kind of preparation method of semiconductor package, the semiconductor package
Preparation method includes the following steps:
1) substrate is provided, the upper surface of Yu Suoshu substrate forms sacrificial layer；
2) upper surface of Yu Suoshu sacrificial layer forms re-wiring layer；
3) upper surface of Yu Suoshu re-wiring layer forms electric connection structure, the electric connection structure and the rewiring
Layer electrical connection；
4) upper surface of Yu Suoshu re-wiring layer forms plastic packaging layer, and the plastic packaging layer is by the electric connection structure plastic packaging；
5) upper surface of Yu Suoshu plastic packaging layer forms first antenna layer, the first antenna layer and electric connection structure electricity
Connection, the first antenna layer includes at least one first antenna；
6) upper surface of Yu Suoshu plastic packaging layer forms frame structure, and the frame structure is located at the outer of the first antenna layer
It encloses；
7) lens substrate is provided, a surface of the lens substrate is formed with the second antenna stack, the second antenna stack packet
Include at least one second antenna；The lens substrate is bonded to the top of the frame structure, second antenna after bonding
Layer is located at the lower surface of the lens substrate, and has spacing with the first antenna layer；
8) lens substrate is performed etching to form lens jacket, the lens jacket includes at least one lens, described
Lens are corresponding up and down with second antenna；
9) substrate and the sacrificial layer are removed；
10) chip is provided, by the chip bonding in the lower surface of the re-wiring layer, the chip and it is described again
Wiring layer electrical connection；
11) lower surface of Yu Suoshu re-wiring layer forms soldered ball convex block, the soldered ball convex block and the re-wiring layer
Electrical connection.
In step 1), S1 step and Fig. 2 in Fig. 1 are please referred to, substrate 10, the upper surface shape of Yu Suoshu substrate 10 are provided
At sacrificial layer 11.
As an example, the material of the substrate 10 can be in silicon, glass, silica, ceramics, polymer and metal
A kind of material or two or more composite materials, shape can be round, rectangular or other any required shapes, surface area
Subsequent structural can be carried by being subject to.Preferably, in the present embodiment, the material of the substrate 10 is glass, i.e., the described substrate 10 is excellent
It is selected as substrate of glass.
As an example, the sacrificial layer 11 separating layer as re-wiring layer and the substrate 10 in the subsequent process,
It preferably selects the jointing material with smooth finish surface to be made, and must have certain binding force with the re-wiring layer,
In addition, it also has stronger binding force with the substrate 10.
As an example, the sacrificial layer 11 may include polymeric layer, band-like adhesion layer or photothermal conversion (LTHC) layer；Tool
Body, the material of the sacrificial layer 11 can be selected from two-sided adhesive tape (for example, chip coherent film or the non-conductive film for all having viscosity
Etc.) or pass through the adhesive glue etc. that spin coating proceeding makes；Preferably, in the present embodiment, the sacrificial layer 11 is preferably UV adhesive tape,
It is easy to pull off after UV light (ultraviolet light) irradiation；Certainly, in other examples, the sacrificial layer 11 can also select object
The other materials layer that physical vapor deposition method or chemical vapour deposition technique are formed, such as epoxy resin (Epoxy), silicon rubber
(silicone rubber), polyimides (PI), polybenzoxazoles (PBO), benzocyclobutene (BCB) etc., in later separation institute
When stating substrate 10, the methods of wet etching, chemical mechanical grinding can be used and remove the sacrificial layer 11.
As an example, the sacrificial layer 11 can also be formed by automatic pasting technique.
In step 2), the S2 step and Fig. 3 to Fig. 5 in Fig. 1 are please referred to, the upper surface of Yu Suoshu sacrificial layer 11 forms weight
New route layer 12.
As an example, the upper surface of Yu Suoshu sacrificial layer 11 forms the re-wiring layer 12 and may include in step 2)
Following steps:
2-1) upper surface of Yu Suoshu sacrificial layer 11 forms bottom dielectric layer 121, as shown in Figure 3；
2-2) upper surface of Yu Suoshu bottom dielectric layer 121 forms capsulation material layer 122, as shown in Figure 3；
2-3) upper surface of Yu Suoshu capsulation material layer 122 forms seed layer 123, as shown in Figure 3；
Processing 2-4) is patterned to the seed layer 123 and the capsulation material layer 122, as shown in Figure 4；Specifically
Processing can be patterned to the seed layer 123 and the capsulation material layer 122 using lithographic etch process；
2-5) upper surface of Yu Suoshu bottom dielectric layer 121 forms dielectric layer 124 and metal conducting layer 125, the metal
Conductive layer 125 is located in the dielectric layer 124, and is electrically connected with the seed layer 123, as shown in Figure 5；The metal conducting layer
125 include that the metal line layer (not indicating) of Spaced arrangement and metal plug (not indicating), the metal plug are located at
Between the adjacent metal line layer, the adjacent metal line layer is electrically connected.
As an example, the material of the bottom dielectric layer 121 may include low k dielectric.Specifically, the bottom is situated between
The material of electric layer 121 may include using in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass
It is one or more；According to the difference of specific the selection of material, the bottom dielectric layer 121 can using spin coating, CVD, etc.
The techniques such as ion enhancing CVD are formed.
As an example, the material of the capsulation material layer 122 may include but be not limited only to polyimides, silica gel or epoxy
One of materials such as resin are a variety of.
The seed layer 123 is formed as an example, can use but be not limited only to sputtering technology；The seed layer 123
Material may include one of Ti (titanium) and Cu (copper) or a variety of；Specifically, the seed layer 123 can be titanium layer, it can also
Think layers of copper, or the laminated construction of titanium layer and layers of copper can also be CTB alloy layer.
As an example, the material of the dielectric layer 124 may include low k dielectric.As an example, the dielectric layer
124 can use one of epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass or a variety of,
According to the difference of specific material, the dielectric layer 124 can be formed using techniques such as spin coating, CVD, plasma enhanced CVDs.
As an example, the metal line layer may include single metal layer, it also may include two or more layers metal layer.Make
For example, the material of the material of the metal line layer and the metal plug may include copper, aluminium, nickel, gold, silver, one in titanium
Kind is a variety of.
In step 3), S3 step and Fig. 6 in Fig. 1 are please referred to, the upper surface of Yu Suoshu re-wiring layer 12 forms electricity
Connection structure 13, the electric connection structure 13 are electrically connected with the re-wiring layer 12.
As an example, institute can be formed in the upper surface of the re-wiring layer 12 using routing technique or column bonding technology
State electric connection structure 13；The electric connection structure 13 may include bonding wire or conductive column.
As an example, the quantity of the electric connection structure 13 can be set according to actual needs, only with signal in Fig. 6
Four electric connection structures 13 are as an example, in actual example out, the quantity of the electric connection structure 13 not as
Limit.
In step 4), the S4 step and Fig. 7 to Fig. 8 in Fig. 1, the upper surface shape of Yu Suoshu re-wiring layer 12 are please referred to
At plastic packaging layer 14, the plastic packaging layer 14 is by 13 plastic packaging of electric connection structure.
As an example, molded underfill technique, coining moulding technology, transfer modling work can be used but is not limited only to
The upper surface that skill, hydraulic seal plastic package process, vacuum lamination process or spin coating proceeding are equal to the re-wiring layer 12 forms institute
State plastic packaging layer 14；Preferably, in the present embodiment, using molded underfill technique in the upper surface shape of the re-wiring layer 12
At the plastic packaging layer 14.The plastic packaging layer 14 is formed using molded underfill technique, the plastic packaging layer 14 can be smooth and fast
The gap between the electric connection structure 13 is filled up fastly, it is possible to prevente effectively from there is interface debonding；And molded underfill work
Skill will not be restricted as capillary underfill technique in the prior art, greatly reduced technology difficulty, be can be used for
Smaller joint gap, is more suitable for stacked structure.
As an example, the material of the plastic packaging layer 14 may include but be not limited only to polymer-based material, resin-based materials,
One of polyimides, silica gel or epoxy resin etc. are a variety of.
As an example, the upper surface for the plastic packaging layer 14 being initially formed can be higher than the top of the electric connection structure 13
Portion is also needed to execute the plastic packaging layer 14 is carried out thinned work as shown in fig. 7, at this point, after forming the plastic packaging layer 14
Skill, specifically, can use but be not limited only to chemical mechanical milling tech the plastic packaging layer 14 is carried out it is thinned so that retain
The top flush of the upper surface of the plastic packaging layer 14 and the electric connection structure 13, as shown in Figure 8.Certainly, in other examples
In, top flush of the upper surface for the plastic packaging layer 14 being initially formed i.e. with the electric connection structure 13, as shown in figure 8,
Thinned technique is carried out to the plastic packaging layer 14 at this point, can then save.
Certainly, in other examples, the plastic packaging layer 14 can also be initially formed and form through-hole in the plastic packaging layer 14,
The through-hole exposes the metal conducting layer 125 of the re-wiring layer 12, fills metal in through-hole later to be formed
The electric connection structure 13 does not do considered critical in the present embodiment.This mode is compared to being initially formed the electric connection structure 13
The benefit for carrying out the mode of plastic packaging again be can collapse to avoid the electric connection structure 13 and/or subsequent plastic packaging during to described
Electric connection structure 13 causes the problems such as damage, improves the performance of the semiconductor package.
In step 5), S5 step and Fig. 9 in Fig. 1 are please referred to, the upper surface of Yu Suoshu plastic packaging layer 14 is formed first day
Line layer 15, the first antenna layer 15 are electrically connected with the electric connection structure 13, and the first antenna layer 15 includes at least one
First antenna 151.
As an example, forming the first antenna layer 15 in the upper surface of the plastic packaging layer 14 may include steps of:
5-1) upper surface of Yu Suoshu plastic packaging layer 14 forms first antenna metal layer (not shown)；
5-2) perform etching to the first antenna metal layer includes multiple first antennas being intervally arranged to obtain
The 151 first antenna layer 15；The i.e. described first antenna layer 15 may include several described first antennas 151, Duo Gesuo
Stating first antenna 151 can be arranged with uniform intervals, can enhance gain and the beam angle of the first antenna layer 15；Certainly at it
First antenna 151 described in his example can be (for example, annular in shape point in arbitrary shape arrangement in the upper surface of the plastic packaging layer 14
Cloth etc.).The quantity of the first antenna 151 of the first antenna layer 15 can be set according to actual needs, in Fig. 9
It only include four first antennas 151 as an example, in actual example with the first antenna layer 15, the first antenna
The quantity of the first antenna 151 is not limited thereto in layer 15.
In another example, groove, the first antenna layer 15 can also be formed in the upper surface of the plastic packaging layer 14
Be formed in the groove, obtained structure is as shown in Figure 10, and the upper surface of the preferably described first antenna layer 15 with it is described
The upper surface flush of plastic packaging layer 14.When the first antenna 151 of the first antenna layer 15 is multiple, multiple described the
One antenna 151 is spaced by the plastic packaging layer 14, can form good protection to the first antenna 151.
As an example, can be formed using electroplating technology, physical gas-phase deposition or chemical vapor deposition process described
First antenna layer 15；The material of the first antenna layer 15 can include but are not limited at least one of copper, aluminium and silver.
As an example, the shape of the first antenna 151 may include but be not limited only to blocky or helical form etc..
In step 6), S6 step and Figure 11 in Fig. 1 are please referred to, the upper surface of Yu Suoshu plastic packaging layer 14 forms frame knot
Structure 16, the frame structure 16 are located at the periphery of the first antenna layer 15.
As an example, the frame structure 16 includes resinous framework structure, metal framework structure or ceramic frame configuration；It is excellent
Metal framework structure is selected, can avoid external environment to the electromagnetic interference of the first antenna layer 15.
As an example, the frame structure 16 can surround 15 surrounding of first antenna layer, and the frame structure 16
There is spacing between the first antenna layer 15.
As an example, the frame structure 16 can be bonded to the upper surface of the plastic packaging layer 14 using bonding technology.
In step 7), S7 step and Figure 12 in Fig. 1 are please referred to, lens substrate 17a, the lens substrate 17a are provided
A surface be formed with the second antenna stack 18, second antenna stack 18 includes at least one second antenna 181；By the lens
Substrate 17a is bonded to the top of the frame structure 16, and second antenna stack 18 is located at the lens substrate 17a's after bonding
Lower surface, and second antenna stack 18 and the first antenna layer 15 have spacing.
As an example, the lens substrate 17a is by the regional seal in the frame structure 16, after step 7) to be formed
Air chamber 20, the first antenna layer 15 and second antenna stack 18 are respectively positioned in the air chamber 20.
The preferred non-optical glass substrate of lens substrate 17a, such as quartz glass, it is possible to reduce the radiation loss of antenna,
Improve antenna performance.
Include the following steps: as an example, forming second antenna stack 18 in a surface of the lens substrate 17a
The second antenna metal layer (not shown) is formed in a surface of the lens substrate 17a；
Perform etching to the second antenna metal layer includes described in multiple the second antennas 181 being intervally arranged to obtain
Second antenna stack 18；I.e. described second antenna stack 18 may include several second antennas 181, several described second antennas
181 can arrange (for example, being arranged in array) in the lower surface of the frame structure 16 in arbitrary shape, and adjacent described second
There is spacing between antenna 181.The quantity of second antenna 181 of second antenna stack 18 can according to actual needs into
Row setting only with second antenna stack 18 includes four second antennas 181 as an example, in actual example in Figure 12
In, the quantity of second antenna 181 of second antenna stack 18 is not limited thereto.Second antenna stack 18 it is described
Number of quantity, shape and the arrangement mode of second antenna 181 preferably with the first antenna 151 of the first antenna layer 15
Amount, shape and arrangement mode is just the same and the first antenna 151 and about 181 second antenna one-to-one correspondence, favorably
In improving antenna gain, increase the beam angle of antenna.
Certainly, in other examples, multiple ditches being spaced apart can also be formed in the surface of the lens substrate 17a
Slot, the interior filling metal of Yu Suoshu groove form second antenna stack 18, i.e., described second antenna stack 18 is formed in the lens
In the groove of the substrate 17a and preferred surface of second antenna stack 18 and the surface flush of the lens substrate 17a, thus
Good protection can be formed to second antenna stack 18, while be conducive to the focusing of the radiated wave of second antenna stack 18,
Be conducive to improve antenna performance.(first antenna layer described in Figure 13 15 is located at institute to the structure obtained according to this method as shown in figure 13
It states in plastic packaging layer 14).
As an example, the material of second antenna 181 may include but be not limited only in copper, aluminium and silver at least one
Kind.
In step S8), S8 step and Figure 14 in Fig. 1 are please referred to, the lens substrate 17a is performed etching to be formed
Lens jacket 17, the lens jacket 17 include at least one lens 171, and the lens 171 and about 181 second antenna are right
It answers；The lens 171 are preferably several and the more preferably lens 171 and the first antenna 151 and second antenna
181 be that the multiple and described first antenna 151, second antenna 181 and the lens 171 correspond in the longitudinal direction, institute
Stating lens 171 is preferably convex lens, can be focused to the radiated wave of antenna to improve antenna gain, and the first antenna
151, second antenna 181 and the lens 171 be it is multiple beam angle can be improved so that the semiconductor packages of the application
The performance of structure is obviously improved.Certainly, in other examples, according to different needs, the lens 171 can be concavees lens,
Not stringent limitation in the present embodiment.
As an example, partial etching is only carried out to form the lens 171 to the lens substrate 17a in the present embodiment,
The part not etched becomes the planar portions 172 of the lens jacket 17, and the planar portions 172 are located at the top of the frame structure 16
And the lens 171 are located at the surface of the planar portions 172, thus the planar portions 172 and the lens 171 be it is integrated,
Such integral structure advantageously reduces the radiation loss of antenna, improves antenna performance.The thickness of the lens substrate 17a and quarter
Depth is lost depending on the focal length of the lens 171, and second antenna 181 of preferably described second antenna stack 18 is away from the lens
The distance (i.e. object distance) of 171 optical centers is greater than twice of the focal length of the lens 171, with utmostly focusing anteena radiated wave, mentions
High antenna gain.
It should be noted that the lens jacket 17 can also be by large-scale production and preparation without in each packaging technology
It independently forms the lens jacket 17 in the process, and forms the lens 171 and form described the on the surface of the lens jacket 17
There is no stringent precedence relationships for both two antenna stacks 18, for example first can form described the on the surface the lens substrate 17a
Two antenna stacks 18 later perform etching the lens substrate 17a according to second antenna stack 18 to form the lens 171,
The lens 171 can also be corresponded to again after forming the lens 171 and form second antenna stack 18, in the present embodiment not
Considered critical.It is preferred that the latter, that is, be initially formed the lens 171 and re-form second antenna stack 18, to reduce described second day
Line layer 18 is exposed to the outer time, it is ensured that the performance of second antenna stack 18, while avoiding being initially formed second antenna
Layer 18 etch in the technical process to form the lens 171 again may to damage caused by second antenna stack 18 (than if any
May cause falling off for second antenna stack 18), it is ensured that device performance.
In step 9), S9 step and Figure 15 in Fig. 1 are please referred to, removes the substrate 10 and the sacrificial layer 11.
As an example, the sacrificial layer 11 can be removed while removing substrate 10.
As an example, using grinding technics, reduction process or the technique removal sacrificial layer 11 and the base can be removed
Bottom 10；Preferably, in the present embodiment, the substrate 10 is removed by the way of removing the sacrificial layer 11.
As an example, further including following steps after step 9): forming opening 126, institute in Yu Suoshu re-wiring layer 12
Opening 126 is stated through the bottom dielectric layer 121 and the capsulation material layer 122 to expose the seed layer 123, such as Figure 16
It is shown.Specifically, the lower surface that can use lithographic etch process from the re-wiring layer 12 performs etching described in formation
Opening 126.
In step 10), S10 step and Figure 17 in Fig. 1 are please referred to, chip 21 is provided, the chip 21 is bonded to
The lower surface of the re-wiring layer 12, the chip 21 is realized with the re-wiring layer 12 to be electrically connected.
As an example, the chip 21 can be any one functional chip, device could be formed in the chip 21
Structure (not shown), the surface of the chip 21 could be formed with connection weld pad (not shown), the connection weld pad and the device
The electrical connection of part structure.
As an example, the device architecture in the chip 21 may include active component and passive element.
As an example, the chip 21 can be bonded to the rewiring using any one existing bonding technology
The lower surface of layer 12；The connection weld pad of the chip 21 is via the part opening and the institute in the re-wiring layer 12
State the electrical connection of metal conducting layer 125.
As an example, further including in the core after the chip 21 to be bonded to the lower surface of the re-wiring layer 12
The step of Underfill layer 22 are formed between piece 21 and the re-wiring layer 12；Specifically, it can use but be not limited only to spray
Black technique, gluing process, compressing and forming process, Transfer molding technique, fluid-tight moulding process, vacuum lamination process or spin coating
At least one of technique forms the Underfill layer 22；The material of the Underfill layer 22 may include but be not limited only to
At least one of polyimides, silica gel and epoxy resin.The Underfill layer 22 can be enhanced the chip 21 with it is described
The bond strength of re-wiring layer 12, and protect the re-wiring layer 12.
In step 11), the S11 step and Figure 18 and Figure 19 in Fig. 1, the following table of Yu Suoshu re-wiring layer 12 are please referred to
Face forms soldered ball convex block 19, and the soldered ball convex block 19 is electrically connected with the re-wiring layer 12.
As an example, the soldered ball convex block 19 is located in the opening 126 of 21 periphery of chip, the soldered ball convex block
19 are in contact with the seed layer 123.
As an example, the material of the soldered ball convex block 19 may include at least one of copper and tin.
Certainly, above-mentioned process sequence is only illustrative, and can be adjusted according to different needs, such as in other examples
In, the surface that the chip 21 is bonded to the re-wiring layer 12 first can also be sequentially formed into other structures, this implementation again
Not considered critical in example.And as needed, antenna stack can also be 3 layers or more, to further increase antenna performance.
The semiconductor package of the preparation method preparation of semiconductor package of the invention passes through will be described
Mirror layer 17, about 21 plastic packaging of first antenna layer 15, second antenna stack 18 and the chip can be effectively reduced and described partly be led
The volume of body encapsulating structure improves the integrated level of device；It is described by the way that the active component and the passive element to be integrated in
In chip 21, the volume of the encapsulating structure can be further decreased, further increases the integrated level of device；Pass through lens jacket
Lens are focused the radiated wave of antenna, can effectively improve antenna gain；The first antenna layer 15 and second antenna
Only has air insulated between layer 18, the dielectric loss of air is minimum, can reduce the first antenna layer 15 and described second day
The loss of signal of line layer 18, and transmission signal path is shorter in semiconductor package of the invention, available better electricity
Property and antenna performance.Using preparation method of the invention, it is remarkably improved the performance of the semiconductor package of preparation, and advantageous
In reduction production cost.
Embodiment two
Incorporated by reference to Fig. 2 to Figure 17 with continued reference to 18 and Figure 19, the present invention also provides a kind of semiconductor package, described half
Conductor package structure can be prepared according to the preparation method of embodiment one, therefore completely suitable to the explanation of dependency structure in embodiment one
For the present embodiment.
As shown in figure 18, the semiconductor package includes: re-wiring layer 12；Chip 21, the chip 21 are bonded
In the lower surface of the re-wiring layer 12, and the chip 21 is electrically connected with the re-wiring layer 12；Electric connection structure 13,
The electric connection structure 13 is located at the upper surface of the re-wiring layer 12, and the electric connection structure 13 and the rewiring
Layer 12 is electrically connected；Plastic packaging layer 14, the plastic packaging layer 14 is located at the upper surface of the re-wiring layer 12, and the plastic packaging layer 14 will
13 plastic packaging of electric connection structure；First antenna layer 15, the first antenna layer 15 are located at the upper surface of the plastic packaging layer 14, and
The first antenna layer 15 is electrically connected with the electric connection structure 13, and the first antenna layer 15 includes at least one first antenna
151；Frame structure 16, the frame structure 16 is located at the upper surface of the plastic packaging layer 14, and the frame structure 16 is located at institute
State the periphery of first antenna layer 15；Lens jacket 17, positioned at the top of the frame structure 16, the lens jacket 17 includes at least one
A lens 171；Second antenna stack 18, second antenna stack 18 are located at the lower surface of the lens jacket 17, and described second day
Line layer 18 and the first antenna layer 15 have spacing, and second antenna stack 18 includes at least one second antenna 181 and institute
The lens 171 for stating the second antenna 181 and the lens jacket 17 are correspondingly arranged；Soldered ball convex block 19, the soldered ball convex block 19 are located at institute
The lower surface of re-wiring layer 12 is stated, and the soldered ball convex block 19 is electrically connected with the re-wiring layer 12.Of the invention partly leads
Body encapsulating structure is by that can effectively reduce encapsulation knot for plastic packaging above and below lens jacket, first antenna layer, the second antenna stack and chip
The volume of structure improves the integrated level of device；The radiated wave of antenna is focused by the lens of lens jacket, day can be effectively improved
Line gain；Only has air insulated between first antenna layer and the second antenna stack, the dielectric loss of air is minimum, can reduce by first
The loss of signal of antenna stack and the second antenna stack, and transmission signal path is shorter in semiconductor package of the invention, can be with
Obtain better electrical property and antenna performance.
As an example, the re-wiring layer 12 may include: dielectric layer 124, positioned at the upper surface of the sacrificial layer 11；
Metal conducting layer 125, the metal conducting layer 125 are located in the dielectric layer 124, and the metal conducting layer 125 includes multilayer
The metal line layer (not indicating) and metal plug (not indicating) being intervally arranged, the metal plug are located at the adjacent metal
Between line layer, the adjacent metal line layer is electrically connected.
As an example, the material of the dielectric layer 124 may include low k dielectric.Specifically, the dielectric layer 124
Material may include one of using epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass
Material；The dielectric layer 124 can be formed using techniques such as spin coating, CVD, plasma enhanced CVDs.
As an example, the re-wiring layer 12 can also include: seed layer 123, the seed layer 123, which is located at, to be given an account of
In matter layer 124, and the seed layer 123 is electrically connected with the metal conducting layer 125；Capsulation material layer 122, the capsulation material
Layer 122 is located in the dielectric layer 124, and is located at the lower surface of the seed layer 123；The dielectric layer 124 coats the modeling
123 bottom dielectric layer 121 of closure material layer 122 and the seed layer, the bottom dielectric layer 121 are located at the dielectric layer 124
Lower surface.
As an example, the material of the bottom dielectric layer 121 may include low k dielectric.Specifically, the bottom is situated between
121 material of electric layer may include using in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass
It is one or more；According to the difference of material, the bottom dielectric layer 121 can be using spin coating, CVD, plasma enhanced CVD etc.
Technique is formed.
As an example, the material of the capsulation material layer 122 may include but be not limited only to polyimides, silica gel or epoxy
One of materials such as resin are a variety of.
The seed layer 123 is formed as an example, can use but be not limited only to sputtering technology；The seed layer 123
Material may include at least one of Ti (titanium) and Cu (copper)；Specifically, the seed layer 123 can be titanium layer, it can also be with
For layers of copper, or the laminated construction of titanium layer and layers of copper can also be CTB alloy layer.
As an example, the material of the dielectric layer 124 may include low k dielectric.As an example, the dielectric layer
124 can use one of epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass or a variety of,
And the dielectric layer 124 can be formed using techniques such as spin coating, CVD, plasma enhanced CVDs.
As an example, the metal line layer may include single metal layer, it also may include two or more layers metal layer.Make
For example, the material of the material of the metal line layer and the metal plug may include copper, aluminium, nickel, gold, silver, one in titanium
Kind material or two or more combined materials.
As an example, the chip 21 can be any one functional chip, device could be formed in the chip 21
Structure (not shown), the surface of the chip 21 could be formed with connection weld pad (not shown), the connection weld pad and the device
The electrical connection of part structure.
As an example, the device architecture in the chip 21 may include active component and passive element.
As an example, the chip 21 can be bonded to the rewiring using any one existing bonding technology
The lower surface of layer 12；The connection weld pad and the metal conducting layer 125 in the re-wiring layer 12 of the chip 21
Electrical connection.
As an example, the electric connection structure 13 may include bonding wire or conductive column.
As an example, the quantity of the electric connection structure 13 can be set according to actual needs, only to show in Figure 18
Four electric connection structures 13 anticipate out as an example, in actual example, the quantity of the electric connection structure 13 is not with this
It is limited.
As an example, the material of the plastic packaging layer 14 may include but be not limited only to polymer-based material, resin-based materials,
One of polyimides, silica gel or epoxy resin etc. are a variety of.
As an example, the top flush of the upper surface of the plastic packaging layer 14 and the electric connection structure 13.
As an example, the first antenna layer 15 includes several first antennas 151；Several described first antennas 151
In the upper surface of the plastic packaging layer 14 in arbitrary shape arrangement (for example, several described first antennas 151 be evenly spaced on and
It is arranged in array, is conducive to increase antenna beamwidth), and there is spacing between the adjacent first antenna 151.Described first
The quantity of the first antenna 151 of antenna stack 15 can be set according to actual needs, only with described first day in Figure 15
Line layer 15 includes four first antennas 151 as an example, in actual example, and described the first of the first antenna layer 15
The quantity of antenna 151 is not limited thereto.
As an example, can be formed using electroplating technology, physical gas-phase deposition or chemical vapor deposition process described
First antenna layer 15；The material of the first antenna layer 15 can include but are not limited at least one of copper, aluminium and silver.
As an example, the frame structure 16 includes resinous framework structure, metal framework structure or ceramic frame configuration, it is excellent
Select metal framework, it is possible to reduce outside electromagnetic interference.
As an example, the frame structure 16 can surround 15 surrounding of first antenna layer, and the frame structure 16
There is spacing between the first antenna layer 15.
As an example, the frame structure 16 can be bonded to the upper surface of the plastic packaging layer 14 using bonding technology.
The lens jacket 17 is by the regional seal in the frame structure 17, to form air chamber 20, the first antenna
Layer 15 and second antenna 18 are respectively positioned in the air chamber 20.
As an example, the preferred optical glass of material of the lens jacket 17, such as quartz glass, the lens 171 are preferably
For convex lens, the focusing to aerial radiation wave may be implemented, improve antenna gain.
As an example, the lens jacket 17 further includes planar portions 172, the planar portions 172 are located at the frame structure 16
Top, the lens 171 are located at the upper surface of the planar portions 172, and the planar portions 172 and the lens 171 are preferably
Integral structure, it is possible to reduce the radiation loss of antenna improves antenna gain.
As an example, second antenna stack 18 may include several second antennas 181, several described second antennas
181 in the frame structure 16 be in arbitrary shape arrangement (for example, several described second antennas 181 be evenly spaced on and
It is arranged in array, is conducive to increase antenna beamwidth), and there is spacing between adjacent second antenna 181.Described second
The quantity of second antenna 181 of antenna stack 18 can be set according to actual needs, only with described second day in Figure 11
Line layer 18 includes four second antennas 181 as an example, in actual example, and described the second of second antenna stack 18
The quantity of antenna 181 is not limited thereto.
As an example, the quantity of the first antenna 151, second antenna 181 and the lens 171 be it is multiple,
For example be 2 or 2 or more, three's quantity is preferably identical and the first antenna 151, second antenna 181 and described
Be arranged in a one-to-one correspondence on 171 longitudinal direction of mirror and the projected area of the lens 171 not less than second antenna 181 surface area with
Ensure that the lens 171 focus the radiated wave of second antenna 181 comprehensively, help to improve antenna gain, increases
Antenna beamwidth.
As an example, the material of second antenna 181 may include but be not limited only in copper, aluminium and silver at least one
Kind.
As an example, the material of the soldered ball convex block 19 may include at least one of copper and tin.
As shown in figure 19, in another example, the upper surface of the plastic packaging layer 14 is formed with groove (not shown), and described
One antenna stack 15 is formed in the groove of the plastic packaging layer 14, and the upper surface of the preferably first antenna layer 15 and the plastic packaging
The upper surface flush of layer 14, includes the case where multiple first antennas 151 being spaced apart in the first antenna layer 15
Under, the interval between the first antenna 151 is filled good to be formed to the first antenna layer 15 by the plastic packaging layer 14
Protection improves antenna performance, while being conducive to miniaturising for device.Certainly, in other examples, second antenna
Layer 18, which can also be formed in the lens jacket 17, (is formed with groove, 18 shape of the second antenna stack in the i.e. described lens jacket 17
At in the groove of the lens jacket 17) and the surface of second antenna stack 18 and the lens jacket 17 surface flush,
Not considered critical in the present embodiment.
In conclusion the present invention provides a kind of semiconductor package and preparation method thereof, the semiconductor package
It include: re-wiring layer；Chip is bonded to the lower surface of the re-wiring layer, and is electrically connected with the re-wiring layer；Electricity
Connection structure is electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；Plastic packaging layer is located at described
The upper surface of re-wiring layer, and by the electric connection structure plastic packaging；First antenna layer, positioned at the upper surface of the plastic packaging layer,
And be electrically connected with the electric connection structure, the first antenna layer includes at least one first antenna；Frame structure is located at described
The upper surface of plastic packaging layer, and it is located at the periphery of the first antenna layer；Lens jacket, it is described positioned at the top of the frame structure
Lens jacket includes at least one lens；Second antenna stack has positioned at the lower surface of the lens jacket, and with the first antenna layer
There is spacing, second antenna stack includes at least one second antenna and second antenna is corresponding with the lens of the lens jacket
Setting；Soldered ball convex block is electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer.Of the invention half
Conductor package structure is by that can effectively reduce encapsulation for plastic packaging above and below lens jacket, first antenna layer, the second antenna stack and chip
The volume of structure improves the integrated level of device；The radiated wave of antenna is focused by the lens of lens jacket, can be effectively improved
Antenna gain；Only has air insulated between first antenna layer and the second antenna stack, the dielectric loss of air is minimum, can reduce by the
The loss of signal of one antenna stack and the second antenna stack, and transmission signal path is shorter in semiconductor package of the invention, it can
To obtain better electrical property and antenna performance.
The principle of the present invention and its effect is only illustrated in above embodiment, and is not intended to limit the present invention.It is any
Those skilled in the art all without departing from the spirit and scope of the present invention, modifies above embodiment or is changed
Become.Therefore, such as those of ordinary skill in the art without departing from disclosed spirit and technical idea
Lower completed all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (10)
1. a kind of semiconductor package, which is characterized in that the semiconductor package includes:
Re-wiring layer；
Chip is bonded to the lower surface of the re-wiring layer, and is electrically connected with the re-wiring layer；
Electric connection structure is electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；
Plastic packaging layer, positioned at the upper surface of the re-wiring layer, and by the electric connection structure plastic packaging；
First antenna layer is electrically connected positioned at the upper surface of the plastic packaging layer, and with the electric connection structure, the first antenna layer
Including at least one first antenna；
Frame structure positioned at the upper surface of the plastic packaging layer, and is located at the periphery of the first antenna layer；
Lens jacket, positioned at the top of the frame structure, the lens jacket includes at least one lens；
Second antenna stack has spacing, second antenna positioned at the lower surface of the lens jacket, and with the first antenna layer
Layer is correspondingly arranged including the lens of at least one second antenna and second antenna and the lens jacket；
Soldered ball convex block is electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer.
2. semiconductor package according to claim 1, it is characterised in that: the first antenna, second antenna
Quantity with the lens is that the multiple and described first antenna, second antenna and the lens correspond.
3. semiconductor package according to claim 1, it is characterised in that: the frame structure includes resinous framework knot
Structure, metal framework structure or ceramic frame configuration.
4. semiconductor package according to claim 1, it is characterised in that: the semiconductor package further includes bottom
Portion's filled layer, the Underfill layer is between the chip and the re-wiring layer.
5. semiconductor package according to any one of claim 1 to 4, it is characterised in that: the lens are convex lens
Mirror, the lens jacket further include planar portions, and the planar portions are located at the top of the frame structure, and the convex lens is located at described
The upper surface of planar portions.
6. a kind of preparation method of semiconductor package, which is characterized in that the preparation method packet of the semiconductor package
Include following steps:
Substrate is provided, the upper surface of Yu Suoshu substrate forms sacrificial layer；
Re-wiring layer is formed in the upper surface of the sacrificial layer；
Electric connection structure is formed in the upper surface of the re-wiring layer, the electric connection structure is electrically connected with the re-wiring layer
It connects；
Plastic packaging layer is formed in the upper surface of the re-wiring layer, the plastic packaging layer is by the electric connection structure plastic packaging；
First antenna layer is formed in the upper surface of the plastic packaging layer, the first antenna layer is electrically connected with the electric connection structure,
The first antenna layer includes at least one first antenna；
Frame structure is formed in the upper surface of the plastic packaging layer, the frame structure is located at the periphery of the first antenna layer；
Lens substrate is provided, a surface of the lens substrate is formed with the second antenna stack, and second antenna stack includes at least
One the second antenna；The lens substrate is bonded to the top of the frame structure, second antenna stack is located at after bonding
The lower surface of the lens substrate, and there is spacing with the first antenna layer；
The lens substrate is performed etching to form lens jacket, the lens jacket includes at least one lens, the lens with
Second antenna is corresponding up and down；
Remove the substrate and the sacrificial layer；
Chip is provided, by the chip bonding in the lower surface of the re-wiring layer, the chip and the re-wiring layer
Electrical connection；
Soldered ball convex block is formed in the lower surface of the re-wiring layer, the soldered ball convex block is electrically connected with the re-wiring layer.
7. the preparation method of semiconductor package according to claim 6, it is characterised in that: the frame knot of formation
Structure includes resinous framework structure, metal framework structure or ceramic frame configuration；The lens of the lens jacket are convex lens.
8. the preparation method of semiconductor package according to claim 6, which is characterized in that
The first antenna layer is formed in the upper surface of the plastic packaging layer to include the following steps:
First antenna metal layer is formed in the upper surface of the plastic packaging layer；
Perform etching to the first antenna metal layer includes described the of multiple first antennas being intervally arranged to obtain
One antenna stack；
Second antenna stack is formed in a surface of the lens substrate to include the following steps:
The second antenna metal layer is formed in a surface of the lens substrate；
Perform etching to the second antenna metal layer includes described the of multiple second antennas being intervally arranged to obtain
Two antenna stacks；
The first antenna is correspondingly arranged up and down one by one with second antenna.
9. the preparation method of semiconductor package according to claim 6, it is characterised in that: by the chip bonding in
It further include forming Underfill layer between the chip and the re-wiring layer after the lower surface of the re-wiring layer
The step of.
10. according to the preparation method of the described in any item semiconductor packages of claim 6 to 9, it is characterised in that: described
Mirror layer includes planar portions and the lens positioned at the planar portions surface, and the planar portions are located at the top of the frame structure, institute
It states lens and the first antenna and second antenna is the multiple and described first antenna, second antenna and described
Mirror corresponds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910482090.5A CN110112110A (en) | 2019-06-04 | 2019-06-04 | Semiconductor package and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910482090.5A CN110112110A (en) | 2019-06-04 | 2019-06-04 | Semiconductor package and preparation method thereof |
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| CN110112110A true CN110112110A (en) | 2019-08-09 |
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| CN201910482090.5A Pending CN110112110A (en) | 2019-06-04 | 2019-06-04 | Semiconductor package and preparation method thereof |
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Cited By (1)
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|---|---|---|---|---|
| CN113113766A (en) * | 2019-12-25 | 2021-07-13 | 盛合晶微半导体(江阴)有限公司 | Lens antenna packaging structure, preparation method and electronic equipment |
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| CN108417559A (en) * | 2017-02-08 | 2018-08-17 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation device and its manufacturing method |
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| CN113113766B (en) * | 2019-12-25 | 2024-04-26 | 盛合晶微半导体(江阴)有限公司 | Lens antenna packaging structure, manufacturing method and electronic equipment |
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