CN110110355A

CN110110355A - A kind of Prototype Verification Platform based on FPGA

Info

Publication number: CN110110355A
Application number: CN201910225854.2A
Authority: CN
Inventors: 王忆文; 郭少成
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2019-03-25
Filing date: 2019-03-25
Publication date: 2019-08-09

Abstract

The invention belongs to SoC chip verification technique field, specially a kind of Prototype Verification Platform device based on FPGA.FPGA is existing frequently-used Design of Digital System platform, and maximum advantage is that FPGA can not have to change hardware circuit, carries out dynamic configuration to fpga chip using software by user completely, realize specific function, and can repeat erasable use.Using FPGA as the hardware platform of Digital Design, user can combine hardware design and software design, the mistake in design can timely be modified, it is compared to the trial and error cost that ASIC design is greatly reduced chip design, the flexibility of design is provided, to greatly shorten the design cycle.Using FPGA as the hardware carrier of MC-SoC system, can achieve with the comparable operating rate of actual chips, greatly improve simulation velocity, the speed shortcomings of simple software emulation work can be made up, designer is helped find to design mistake present in circuit as early as possible.

Description

A kind of Prototype Verification Platform based on FPGA

Technical field

The invention belongs to SoC chip verification technique field, specially a kind of Prototype Verification Platform device based on FPGA.

Background technique

In the design process of SoC chip, for the coverage rate of raising chip checking as big as possible, it is necessary to using a variety of The mode that verifying means combine.Wherein, it is designed as a kind of important verifying means in chip based on the prototype verification of FPGA Functional verification in play very important effect.

Based on pure software and Dynamic Simulation Technology and formal verification technology there are its intrinsic limitation, this has just been determined The mistake of some chip designs will not be found by dynamic functional simulation, because the speed of emulation cannot work with actual chips Speed mention in the same breath, as soon as and the operating rate of FPGA system can be similar with true chip system, therefore It is possible that find some simple emulation not detectable chip design mistake.

SoC chip designs compared with legacy chip designs, and design scale becomes larger, and traditional chip design is often only wrapped The design of hardware circuit containing chip, and the design of a SoC chip not only includes the design of hardware circuit, but also includes very The work of the software design of big specific gravity, it is therefore desirable to the design of SoC system support software will be carried out simultaneously in the design process And verified, so needing to carry out software-hardware co-designing.Software-hardware co-designing is very crucial in SoC verifying process A link, the software-hardware co-designing for only having passed through SoC just can guarantee the matched software of design on SoC hardware platform It works normally.

Summary of the invention

The purpose of the present invention is to provide a kind of SoC chip Prototype Verification Platform based on FPGA, the verification platform include Hardware components and software section can carry out software-hardware co-designing to SoC chip,

The hardware components of verification platform include FPGA prototype verification development board, Vivado software, Xilinx in the present invention FPGA downloader hardware device relevant with other.

In hardware components, the RTL design of SoC chip carries out logic synthesis, a system such as placement-and-routing in Vivado software Column process, and ultimately generate bit stream file, then by the JTAG download interface on FPGA plate by the bit stream file of generation FPGA is downloaded to, by SoC system configuration into fpga chip.

The software section of verification platform includes Keil software and ULink emulator in the present invention, and wherein Keil is for compiling Assembler and C language test program, ULink emulator are used to connect the Keil software and FPGA witness plate at the end PC.

The workflow of software section is about, by the assembler write and C test program by compiling in Keil The sequence of operations such as link obtain the binary file that chip core can be read, and download to SoC core by ULink emulator In piece.

SoC chip Prototype Verification Platform provided by the invention can make up the deficiency of software analog simulation, when reducing verifying Between, examine whether the design of SoC realizes the function that design specification determines, so as to improve the flow success rate of SoC chip.

Detailed description of the invention

Fig. 1 is the architecture diagram of Prototype Verification Platform of the invention；

Fig. 2 is Prototype Verification Platform work overview flow chart；

Fig. 3 is the specific work step of Prototype Verification Platform hardware components of the invention；

Fig. 4 is the specific work step of Prototype Verification Platform software section of the invention；

Specific embodiment

Method of the invention is described further below in conjunction with attached drawing:

Fig. 1 show the general frame figure for the Prototype Verification Platform based on FPGA that the present invention designs, wherein mainly including Following two part.

At the end PC, it is mounted with Keil software, Vivado software and AccessPort software, passes through ULink emulator respectively, Xilinx downloading wire and UART turn USB line and are connected with FPGA witness plate.

At FPGA witness plate end, main includes that the fpga chip of an Xilinx Kintex-7 series and JTAG downloading connect Mouthful, the hardware adaptors such as UART interface.

It is the groundwork process of Prototype Verification Platform of the invention shown in Fig. 2, specifically includes that

The RTL code of SoC design to be verified is passed through into logic synthesis in Vivado, the generation of the processes such as placement-and-routing can The bit stream file for configuring FPGA, SoC design is realized in FPGA.

Then the assembler write and C language test program are passed through to the processes such as compiling link in Keil software, it is raw At can be by the binary file or hex file of the memory reading in SoC system.

After SoC system reads in the test program of binary format and execution, debugging letter is printed by using UART module The waveform of breath or crawl signal, judges whether system correctly executes the instruction in c program.

It is the specific work steps of Prototype Verification Platform hardware components of the invention shown in Fig. 3:

1) RTL design of SoC chip to be verified is converted to the RTL design that can be realized in FPGA, mainly includes Clock resets, memory and IO Pad.

2) corresponding temporal constraint and pin constraint are write.Temporal constraint is similar with the temporal constraint in ASIC design, Final purpose is provided to guarantee that there is no setup/hold to break rules in design.Pin constraint is called physical constraint, is used for SoC The pin in port assignment to FPGA development board in design.

3) logic synthesis and cloth then are carried out by the RTL code and unbound document reading Vivado software after modification Office's wiring operations, then will be generated to bit stream file programming into fpga chip.

It is the specific work steps of Prototype Verification Platform software section of the invention shown in Fig. 4:

Software section includes the starting code write using assembler language and the test for making the modules shown a C language Code.

Assembly code and C code are compiled respectively using different compilers first, then linked using armlink All program chains are image file by device, are then reflected the ELF that ARM linker generates by format converter fromelf As being converted to the binary system or hexadecimal format that suitable ROM is read, and they are loaded directly into memory.

The above described is only a preferred embodiment of the present invention, being not intended to limit the present invention in any form.Appoint What those skilled in the art, without departing from the scope of the technical proposal of the invention, all using the side of the disclosure above Method and technology contents make many possible changes and modifications to technical solution of the present invention, or are revised as the equivalent reality of equivalent variations Apply example.Therefore, anything that does not depart from the technical scheme of the invention according to the technical essence of the invention do above embodiments Any simple modifications, equivalents, and modifications, all of which are still within the scope of protection of the technical scheme of the invention.

Claims

1. a kind of Prototype Verification Platform based on FPGA, including FPGA witness plate (1), which is characterized in that the FPGA witness plate (1) JTAG download interface is connected with Xilinx downloader (2), the Xilinx downloader (2) and installation Vivado software (3) The USB interface at the end PC be connected, the JTAG of the FPGA witness plate (1) debugging port is connected with ULink emulator (4), described ULink emulator (4) is connected with the USB interface at the end PC of installation Keil software (5), the UART mould of the FPGA witness plate (1) Block pin turns USB connecting line (6) with UART and is connected, and the UART turns USB connecting line (6) and installs AccessPort software (7) The USB port at the end PC is connected.

2. a kind of Prototype Verification Platform based on FPGA as described in claim 1, which is characterized in that RTL form to be verified SoC design logic synthesis is carried out in the Vivado software (3), placement-and-routing generates the processes such as bit stream file, then It is downloaded in the FPGA witness plate (1) by the Xilinx downloader (2).

3. a kind of Prototype Verification Platform based on FPGA as described in claim 1, which is characterized in that the assembler write and For C test program by compiling in the Keil (4), the sequence of operations such as link obtain the binary system that chip core can be read Then file is downloaded in SoC chip by the ULink emulator (4).

4. a kind of Prototype Verification Platform based on FPGA as described in claim 1, which is characterized in that the ULink emulator (4) status information that can be run SoC system is transmitted to the debugging window of the Keil software (5) at the end PC.