CN101174283A - Software and hardware cooperating simulation platform based on network - Google Patents
Software and hardware cooperating simulation platform based on network Download PDFInfo
- Publication number
- CN101174283A CN101174283A CNA2007100506865A CN200710050686A CN101174283A CN 101174283 A CN101174283 A CN 101174283A CN A2007100506865 A CNA2007100506865 A CN A2007100506865A CN 200710050686 A CN200710050686 A CN 200710050686A CN 101174283 A CN101174283 A CN 101174283A
- Authority
- CN
- China
- Prior art keywords
- simulation
- hardware
- debugger
- user
- mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention discloses a method for realizing software and hardware co-simulation platform based on network, belonging to the technical field of SOC simulation and verification, which comprises a PC terminal for running the software part, a target board for simulating the hardware part, and a debugger for connecting the PC terminal and the target board mutually. The invention has the advantages that the simulation support to Vector mode and Co-simulation mode can be realized on a unitive multi-mode simulation system; the occupation on I/O resources is reduced greatly due to the communication between the debugger and the target board adopting serial-parallel conversion method; and the software part is communicated with the hardware part via Ethernet to support remote co-simulation.
Description
Technical field
The invention belongs to the functional simulation technical field of integrated circuit (IC) chip, particularly software and hardware cooperating simulation, verification technique.
Background technology
System on Chip/SoC (SOC) design is developing rapidly in recent years, it is except a large amount of hardware modules with respect to the maximum difference of ASIC, also comprise a large amount of software, as operating system, driver, communication protocol and various application programs etc., its design complexities is far above traditional integrated circuit (IC) chip.Therefore the emulation to the SOC chip also becomes very difficult,
Not only need system hardware is partly carried out emulation, also will carry out emulation, just will carry out software and hardware cooperating simulation software section.
The software and hardware cooperating simulation technology is that the SOC design of a complexity is divided according to the IP module, employing is based on the emulation technology of module, part or all module is downloaded on the FPGA (Field Programmable Gate Array) hardware, simulate its function with hardware circuit, this partial circuit is operated near real-time travelling speed, and the remaining design part still operates in the software simulator, replaces pure Computer Simulation by hardware platform, thereby improves the accuracy of SOC chip emulation widely.Collaborative simulation system is made up of a software execution environment and a hardware execution environment, by incident and order, uses synchronization mechanism, controls between these two environment, makes cooperative work of software and hardware, finishes the emulation of system jointly.
The software emulation module is moved on computers, adopts higher other modeling method of abstractdesription level, and can obtain the dirigibility of software emulation and debugging method easily.Simulation hardware module in the simulation hardware platform typically uses hardware description language (HDL) carry out the modeling of register transfer level (RTL) after, use electric design automation (EDA) instrument to carry out comprehensive then and placement-and-routing's processing, download on the simulation hardware platform and realize.The simulation hardware module is in the operation of simulation hardware platform, and the ardware feature of analogy model reaches the execution speed of hardware more exactly, and uses real interface and extraneous swap data.
In the various software and hardware cooperating simulation methods of signal level, if the input signal of system or module can not be subjected to the feedback influence of self output signal, this pattern is called test vector pattern (Vector mode), because input signal is not influenced by output signal, therefore can once apply the pumping signal vector of a plurality of time beats, simulation velocity is fast.If the input signal of system or module is subjected to the feedback influence of self output signal, this pattern is called collaborative simulation pattern (Co-Simulation mode).
The present implementation method of the various collaborative simulation technology that propose, emphasis mainly is to improve the simulation efficiency aspect, and relatively is short of in system flexibility, the support that takies the aspects such as diversity of hardware resource, emulation mode.Along with improving constantly of user's design to be measured (DUT) complexity, the I/O resource day of simulation hardware platform Target Board is becoming tight, and system should take the I/O resource of Target Board as far as possible less.In addition, in order to satisfy the different emulation customs of different user, satisfy the specific demand of different simulation stage, emulation platform should be supported multiple simulation model.Simultaneously, in order to realize R﹠D team's distributed earth emulation, emulation platform should be supported the remote emulation debug function.
Summary of the invention
Task of the present invention is to realize a kind of based on network software and hardware cooperating simulation platform, this platform has considered emphatically that resource occupation is low, debugging flexibly and characteristic such as simulation means is abundant.The present invention can realize the software and hardware cooperating simulation of Vector pattern and Co-Simulation pattern, and it mainly is made up of three parts: PC terminal 101, debugger 102 and Target Board 103.PC terminal 101 erecting stage programmable gate array (FPGA) developing instruments 111, emulator Modelsim112; The user finishes system design, configuration file generation, the generation of collaborative simulation excitation file, sampled data analysis on PC terminal 101.Debugger 102 is finished the translation and the transmission of configuration file, collaborative simulation excitation file, collaborative simulation response file, finishes the conversion of interface standard.Target Board has one or many target FPGA106, run user DUT, simulation application goal systems; Target Board has I/O interface 109 and jtag interface 110, and jtag interface 110 is passages of configuration target FPGA106, and I/O interface 109 is the passages that transmit excitation and return response.
When the user need carry out collaborative simulation, at first need the configuration file that has comprised DUT is downloaded on the target FPGA106, in the emulator 112 of PC terminal 101, define excitation vectors then, PC terminal 101 is preserved into the excitation file with excitation vectors, to encourage file to be sent to long-range debugger 102 by Ethernet translates into the serial pumping signal, is sent to Target Board 103 through the PCI-E serial line interface; The serial pumping signal is sent into target FPGA106 by I/O socket 109.Collaborative simulation interface module 108 in the target FPGA106 parses parallel pumping signal, implements excitation, gathers response, with the response data packing, returns PC terminal 101 and shows, analyzes again.For the Vector pattern, an excitation file comprises the pumping signal vector in a plurality of moment; For the Co-Simulation pattern, an excitation file only comprises the pumping signal vector in a moment, and PC terminal 101 and Target Board 103 promote emulation continuous propelling constantly by constantly encouraging file and response file alternately.
Cooperating simulation platform of the present invention is with respect to the advantage of the cooperating simulation platform that has other now: this cooperating simulation platform of is supported the emulation of Vector pattern and Co-Simulation pattern simultaneously on unified multi-mode emulation mechanisms; The 2nd, debugger 102 and PC terminal 101 are connected with ethernet line, support the user to carry out remote download and debug with remote emulation; The 3rd. when debugger 102 transmits user's pumping signal and receives response signal to Target Board 103, finish, significantly reduced taking Target Board I/O resource by serial mode; The 4th. unite use with the emulator Modelsim of industry-wide adoption, user's operation is good with the use interface.
Description of drawings
Fig. 1 is that system of the present invention forms structural drawing.Comprise PC terminal 101, Target Board 103 connects the above two debugger 102.
Fig. 2 is the cut-away view of control FPGA105 in the debugger 102.
Fig. 3 is the cut-away view of target FPGA106.
Fig. 4 is the data flow diagram of emulation under the Vector simulation model.
Fig. 5 is the data flow diagram of emulation under the Co-Simulation simulation model.
Embodiment:
The present invention is a kind of based on network software and hardware cooperating simulation platform.Now in conjunction with the accompanying drawings software and hardware cooperating simulation platform of the present invention is carried out the description of embodiment.
Fig. 1 shows system of the present invention composition diagram.System is made up of PC terminal 101, debugger 102 and Target Board 103 3 parts.The user finishes the design of DUT on PC terminal 101.Because the DUT module must rely on the support of collaborative simulation interface module 108, could receive pumping signal, passback response signal, so user DUT module 107 must produce the FPGA configuration file with collaborative simulation interface module 108 comprehensive, placement-and-routings.Configuration file downloads to the target FPGA106 of Target Board 103 through jtag interface 110 by debugger 102.The pumping signal vector of Vector pattern and Co-Simulation pattern all produces in the emulator 112Modelsim of PC terminal 101, and the packaged formation excitation of all pumping signal vectors file sends to debugger 102.Debugger 102 mainly is made of embedded microprocessor ARM104 and control FPGA105, and ARM104 finishes telecommunications functions, and control FPGA105 is implemented to the various local logical sequence of Target Board 103.The readable debugged device 102 of excitation file of user resolves to the pumping signal that hardware can be understood, sends to Target Board 103 by the PCI-E interface with serial mode.Have one or many interconnected FPGA on the Target Board 103, target FPGA106 simulation application goal systems, operation has user DUT module 107 and the collaborative simulation interface module of having downloaded 108.Collaborative simulation interface module 108 imposes on DUT module 107 with the pumping signal that receives.The excitation of 107 pairs of DUT modules produces corresponding response, and collaborative simulation interface module 108 is sent debugger 102 back to after with the response signal collection.Debugger 102 is packaged into response file with these response signals, sends PC terminal 101 back to by Ethernet, shows the response signal waveform in emulator 112Modelsim.
Fig. 2 is the cut-away view of control FPGA105 in the debugger 102, mainly comprises following each functional module:
1.ARM interface module 201: the ARM104 in the debugger 102 finishes telecommunications functions, transmitting-receiving excitation file and response file.ARM interface module 201 among the control FPGA105 is responsible for fetching the excitation file of reception from ARM104, and sends the response file that need pass back to ARM104.
2. address resolution module 202: be input as instruction or data according to the address judgement; If instruction is then sent into command analysis module and is resolved; If data are then sent into Input Data Buffer 203, in order to target FPGA configuration module 205 or send excitation/reception respond module 207 one of them calls.
3. command analysis module 204: resolve the instruction of sending here, with the function of determining to finish.Instruction is divided into three kinds of instructions: (1) is if configuration target FPGA instruction then enables target FPGA configuration module 205; (2) if read the instruction of target FPGA status register, then enable read target FPGA status register module 206; (3) if the simulation run instruction then enables to send excitation/reception respond module 207.
4. target FPGA configuration module 205: the configuration file of sending into is downloaded to target FPGA106 be configured.
5. read target FPGA status register module 206: read the value of the status register of target FPGA106, to determine to download whether successfully wait details.
6. send excitation/reception respond module 207: when emulation is carried out, be responsible for sending pumping signal and receiving the response signal of returning from target FPGA106 to target FPGA106.From the pumping signal of this module transmission and the signal response of reception all is to transmit in the mode of serial.
7. the feedback information processing module 208: after target FPGA configuration operation is finished, send the operating result that returns to feedback information processing module 208, and announcement ARM104.
In the collaborative simulation process, send into address resolution module 202 from the simulation run instruction of ARM104 through ARM interface module 201, the judgment data type then is forwarded to command analysis module 204 for instruction; Through resolving to the simulation run instruction, then enable corresponding transmission excitation/reception respond module 207.Then ARM interface module 201 will be received follow-up pumping signal, and address resolution module 202 judges that it is to send into Input Data Buffer 203 after the data.Transmission excitation/reception the respond module 207 that has been enabled subsequently begins to send pumping signal.After excitation to be sent/reception respond module 207 received response signal, 204 these instructions of notification instruction parsing module were finished, and cancellation enables; Simultaneously the response signal that receives is passed to feedback information processing module 208, return to ARM104 through ARM interface module 201 again.
Fig. 3 is the cut-away view of target FPGA106.Mainly comprise two modules: user DUT module 107 and collaborative simulation interface module 108.Collaborative simulation interface module 108 will convert parallel pumping signal to from the pumping signal that the serial of debugger 102 is imported, and parallel each port that imposes on user DUT module 107 of all pumping signals of current time.On the contrary, the response signal of DUT module 107 under the pumping signal effect gathered in parallel mode by collaborative simulation interface module 108,108 pairs of parallel response signals of collaborative simulation interface module carry out and go here and there conversion and synchronously after, return to debugger 102 in the mode of serial.
Fig. 4 is the data flow diagram of emulation under the Vector simulation model.The user for user DUT prepares an excitation file, preserves with EVCD (Extended Value Change Dump) form in emulator 112Modelsim.Bottom layer driving 407 will encourage file to send to long-range debugger 102, after debugger 102 the excitation file processing that the user is readable, translate into the pumping signal that hardware can be understood, with serial mode the pumping signal of current time be sent to Target Board 103.Collaborative simulation interface module 108 among the target FPGA106 produces pumping signal level and sequential according to these pumping signals at the corresponding input port of DUT module 107, and with the response signal value collection of the output port after the of short duration time-delay, and mail to debugger 102 after the string conversion.Debugger 102 continues to send next pumping signal constantly, and receives next response signal constantly, is advanced into end value constantly until emulation.Debugger 102 is translated into response file with the serial response signal that all collect then, preserves with the EVCD form, sends it back PC end emulator 112 and shows.
Fig. 5 is the data flow diagram of emulation under the Co-Simulation pattern.The user uses VHDL language to describe test platform TestBench504 as DUT, and moves on HDL emulator 112Modelsim.Under the Co-simulation pattern, a part of module (being module B506 herein) can be downloaded to target FPGA106 and go up realization, and (be modules A 505 with all the other modules herein, module C507) remains running in the emulator 112, and module B506 is substituted by " black box " structure, should " black box " structure keep the port attribute identical with former design document, the other parts of DUT can not made any modification.Emulator 112Modelsim is sent to dynamic link library 509 by calling towards the FLI interface 508 of VHDL language with excitation information, corresponding built-in function is translated into excitation information the excitation file of EVCD form, send to long-range debugger 102 through bottom layer driving 407, after debugger 102 the excitation file processing that the user is readable, translate into the pumping signal that hardware can be understood, the pumping signal of current time is sent to target FPGA106 with serial mode.Collaborative simulation interface module 108 among the target FPGA106 produces pumping signal level and sequential according to these pumping signals at the corresponding input port of DUT module 107, and with the response signal value collection of the output port after the of short duration time-delay, and mail to debugger 102 after the string conversion.The current serial response signal that debugger 102 will collect is translated into response file, preserves with the EVCD form, sends it back PC end emulator 112.PC end emulator 112 produces next new pumping signal vector constantly according to testbench504 with the response signal vector that feeds back, 103 of PC terminal 101 and Target Boards encourage file and response file so repeatedly alternately, are advanced into end value constantly until emulation.
Claims (6)
1. based on network software and hardware cooperating simulation platform comprises three parts: the user PC end of operating software part, and the Target Board of analog hardware part, and with the debugger of the two interconnection.
2. a kind of based on network software and hardware cooperating simulation platform according to claim 1 is characterized in that: the support to Vector pattern and Co-simulation mode simulation can realize on unified multi-mode emulation system.
3. a kind of based on network software and hardware cooperating simulation platform according to claim 2, it is characterized in that: unified multi-mode emulation system uses debugger that the excitation file translation that user PC end produces is become the discernible pumping signal of Target Board hardware, and the response signal of Target Board passback is translated into the readable response file of user.
4. a kind of based on network software and hardware cooperating simulation platform according to claim 2, it is characterized in that: under the unified multi-mode emulation system, the emulation of Co-simulation pattern propelling constantly is by encouraging file and response file to realize repeatedly alternately between user PC end and Target Board; The emulation of Vector pattern propelling is constantly realized by mutual repeatedly pumping signal and response signal between debugger and Target Board.
5. a kind of based on network software and hardware cooperating simulation platform according to claim 1, it is characterized in that: collaborative simulation interface module among the target FPGA and user DUT module apply excitation and gather response in parallel mode, and communicate by letter in the mode of serial with debugger.
6. a kind of based on network software and hardware cooperating simulation platform according to claim 1, it is characterized in that: user PC end is connected by Ethernet with debugger, both sides realize the remote download and the remote emulation debugging of collaborative simulation by TCP/IP SOCKET communication.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100506865A CN101174283A (en) | 2007-12-03 | 2007-12-03 | Software and hardware cooperating simulation platform based on network |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100506865A CN101174283A (en) | 2007-12-03 | 2007-12-03 | Software and hardware cooperating simulation platform based on network |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101174283A true CN101174283A (en) | 2008-05-07 |
Family
ID=39422797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007100506865A Pending CN101174283A (en) | 2007-12-03 | 2007-12-03 | Software and hardware cooperating simulation platform based on network |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101174283A (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184131A (en) * | 2011-04-13 | 2011-09-14 | 中兴通讯股份有限公司 | Simulation verification method and device for SoC (system on a chip) |
| CN101577713B (en) * | 2009-06-02 | 2012-07-04 | 中兴通讯股份有限公司 | Realization method, device and testing system for virtual user identification module |
| CN102681923A (en) * | 2011-03-16 | 2012-09-19 | 中国科学院微电子研究所 | Hardware platform device for verifying system-on-chips |
| CN102736942A (en) * | 2011-04-12 | 2012-10-17 | 洛克泰克科技有限公司 | Parallel simulation using multiple co-simulators |
| CN105653346A (en) * | 2014-11-19 | 2016-06-08 | 中国航空工业集团公司西安飞机设计研究所 | Universal exciter frame design method for assisting avionics software development |
| CN106303759A (en) * | 2016-08-30 | 2017-01-04 | 北京赛博兴安科技有限公司 | A kind of high speed serialization transceiver interface based on FPGA and method of work thereof |
| CN106292409A (en) * | 2015-06-03 | 2017-01-04 | 国网智能电网研究院 | A kind of real-time emulation system based on FPGA multi tate optical-fibre communications and emulation mode thereof |
| CN107038265A (en) * | 2016-02-04 | 2017-08-11 | 京微雅格（北京）科技有限公司 | Computing architecture including FPGA circuitry and use its EDA design methods |
| CN108319453A (en) * | 2017-12-20 | 2018-07-24 | 中核控制***工程有限公司 | A kind of algorithm configuration software design approach based on FPGA control logics |
| CN109492301A (en) * | 2018-11-08 | 2019-03-19 | 北京世冠金洋科技发展有限公司 | Software and hardware switching method and system |
| CN109710536A (en) * | 2018-12-29 | 2019-05-03 | 湖北航天技术研究院总体设计所 | A kind of system and method automatically extracting FPGA software verification result simulation waveform |
| CN110110355A (en) * | 2019-03-25 | 2019-08-09 | 电子科技大学 | A kind of Prototype Verification Platform based on FPGA |
| CN111338753A (en) * | 2020-02-17 | 2020-06-26 | 东风电子科技股份有限公司 | System for realizing hardware simulation of electronic control unit based on computer |
| CN112329369A (en) * | 2020-11-09 | 2021-02-05 | 安徽芯纪元科技有限公司 | Method for debugging software on chip simulation model |
| CN117194276A (en) * | 2023-11-06 | 2023-12-08 | 沐曦集成电路(上海)有限公司 | Chip software and hardware joint simulation debugging system |
-
2007
- 2007-12-03 CN CNA2007100506865A patent/CN101174283A/en active Pending
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101577713B (en) * | 2009-06-02 | 2012-07-04 | 中兴通讯股份有限公司 | Realization method, device and testing system for virtual user identification module |
| CN102681923A (en) * | 2011-03-16 | 2012-09-19 | 中国科学院微电子研究所 | Hardware platform device for verifying system-on-chips |
| CN102681923B (en) * | 2011-03-16 | 2015-04-01 | 中国科学院微电子研究所 | Hardware platform device for verifying system-on-chips |
| CN102736942A (en) * | 2011-04-12 | 2012-10-17 | 洛克泰克科技有限公司 | Parallel simulation using multiple co-simulators |
| CN102184131A (en) * | 2011-04-13 | 2011-09-14 | 中兴通讯股份有限公司 | Simulation verification method and device for SoC (system on a chip) |
| CN102184131B (en) * | 2011-04-13 | 2015-08-12 | 中兴通讯股份有限公司 | The emulation verification method of SOC (system on a chip) and device |
| CN105653346A (en) * | 2014-11-19 | 2016-06-08 | 中国航空工业集团公司西安飞机设计研究所 | Universal exciter frame design method for assisting avionics software development |
| CN105653346B (en) * | 2014-11-19 | 2019-01-01 | 中国航空工业集团公司西安飞机设计研究所 | A kind of general driver frame design method assisting avionics software development |
| CN106292409A (en) * | 2015-06-03 | 2017-01-04 | 国网智能电网研究院 | A kind of real-time emulation system based on FPGA multi tate optical-fibre communications and emulation mode thereof |
| CN106292409B (en) * | 2015-06-03 | 2020-03-06 | 国网智能电网研究院 | Real-time simulation system based on FPGA multi-rate optical fiber communication and simulation method thereof |
| CN107038265A (en) * | 2016-02-04 | 2017-08-11 | 京微雅格（北京）科技有限公司 | Computing architecture including FPGA circuitry and use its EDA design methods |
| CN106303759A (en) * | 2016-08-30 | 2017-01-04 | 北京赛博兴安科技有限公司 | A kind of high speed serialization transceiver interface based on FPGA and method of work thereof |
| CN106303759B (en) * | 2016-08-30 | 2019-07-12 | 北京赛博兴安科技有限公司 | A kind of high speed serialization transceiver interface and its working method based on FPGA |
| CN108319453A (en) * | 2017-12-20 | 2018-07-24 | 中核控制***工程有限公司 | A kind of algorithm configuration software design approach based on FPGA control logics |
| CN109492301A (en) * | 2018-11-08 | 2019-03-19 | 北京世冠金洋科技发展有限公司 | Software and hardware switching method and system |
| CN109492301B (en) * | 2018-11-08 | 2020-05-22 | 北京世冠金洋科技发展有限公司 | Software and hardware switching method and system |
| CN109710536A (en) * | 2018-12-29 | 2019-05-03 | 湖北航天技术研究院总体设计所 | A kind of system and method automatically extracting FPGA software verification result simulation waveform |
| CN109710536B (en) * | 2018-12-29 | 2022-03-18 | 湖北航天技术研究院总体设计所 | System and method for automatically extracting simulation waveform of FPGA software verification result |
| CN110110355A (en) * | 2019-03-25 | 2019-08-09 | 电子科技大学 | A kind of Prototype Verification Platform based on FPGA |
| CN111338753A (en) * | 2020-02-17 | 2020-06-26 | 东风电子科技股份有限公司 | System for realizing hardware simulation of electronic control unit based on computer |
| CN112329369A (en) * | 2020-11-09 | 2021-02-05 | 安徽芯纪元科技有限公司 | Method for debugging software on chip simulation model |
| CN112329369B (en) * | 2020-11-09 | 2024-04-12 | 安徽芯纪元科技有限公司 | Method for debugging software on chip simulation model |
| CN117194276A (en) * | 2023-11-06 | 2023-12-08 | 沐曦集成电路(上海)有限公司 | Chip software and hardware joint simulation debugging system |
| CN117194276B (en) * | 2023-11-06 | 2024-01-23 | 沐曦集成电路(上海)有限公司 | Chip software and hardware joint simulation debugging system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101174283A (en) | Software and hardware cooperating simulation platform based on network | |
| US8839179B2 (en) | Prototype and emulation system for multiple custom prototype boards | |
| CN100399341C (en) | Software and hardware synergistic simulation/ validation system and vector mode simulation/ validation method | |
| US7480609B1 (en) | Applying distributed simulation techniques to hardware emulation | |
| US8281280B2 (en) | Method and apparatus for versatile controllability and observability in prototype system | |
| CN101719096B (en) | Method for improving executing speed of test script of real-time embedded system | |
| CN104063321B (en) | A kind of test checking system and test verification method for the soft core programs of MicroBlaze | |
| US7424416B1 (en) | Interfacing hardware emulation to distributed simulation environments | |
| CN103925853B (en) | A kind of carrier rocket ground testing system device | |
| CN101499937A (en) | Software and hardware collaborative simulation verification system and method based on FPGA | |
| CN108427776A (en) | Distributed all digital combined simulation system and method | |
| CN102480467B (en) | A kind of SOC software and hardware cooperating simulation verification method of communications protocol Network Based | |
| CN102591756B (en) | Verification method and system for interface protocol compatibility of multi-interface protocol chip | |
| CN102521444A (en) | Cooperative simulation/verification method and device for software and hardware | |
| US20130035925A1 (en) | Method and apparatus for versatile controllability and observability in prototype system | |
| CN104991862B (en) | FPGA remote online adjusting, measuring methods based on JTAG virtual technologies | |
| CN110442528B (en) | Train control software cross-platform operation system and method based on safety computer simulation software | |
| CN101102566B (en) | A design method and debugging method for mobile phone JTAG debugging interface signals | |
| CN114036013A (en) | UVM-based transponder chip multi-module synchronous verification platform and verification method | |
| CN110134561B (en) | Method and device for outputting debugging information in software and hardware collaborative verification | |
| CN105956267A (en) | Equipment modeling language based embedded type emulated serial port and modeling method thereof | |
| CN106708764A (en) | Universal IO processing system for airborne avionic system | |
| CN102411312A (en) | Sensor simulator and satellite closed loop simulation system | |
| CN104734900B (en) | A kind of sending control method of communication protocol test | |
| CN102436186B (en) | Performer simulator and satellite closed loop simulation system with performer simulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |