CN110098199B - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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CN110098199B
CN110098199B CN201910368262.6A CN201910368262A CN110098199B CN 110098199 B CN110098199 B CN 110098199B CN 201910368262 A CN201910368262 A CN 201910368262A CN 110098199 B CN110098199 B CN 110098199B
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common electrode
layer
substrate
electrically connected
display panel
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CN110098199A (zh
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朱静
王添鸿
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to PCT/CN2019/109091 priority patent/WO2020224172A1/zh
Priority to US16/618,812 priority patent/US11462570B2/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
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    • H01L2224/29034—Disposition the layer connector covering only portions of the surface to be connected
    • H01L2224/29035—Disposition the layer connector covering only portions of the surface to be connected covering only the peripheral area of the surface to be connected
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    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29344—Gold [Au] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32238—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

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Abstract

本申请提供一种显示面板，其包括显示区和设置在所述显示区***的边框区，所述边框区包括一阵列基板和彩膜基板；阵列基板包括第一衬底、设置在所述第一衬底上的GOA电路；彩膜基板包括第二衬底、设置在所述第二衬底上的讯号走线；其中所述GOA电路与所述讯号走线重叠设置。本申请还涉及一显示装置。本申请通过将讯号走线转移至彩膜基板，并与GOA电路重叠设置，减少了阵列基板侧的边框宽度。

Description

显示面板及显示装置
技术领域
本申请涉及一种显示技术，特别涉及一种显示面板及显示装置。
背景技术
如图1所示为现有技术的显示面板的示意图，显示面板包括显示区和设置在显示区***的边框区，边框区由GOA(Gate Driver On Array)电路、GOA讯号走线(GOABusline)、公共电极(COM)三大部分构成。GOA讯号走线因应用于大尺寸高解析度产品，RCLoading(电容负载)较重，故而需要搭配GOA讯号走线设计较宽，进而需要的边框较大。
显示面板的成盒侧由导电胶(Seal)和基板组成，由于导电胶需要受紫外线(Ultraviolet，UV)照射实现固化，阵列基板侧的走线的开口率符合一定的要求后，才能使导电胶固化良好。
受限于以上需求，导电胶与GOA讯号走线不重叠时，GOA讯号走线可以采用实心设计，若导电胶与GOA讯号走线重叠时，会将GOA讯号走线挖狭缝(slit)。为了保持有效的金属线宽，两者均需要的边框的宽度很大。
发明内容
本申请实施例提供一种显示面板及显示装置，以解决现有的显示面板对边框宽度需求较大的技术问题。
本申请实施例提供一种显示面板，包括显示区和设置在所述显示区***的边框区，所述边框区包括：
一阵列基板，包括第一衬底、设置在所述第一衬底上的GOA电路；以及
一彩膜基板，包括第二衬底、设置在所述第二衬底上的讯号走线；
其中所述GOA电路与所述讯号走线重叠设置。
在本申请的显示面板的所述边框区中，所述彩膜基板包括第一公共电极走线，所述第一公共电极走线设置在所述讯号走线远离所述显示区的一侧。
在本申请的显示面板的所述边框区中，所述阵列基板包括第二公共电极走线，所述第二公共电极走线设置在所述GOA电路远离所述显示区的一侧；
所述第一公共电极走线和所述第二公共电极走线重叠设置。
在本申请的显示面板的所述边框区还包括导电胶，所述导电胶固定设置在所述阵列基板和所述彩膜基板之间；所述GOA电路与所述讯号走线通过所述导电胶电性连接；所述第一公共电极走线和所述第二公共电极走线通过所述导电胶电性连接。
在本申请的显示面板中，所述阵列基板包括依次设置在所述第一衬底上的第一金属层、第一绝缘层、有源层、第二金属层、第二绝缘层、第一平坦层和第一透明导电层；
所述彩膜基板包括依次设置在所述第二衬底上的第三金属层、第三绝缘层、第二平坦层和第二透明导电层；
所述第一透明导电层和所述第二透明导电层通过导电胶电性连接。
在本申请的显示面板中，所述GOA电路包括薄膜晶体管，所述薄膜晶体管的栅极形成于所述第一金属层中，所述薄膜晶体管的源/漏极形成于所述第二金属层中，所述薄膜晶体管的沟道区域形成于所述有源层中；所述源/漏极通过第一过孔电性连接于所述第一透明导电层；
所述讯号走线形成于所述第三金属层；所述讯号走线通过第二过孔电性连接于所述第二透明导电层。
在本申请的显示面板中，所述第二公共电极走线形成于所述第一金属层中，所述第二公共电极走线通过第三通孔电性连接于所述第二金属层，所述第二金属层通过第四通孔电性连接于所述第一透明导电层；
所述第一公共电极走线形成于所述第三金属层中，所述第一公共电极走线通过第五通孔电性连接于所述第二透明导电层。
在本申请的显示面板中，所述第一公共电极走线和所述讯号走线均为实心金属走线。
在本申请的显示面板中，所述导电胶包括胶体和设置在所述胶体内的导电体，所述GOA电路与所述讯号走线通过所述导电体电性连接；所述第一公共电极走线和所述第二公共电极走线通过所述导电体电性连接。
本申请还涉及一种显示装置，其包括上述的显示面板。
具体的，所述显示面板，包括显示区和设置在所述显示区***的边框区，所述边框区包括：
一阵列基板，包括第一衬底、设置在所述第一衬底上的GOA电路；以及
一彩膜基板，包括第二衬底、设置在所述第二衬底上的讯号走线；
其中所述GOA电路与所述讯号走线重叠设置。
在本申请的显示装置的所述边框区中，所述彩膜基板包括第一公共电极走线，所述第一公共电极走线设置在所述讯号走线远离所述显示区的一侧。
在本申请的显示面板的所述边框区中，所述阵列基板包括第二公共电极走线，所述第二公共电极走线设置在所述GOA电路远离所述显示区的一侧；
所述第一公共电极走线和所述第二公共电极走线重叠设置。
在本申请的显示装置的所述边框区还包括导电胶，所述导电胶固定设置在所述阵列基板和所述彩膜基板之间；所述GOA电路与所述讯号走线通过所述导电胶电性连接；所述第一公共电极走线和所述第二公共电极走线通过所述导电胶电性连接。
在本申请的显示装置中，所述阵列基板包括依次设置在所述第一衬底上的第一金属层、第一绝缘层、有源层、第二金属层、第二绝缘层、第一平坦层和第一透明导电层；
所述彩膜基板包括依次设置在所述第二衬底上的第三金属层、第三绝缘层、第二平坦层和第二透明导电层；
所述第一透明导电层和所述第二透明导电层通过导电胶电性连接。
在本申请的显示装置中，所述GOA电路包括薄膜晶体管，所述薄膜晶体管的栅极形成于所述第一金属层中，所述薄膜晶体管的源/漏极形成于所述第二金属层中，所述薄膜晶体管的沟道区域形成于所述有源层中；所述源/漏极通过第一过孔电性连接于所述第一透明导电层；
所述讯号走线形成于所述第三金属层中；所述讯号走线通过第二过孔电性连接于所述第二透明导电层。
在本申请的显示装置中，所述第二公共电极走线形成于所述第一金属层中，所述第二公共电极走线通过第三通孔电性连接于所述第二金属层，所述第二金属层通过第四通孔电性连接于所述第一透明导电层；
所述第一公共电极走线形成于所述第三金属层中，所述第一公共电极走线通过第五通孔电性连接于所述第二透明导电层。
在本申请的显示装置中，所述第一公共电极走线和所述讯号走线均为实心金属走线。
在本申请的显示装置中，所述导电胶包括胶体和设置在所述胶体内的导电体，所述GOA电路与所述讯号走线通过所述导电体电性连接；所述第一公共电极走线和所述第二公共电极走线通过所述导电体电性连接。
相较于现有技术的显示面板，本申请的显示面板及显示装置通过将讯号走线转移至彩膜基板，并与GOA电路重叠设置，减少了阵列基板侧的边框宽度；另外，将现有技术的阵列基板中的需要开狭缝的公共电极走线也转移至本申请的彩膜基板，使得本申请的第一公共电极走线设置在彩膜基板上，且第一公共电极走线为实心走线，一方面避免了开狭缝，另一方第一公共电极走线和第二公共电极走线重叠设置，二者共同节省了空间；解决了现有的显示面板对边框宽度需求较大的技术问题。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面对实施例中所需要使用的附图作简单的介绍。下面描述中的附图仅为本申请的部分实施例，对于本领域普通技术人员而言，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1为现有技术的显示面板的结构示意图；
图2为本申请的显示面板的实施例的结构示意图；
图3为本申请的显示面板的实施例的另一结构示意图。
具体实施方式
请参照附图中的图式，其中相同的组件符号代表相同的组件。以下的说明是基于所例示的本申请具体实施例，其不应被视为限制本申请未在此详述的其它具体实施例。
请参照图2和图3，图2为本申请的显示面板的实施例的结构示意图；图3为本申请的显示面板的实施例的另一结构示意图。本申请实施例的显示面板100，其包括显示区A和设置在显示区A***的边框区B。
边框区B包括一阵列基板10、一彩膜基板20和设置在阵列基板10和彩膜基板20之间的导电胶30。
阵列基板10包括第一衬底11、设置在第一衬底11上的GOA电路12(阵列基板行驱动电路12)。彩膜基板20包括第二衬底21、设置在第二衬底21上的讯号走线22。其中GOA电路12与讯号走线22重叠设置。
在现有技术的显示面板中，讯号走线和GOA电路均设置在阵列基板上，使得阵列基板的边框侧需要较大的空间，而且讯号走线位于导电胶的下方，而为了促使导电胶能充分的光照固化，讯号走线需要挖狭缝，使光照透过狭缝照射到导电胶，从而增加了讯号走线的宽度，进而增加了空间的需求。但是，本实施例的显示面板100将讯号走线22转移至彩膜基板20。一方面，讯号走线22与GOA电路12重叠设置，减少了阵列基板10侧需要布置讯号走线22的边框宽度；另一方面，讯号走线22位于导电胶30的上方，避免了讯号走线22挖狭缝，即讯号走线22采用实心的方式制备，减小了讯号走线22的宽度，进而减少了讯号走线22所需的空间，以节省了边框区B的宽度。
在本实施例的显示面板100的边框区B中，彩膜基板20包括第一公共电极走线23。第一公共电极走线23设置在讯号走线22远离显示区A的一侧。
阵列基板10包括第二公共电极走线13。第二公共电极走线13设置在GOA电路12远离显示区A的一侧。第一公共电极走线23和第二公共电极走线13重叠设置。
在现有技术的显示面板中，阵列基板的边框侧还设置有多根公共电极走线，使得阵列基板侧需要更多的空间用于布置公共电极走线，而且公共电极走线位于导电胶的下方，而为了促使导电胶能充分的光照固化，公共电极走线需要挖狭缝，使光照透过狭缝照射到导电胶，从而增加了公共电极走线的宽度，进而增加了空间的需求。但是，本实施例的显示面板10将需要开狭缝的第一公共电极走线23也转移至彩膜基板20，使得第一公共电极走线23设置在彩膜基板20上。一方面避免了第一公共电极走线23开狭缝，即第一公共电极走线23为实心走线，节省了空间；另一方面第一公共电极走线23和第二公共电极走线13重叠设置，也节省了空间。进而使得边框区B窄边框化。
具体的，在本实施例的显示面板100的边框区B还包括导电胶30。导电胶30固定设置在阵列基板10和彩膜基板20之间。GOA电路12与讯号走线22通过导电胶30电性连接。第一公共电极走线23和第二公共电极走线13通过导电胶30电性连接。
其中，导电胶30包括胶体31和设置在胶体31内的导电体32。GOA电路12与讯号走线22通过导电体32电性连接。第一公共电极走线23和第二公共电极走线13通过导电体32电性连接。可选的，导电体32为金球。
在本实施例的显示面板100中，阵列基板10包括依次设置在第一衬底11上的第一金属层101、第一绝缘层102、有源层103、第二金属层104、第二绝缘层105、第一平坦层106和第一透明导电层107。
彩膜基板20包括依次设置在第二衬底21上的第三金属层201、第三绝缘层202、第二平坦层203和第二透明导电层204。
第一透明导电层107和第二透明导电层204通过导电胶30电性连接。其中第一透明导电层107和第二透明导电层204均为氧化铟锡(Indium Tin Oxide,ITO)层。
具体的，在本实施例的显示面板100中，GOA电路12包括多个薄膜晶体管121(图中仅示出一个为例，但并不限于此)，薄膜晶体管121的栅极形成在第一金属层101中，即第一金属层101包括薄膜晶体管121的栅极。薄膜晶体管121的源/漏极形成于在第二金属层104中，即第二金属层104包括薄膜晶体管121的源/漏极。薄膜晶体管121的沟道区域形成在有源层103中，即有源层103包括薄膜晶体管121的沟道区域。源/漏极通过第一过孔111电性连接于第一透明导电层107。
讯号走线22形成于第三金属层201中，即第三金属层201包括讯号走线22。讯号走线22通过第二过孔112电性连接于第二透明导电层204。而第一透明导电层107和第二透明导电层204通过导电胶30电导通，因此讯号走线22电性连接于GOA电路12，实现Gate(扫描)讯号的传输。
第二公共电极走线13形成于第一金属层101中，即第一金属层101包括第二公共电极走线13。第二公共电极走线13通过第三通孔113电性连接于第二金属层104。第二金属层104通过第四通孔114电性连接于第一透明导电层107。
第一公共电极走线23形成于第三金属层201中，即第三金属层201包括第一公共电极走线23。第一公共电极走线23通过第五通孔115电性连接于第二透明导电层204。而第一透明导电层107和第二透明导电层204通过导电胶30电导通，因此第二公共电极走线13电性连接于第一公共电极走线23，实现公共电极讯号的传输。
相较于现有技术的显示面板，本申请的显示面板及显示装置通过将讯号走线转移至彩膜基板，并与GOA电路重叠设置，减少了阵列基板侧的边框宽度；另外，将现有技术的阵列基板中的需要开狭缝的公共电极走线也转移至本申请的彩膜基板，使得本申请的第一公共电极走线设置在彩膜基板上，且第一公共电极走线为实心走线，一方面避免了开狭缝，另一方第一公共电极走线和第二公共电极走线重叠设置，二者共同节省了空间；解决了现有的显示面板对边框宽度需求较大的技术问题。
以上所述，对于本领域的普通技术人员来说，可以根据本申请的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本申请后附的权利要求的保护范围。

Claims (8)

1.一种显示面板，包括显示区和设置在所述显示区***的边框区，其特征在于，所述边框区包括：
一阵列基板，包括第一衬底、设置在所述第一衬底上的GOA电路；以及
一彩膜基板，包括第二衬底、设置在所述第二衬底上的讯号走线；
其中所述GOA电路与所述讯号走线重叠设置，所述彩膜基板包括第一公共电极走线，所述第一公共电极走线设置在所述讯号走线远离所述显示区的一侧，且所述第一公共电极走线仅设置在所述边框区，所述第一公共电极用于给公共电极传输电极讯号，所述阵列基板包括第二公共电极走线，所述第二公共电极走线设置在所述GOA电路远离所述显示区的一侧，所述第一公共电极走线和所述第二公共电极走线重叠设置。
2.根据权利要求1所述的显示面板，其特征在于，所述边框区还包括导电胶，所述导电胶固定设置在所述阵列基板和所述彩膜基板之间；所述GOA电路与所述讯号走线通过所述导电胶电性连接；所述第一公共电极走线和所述第二公共电极走线通过所述导电胶电性连接。
3.根据权利要求1所述的显示面板，其特征在于，所述阵列基板包括依次设置在所述第一衬底上的第一金属层、第一绝缘层、有源层、第二金属层、第二绝缘层、第一平坦层和第一透明导电层；
所述彩膜基板包括依次设置在所述第二衬底上的第三金属层、第三绝缘层、第二平坦层和第二透明导电层；
所述第一透明导电层和所述第二透明导电层通过导电胶电性连接。
4.根据权利要求3所述的显示面板，其特征在于，所述GOA电路包括薄膜晶体管，所述薄膜晶体管的栅极形成于所述第一金属层中，所述薄膜晶体管的源/漏极形成于所述第二金属层中，所述薄膜晶体管的沟道区域形成于所述有源层中；所述源/漏极通过第一过孔电性连接于所述第一透明导电层；
所述讯号走线形成于所述第三金属层中；所述讯号走线通过第二过孔电性连接于所述第二透明导电层。
5.根据权利要求3所述的显示面板，其特征在于，所述第二公共电极走线形成于所述第一金属层中，所述第二公共电极走线通过第三通孔电性连接于所述第二金属层，所述第二金属层通过第四通孔电性连接于所述第一透明导电层；
所述第一公共电极走线形成于所述第三金属层中，所述第一公共电极走线通过第五通孔电性连接于所述第二透明导电层。
6.根据权利要求1所述的显示面板，其特征在于，所述第一公共电极走线和所述讯号走线均为实心金属走线。
7.根据权利要求2所述的显示面板，其特征在于，所述导电胶包括胶体和设置在所述胶体内的导电体，所述GOA电路与所述讯号走线通过所述导电体电性连接；所述第一公共电极走线和所述第二公共电极走线通过所述导电体电性连接。
8.一种显示装置，其特征在于，包括权利要求1-7所述的显示面板。
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