CN110021661A - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN110021661A CN110021661A CN201910342961.3A CN201910342961A CN110021661A CN 110021661 A CN110021661 A CN 110021661A CN 201910342961 A CN201910342961 A CN 201910342961A CN 110021661 A CN110021661 A CN 110021661A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 260
- 238000002360 preparation method Methods 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 claims abstract description 37
- 238000011065 in-situ storage Methods 0.000 claims abstract description 24
- 230000004888 barrier function Effects 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910002601 GaN Inorganic materials 0.000 description 32
- 238000010586 diagram Methods 0.000 description 14
- 230000005533 two-dimensional electron gas Effects 0.000 description 12
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- GQYHUHYESMUTHG-UHFFFAOYSA-N lithium niobate Chemical compound [Li+].[O-][Nb](=O)=O GQYHUHYESMUTHG-UHFFFAOYSA-N 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000007725 thermal activation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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- Junction Field-Effect Transistors (AREA)
Abstract
The embodiment of the present application provides a kind of semiconductor devices and preparation method thereof, wherein, surface based on p type semiconductor layer simultaneously combines production between the grid and p type semiconductor layer of the mode of growth in situ in the semiconductor device to form n type semiconductor layer, so that the n/p that p type semiconductor layer and n type semiconductor layer can collectively form reverse bias is tied, to which grid leakage current be greatly reduced, the reliability of semiconductor devices is improved.
Description
Technical Field
The present disclosure relates to the field of microelectronic technologies, and in particular, to a semiconductor device and a method for fabricating the same.
Background
In a conventional HEMT (High Electron Mobility Transistor) device, such as a gallium nitride (GaN) device, a two-dimensional Electron gas exists between a channel layer and a barrier layer, so that the GaN device is in a normally-on state.
Disclosure of Invention
In view of the above, the present application provides a semiconductor device and a method for fabricating the same, as follows.
In one aspect, the present invention provides a semiconductor device including a heterostructure and a source, a drain and a gate connected to the heterostructure, the heterostructure including:
a substrate;
manufacturing a formed channel layer on the basis of the substrate;
manufacturing a formed barrier layer on the basis of one side of the channel layer away from the substrate;
manufacturing a formed P-type semiconductor layer on the basis of one side of the barrier layer away from the channel layer;
an N-type semiconductor layer formed by in-situ growth on the basis of the surface of the P-type semiconductor layer far away from the barrier layer;
the source electrode and the drain electrode are formed on the basis of the manufacture of the channel layer and are positioned at two opposite ends of the barrier layer, and the grid electrode is manufactured above the N-type semiconductor layer and is in contact with the N-type semiconductor layer.
In an option of the embodiment of the present application, a through hole is formed in the N-type semiconductor layer, and the gate contacts the P-type semiconductor layer through the through hole.
In an option of an embodiment of the present application, the N-type semiconductor layer is doped with a concentration of 1e17～1e19cm-3The thickness of the N-type semiconductor layer is 10 nm-200 nm.
In an option of an embodiment of the present application, the heterostructure further includes a low temperature semiconductor cap layer formed by in-situ growth based on a surface of the N-type semiconductor layer away from the P-type semiconductor layer; or,
and a low-temperature semiconductor cap layer which is formed on the basis that the P-type semiconductor layer is close to the surface of the N-type semiconductor layer and is grown in situ.
In an option of an embodiment of the present application, a forming temperature of the low temperature semiconductor cap layer is 450 to 600 ℃.
In the selection of the embodiment, the thickness of the low-temperature semiconductor cap layer is 2nm to 50 nm.
In an option of an embodiment of the present application, the substrate includes a substrate, and a buffer layer formed based on the substrate, the buffer layer being located between the substrate and the channel layer.
On the other hand, the embodiment of the present application further provides a manufacturing method of a semiconductor device, where the manufacturing method includes:
providing a substrate;
forming a channel layer on the basis of the substrate;
manufacturing and forming a source electrode, a drain electrode and a barrier layer on one side of the channel layer, wherein the source electrode and the drain electrode are respectively positioned at two ends of the barrier layer;
manufacturing and forming a P-type semiconductor layer on one side of the barrier layer away from the channel layer;
forming an N-type semiconductor layer on the surface of the P-type semiconductor layer far away from the barrier layer through in-situ growth;
and manufacturing and forming a grid on the surface of the N-type semiconductor layer far away from the P-type semiconductor layer.
In an option of this embodiment, before the step of forming the gate on the side of the N-type semiconductor layer away from the P-type semiconductor layer, the method further includes:
and etching the N-type semiconductor layer to form a through hole on the N-type semiconductor layer, so that a grid electrode manufactured and formed on the basis of the N-type semiconductor layer can be in contact with the P-type semiconductor layer through the through hole.
In an option of this embodiment, the step of forming a gate on a surface of the N-type semiconductor layer away from the P-type semiconductor layer includes:
forming a low-temperature semiconductor cap layer on the surface of the N-type semiconductor layer far away from the P-type semiconductor layer through in-situ growth;
etching the N-type semiconductor layer and the low-temperature semiconductor cap layer to form through holes on the N-type semiconductor layer and the low-temperature semiconductor cap layer;
and manufacturing and forming a grid electrode on the basis of one side of the low-temperature semiconductor cap layer, which is far away from the N-type semiconductor layer, and enabling the grid electrode to be in contact with the P-type semiconductor layer through the through hole.
Based on the scheme provided above, the application has at least the following beneficial effects:
in the semiconductor device and the manufacturing method thereof provided by the embodiment of the application, after the epitaxial growth of the P-type semiconductor layer in the semiconductor device is completed, the in-situ growth mode is continuously adopted to manufacture and generate the N-type semiconductor layer between the gate and the P-type semiconductor layer, so that the N-type semiconductor layer and the P-type semiconductor layer jointly form a reverse N/P junction, the leakage current is effectively reduced, the gate bias voltage is improved, and the semiconductor device is ensured to be in a normally-closed state.
In addition, a low-temperature semiconductor cap layer is further formed on the N-type semiconductor layer in an in-situ growth mode to cover the semiconductor layer with the inherent penetrating dislocation and the pits on the surface of the semiconductor layer, and leakage current is further reduced.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
FIG. 1 is a schematic cross-sectional view of a conventional P-GaN device.
FIG. 2 is a schematic cross-sectional view of another conventional P-GaN device.
Fig. 3 is a schematic cross-sectional structure diagram of a semiconductor device provided in a first embodiment of the present application.
Fig. 4(a) -4 (b) are schematic diagrams of conduction band edge profiles of the P-GaN device shown in fig. 2 at different gate bias voltages.
Fig. 5(a) -5 (b) are schematic views of conduction band edge profiles of semiconductor devices provided in the embodiments of the present application at different gate bias voltages.
Fig. 6(a) -6 (b) are graphs showing simulation results of 2DEG density of the P-GaN device shown in fig. 2 and the semiconductor device provided in the embodiment of the present application at different gate bias voltages, respectively.
Fig. 7 is a schematic cross-sectional structure diagram of a semiconductor device provided in the second embodiment of the present application.
Fig. 8 is a schematic cross-sectional structure diagram of a semiconductor device provided in a third embodiment of the present application.
Fig. 9 is a schematic cross-sectional structure diagram of another semiconductor device provided in the third embodiment of the present application.
Fig. 10 is a schematic cross-sectional structure diagram of another semiconductor device provided in the third embodiment of the present application.
Fig. 11 is a schematic cross-sectional structure diagram of another semiconductor device provided in the third embodiment of the present application.
Fig. 12 is a process flow diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 13 is a sub-flowchart of step S6 shown in fig. 12.
Icon: 10-a semiconductor device; 11-a source electrode; 12-a drain electrode; 13-a gate; 14-a substrate; 140-a substrate; 141-a buffer layer; 15-a channel layer; 16-barrier layer; a 17-P type semiconductor layer; 170-groove; an 18-N type semiconductor layer; 19-a low temperature semiconductor cap layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the conventional P-GaN device, the formation of the ohmic contact or the schottky contact mainly depends on the work function of the metal in contact with the P-GaN layer, that is, the magnitude of the gate leakage current mainly depends on the metal type of the metal electrode (gate) in contact with the P-GaN layer, so in practical applications, in order to realize the normally-off of the P-GaN device, a larger forward gate bias is generally obtained on the premise of a smaller leakage current as much as possible, so as to improve the reliability of the device.
Currently, reverse biased schottky contacts have less leakage current than ohmic contacts, but even with well processed metal/P-GaN schottky junctions as shown in fig. 1, when the gate bias voltage is less than 7V, there is a full peak electric field inside the depleted P-GaN layer, resulting in the risk of avalanche breakdown.
Furthermore, as shown in FIG. 2, in some other embodiments, in order to reduce and redistribute the peak electric field inside the P-GaN layer as shown in FIG. 1, N-type impurities (e.g., silicon impurities) may be ion implanted into a partial region of the P-GaN layer to form an N-GaN edge guard ring after thermal activation. However, in practice, in order to obtain higher dopant activation efficiencyIt is generally desirable to use more than 5e15cm-2To generate a sufficient electron concentration, so that damage due to ion implantation cannot be effectively eliminated even at temperatures as high as 1200 ℃. In addition, the intrinsic threading dislocation cavity in the P-GaN layer epitaxially grown by MOCVD (Metal-Organic Chemical Vapor Deposition) causes an abnormal leakage path in the P-GaN device, resulting in large leakage current and poor device reliability.
In contrast, as shown in fig. 3, the present embodiment provides a semiconductor device 10 and a method for manufacturing the same, wherein after the epitaxial growth of the P-type semiconductor layer 17 in the semiconductor device 10 shown in fig. 3 is completed, an N-type semiconductor layer 18 is continuously formed between the gate 13 and the P-type semiconductor layer 17 by in-situ growth on the basis of the surface of the P-type semiconductor layer 17, so that an inverted N/P junction is formed between the P-type semiconductor layer 17 and the N-type semiconductor layer 18, and thus, while the peak electric field inside the P-GaN layer shown in fig. 1 is reduced and redistributed, and the implantation damage shown in fig. 2 is avoided, the gate leakage current can be further reduced, the gate bias voltage range is increased, and the reliability of the semiconductor device 10 is ensured. The scheme provided in the present embodiment is explained in detail below with reference to the drawings.
Example one
Referring to fig. 3 again, fig. 3 is a schematic cross-sectional structure diagram of a semiconductor device 10 according to an embodiment of the present disclosure, where the semiconductor device 10 includes a heterostructure including a substrate 14, a channel layer 15, a barrier layer 16, a P-type semiconductor layer 17, and an N-type semiconductor layer 18, and a source electrode 11, a drain electrode 12, and a gate electrode 13 connected to the heterostructure.
The base 14 includes a substrate 140 and a buffer layer 141 formed on the substrate 140, wherein the buffer layer 141 is located between the substrate 140 and the channel layer 15. Alternatively, the substrate 140 may be made of one of sapphire (sapphire), silicon carbide (SiC), silicon (Si), lithium niobate, silicon on insulator (soi), gallium nitride (GaN), aluminum nitride (AlN), and the like, or any other material suitable for growing group III nitride known to those skilled in the art, and the present application is not limited thereto. The buffer layer 141 may be grown on the substrate 140 using, but not limited to, an epitaxial growth process, and the buffer layer 141 may be, but is not limited to, a GaN material layer.
The channel layer 15 is formed based on the buffer layer 141 on the substrate 14, and may be made of, but not limited to, GaN material, the barrier layer 16 is formed based on the side of the channel layer 15 away from the substrate 14, and may be made of, but not limited to, AlGaN, AlN or InAlN, which are materials known to those skilled in the art of semiconductors and capable of forming two-dimensional electron gas with the GaN (channel layer 15), such as group III nitride semiconductor material. In actual implementation, a two-dimensional electron gas is formed between the channel layer 15 and the barrier layer 16, and disappears directly below the P-type semiconductor layer 17. It should be noted that, in the present embodiment, the dotted line shown in fig. 3 is a conductive channel formed in the channel layer 15 and used for providing a two-dimensional electron gas.
The P-type semiconductor layer 17 is formed on the side of the barrier layer 16 away from the channel layer 15, and may be made of, but not limited to, GaN or Al GaN material. The N-type semiconductor layer 18 is formed by in-situ growth on the surface of the P-type semiconductor layer 17 away from the barrier layer 16, and the N-type semiconductor layer 18 may be made of, but not limited to, GaN material, such as N/P junction material known to those skilled in the semiconductor arts that can form a reverse bias with the P-type semiconductor layer 17. In the embodiment of the present application, the formation of the N-type semiconductor layer 18 by in-situ growth means that the growth of the N-type semiconductor layer 18 is achieved by using the same growth environment and the same growth temperature as those of the P-type semiconductor layer 17, for example, if the P-type semiconductor layer 17 is grown by MOCVD at 950 to 1050 ℃, the N-type semiconductor layer 18 is also grown by MOCVD at 950 to 1050 ℃, so that the problem of Mg (magnesium) out-diffusion is effectively reduced, and the device performance of the semiconductor device 10 is improved.
In addition, the N-type semiconductor layer 18 may be doped with 1e17～1e19cm-3And in practical implementation, the thickness of the N-type semiconductor layer 18 may be 10nm to 200nm, such as 40nm, 45nm, 50nm, etc.
Further, the source electrode 11 and the drain electrode 12 are formed based on the fabrication of the channel layer 15 and are located at opposite ends of the barrier layer 16, and the gate electrode 13 is fabricated above the N-type semiconductor layer 18 and is in contact with the N-type semiconductor layer 18.
Further, in order to verify the performance of the semiconductor device 10 in the embodiment of the present application, please refer to fig. 4(a) -4 (b) and fig. 5(a) -5 (b) in combination, wherein fig. 4(a) is a schematic diagram of the edge profile of the conduction band in the P-GaN device shown in fig. 2 when the gate bias voltage is increased from 0V to 6V (the step value is 1V), from which it can be seen that the potential barrier on the barrier layer in the P-GaN device shown in fig. 2 disappears when the gate bias voltage is 0V and 6V shown in fig. 4(b), respectively. Fig. 5(a) is a schematic diagram of the conduction band edge profile in the semiconductor device shown in this application when the gate bias voltage is increased from 0V to 30V (step value of 3V), from which it can be seen that the potential barrier on the barrier layer in the semiconductor device 10 given in this application still exists when the gate bias voltage is 0V and 30V shown in fig. 5(b), respectively.
In addition, please refer to fig. 6(a) -6 (b) in combination, which are a performance simulation diagram of the P-GaN device shown in fig. 2 and a performance simulation diagram of the semiconductor device 10 provided in the present application, respectively, wherein, as can be seen from fig. 6(a), when the gate bias voltage (Vgs) of the P-GaN device provided in fig. 2 reaches the threshold voltage of 1V, the density of 2DEG (two-dimensional electron gas) reaches 2e12cm-2When the gate bias voltage continues to increase and reaches about 6V, the density of the 2DEG (two-dimensional electron gas) is 2e13cm-2And is saturated. As can be seen from fig. 6(b), when the gate bias voltage of the semiconductor device 10 given in the present application reachesThe density of 2DEG can reach 2e at a threshold voltage of 12V12cm-2However, if the density of the 2DEG is required to reach 2e13cm-2And saturates, the gate bias voltage can be increased to around 30V, which can be concluded that the semiconductor device 10 presented in this application has a larger gate voltage range.
In summary, compared with the scheme of forming an N-GaN layer between the gate 13 and the P-GaN layer based on the P-GaN layer and by ion implantation in the P-GaN device shown in fig. 2, in the first embodiment of the present application, after the epitaxial growth of the P-type semiconductor layer 17 is completed, the in-situ growth is continuously performed to form the N-type semiconductor layer 18 to obtain the stacked structure of the gate 13, the N-type semiconductor layer 18, and the P-type semiconductor layer 17, so that the problem of implantation damage caused by ion implantation can be effectively avoided. Meanwhile, compared with a reverse biased schottky junction, since a reverse biased N/P junction of ohmic contact can be formed between the N-type semiconductor layer 18 and the P-type semiconductor layer 17 in the application, the gate leakage current can be effectively reduced, the range of the voltage of the gate 13 of the semiconductor device 10 within the acceptable range of the gate leakage current is increased, even if the bias voltage of the gate 13 is adjusted to a higher value (such as 30V), the structures of the N-type semiconductor layer 18 and the P-type semiconductor layer 17 cannot be damaged, and two-dimensional electron gas can be maintained.
Example two
Fig. 7 is a schematic cross-sectional structure diagram of the semiconductor device 10 provided in the second embodiment of the present application, wherein, compared with the semiconductor device 10 shown in fig. 3, in the semiconductor device 10 provided in the second embodiment, the heterostructure may further include a low-temperature semiconductor cap layer 19 formed by in-situ growth on the basis of the surface of the N-type semiconductor layer 18 away from the P-type semiconductor layer 17, and the low-temperature semiconductor cap layer 19 is used for covering the intrinsic threading dislocation cavity on the crystalline semiconductor layer and the pit on the surface thereof, so as to eliminate the abnormal leakage path and reduce the leakage current.
Optionally, in actual implementation, the low-temperature semiconductor cap layer 19 may also be formed directly on the basis of the surface of the P-type semiconductor layer, and further, the N-type semiconductor layer 18 is formed on the basis of the surface of the low-temperature semiconductor cap layer 19 away from the P-type semiconductor layer 17, which is not limited in this embodiment.
It should be noted that the growth temperature used in the in-situ growth of the low-temperature semiconductor cap layer 19 is required to be lower than the growth temperature of the P-type semiconductor layer 17, for example, the formation temperature of the low-temperature semiconductor cap layer 19 may be, but is not limited to, 450 ℃ to 600 ℃, such as 480 ℃, 490 ℃, 520 ℃ and the like. Alternatively, the low temperature semiconductor cap layer 19 may be, but not limited to, an N-type GaN layer, and the thickness thereof may be, but not limited to, 2nm to 50nm, such as 10nm, 15nm, 20nm, etc.
EXAMPLE III
In the semiconductor device 10 shown in fig. 8 according to the third embodiment, compared with the first and second embodiments, a through hole may be formed in the N-type semiconductor layer 18, and the gate electrode 13 may be in contact with the P-type semiconductor layer 17 through the through hole. The through hole can be obtained by etching the N-type semiconductor layer 18, so as to introduce an N-type semiconductor guard ring into the semiconductor device 10, so that a schottky contact is formed between the gate 13 and the P-type semiconductor layer 17, and the schottky contact is used for controlling the gate 13 leakage current and the gate threshold voltage.
Similarly, when the semiconductor device 10 shown in fig. 7 includes the low temperature semiconductor cap layer 19, a via hole as shown in fig. 9 may be formed by simultaneously etching the N-type semiconductor layer 18 and the low temperature semiconductor cap layer 19, so that the gate 13 is in schottky contact with the P-type semiconductor layer 17 through the via hole for controlling the gate 13 leakage current and the gate threshold voltage.
It should be noted that when the etching of the through hole is performed to form the schottky contact between the gate 13 and the P-type semiconductor layer 17, the etching of the N-type semiconductor layer 18 may be stopped at the surface of the P-type semiconductor layer 17 as shown in fig. 8 and 9, or the etching of the N-type semiconductor layer 18 may be extended into the P-type semiconductor layer 17 and a groove 170 may be formed at the surface of the P-type semiconductor layer 17 as shown in fig. 10 and 11.
Example four
As shown in fig. 12, this embodiment also provides a method for manufacturing the semiconductor device 10, which is used for manufacturing the semiconductor device 10, and it should be noted that the method for manufacturing the semiconductor device 10 according to the present invention is not limited to the specific sequence shown in fig. 12 and described below. It should be understood that the order of some steps in the method for manufacturing the semiconductor device 10 according to the present invention may be interchanged according to actual needs, or some steps may be omitted or deleted, and the present embodiment is not limited herein.
Step S1, providing a substrate 14;
step S2, forming a channel layer 15 on the basis of the substrate 14;
step S3, forming a source 11, a drain 12 and a barrier layer 16 on one side of the channel layer 15, wherein the source 11 and the drain 12 are located at two ends of the barrier layer 16;
step S4, forming a P-type semiconductor layer 17 on the side of the barrier layer 16 away from the channel layer 15;
step S5, forming an N-type semiconductor layer 18 on the surface of the P-type semiconductor layer 17 away from the barrier layer 16 by in-situ growth;
in step S6, a gate 13 is formed on the surface of the N-type semiconductor layer 18 away from the P-type semiconductor layer 17.
It is understood that the semiconductor device 10 shown in fig. 3 can be manufactured through the process flows given in the above steps S1-S6, wherein the detailed description of the steps can refer to the description of the semiconductor device 10 in the above first embodiment, and the detailed description of the embodiment is omitted here.
According to practical requirements, as an embodiment, in order to fabricate the semiconductor device 10 shown in fig. 7, before performing the step of forming the gate electrode 13 on the side of the N-type semiconductor layer 18 away from the P-type semiconductor layer 17 in step S6, the fabrication method may further include: and continuing in-situ growth at the side of the N-type semiconductor layer 18 away from the P-type semiconductor layer 17 at a low temperature of 450-600 ℃ to obtain the low-temperature semiconductor cap layer 19 shown in fig. 7, wherein the thickness of the low-temperature semiconductor cap layer may be, but is not limited to, 2 nm-50 nm.
As another embodiment, in order to fabricate the semiconductor device 10 shown in fig. 8, before performing the step of forming the gate electrode 13 on the side of the N-type semiconductor layer 18 away from the P-type semiconductor layer 17 shown in step S6, the fabrication method may further include: the N-type semiconductor layer 18 is etched to form a through hole on the N-type semiconductor layer 18, so that the gate 13 formed based on the N-type semiconductor layer 18 can be in contact with the P-type semiconductor layer 17 through the through hole.
As still another embodiment, in order to fabricate the semiconductor device 10 shown in fig. 9, as shown in fig. 13, the step of fabricating and forming the gate electrode 13 on the side of the N-type semiconductor layer 18 away from the P-type semiconductor layer 17 shown in step S6 includes:
step S60, forming a low-temperature semiconductor cap layer 19 on the surface of the N-type semiconductor layer 18 far away from the P-type semiconductor layer 17 through in-situ growth;
step S61, etching the N-type semiconductor layer 18 and the low-temperature semiconductor cap layer 19 to form through holes on the N-type semiconductor layer 18 and the low-temperature semiconductor cap layer 19;
step S62, forming a gate 13 on the basis of the side of the low-temperature semiconductor cap layer 19 away from the N-type semiconductor layer 18, and the gate 13 is in contact with the P-type semiconductor layer 17 through the via hole.
In summary, in the semiconductor device 10 and the manufacturing method thereof provided in the embodiments of the present application, after the epitaxial growth of the P-type semiconductor layer 17 in the semiconductor device 10 is completed, the in-situ growth method is continuously adopted to manufacture and generate the N-type semiconductor layer 18 between the gate 13 and the P-type semiconductor layer 17, so that the N-type semiconductor layer 18 and the P-type semiconductor layer 17 jointly form a reverse N/P junction, thereby effectively reducing the leakage current, increasing the gate bias voltage, and ensuring that the semiconductor device 10 is in the normally-off state.
In addition, the present application further forms a low temperature semiconductor cap layer 19 on the N-type semiconductor layer 18 by in-situ growth to cover the semiconductor layer with intrinsic penetration dislocation and the pits on the surface thereof, thereby further reducing the leakage current.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A semiconductor device comprising a heterostructure and source, drain and gate electrodes connected to the heterostructure, the heterostructure comprising:
a substrate;
manufacturing a formed channel layer on the basis of the substrate;
manufacturing a formed barrier layer on the basis of one side of the channel layer away from the substrate;
manufacturing a formed P-type semiconductor layer on the basis of one side of the barrier layer away from the channel layer;
an N-type semiconductor layer formed by in-situ growth on the basis of the surface of the P-type semiconductor layer far away from the barrier layer;
the source electrode and the drain electrode are formed on the basis of the manufacture of the channel layer and are positioned at two opposite ends of the barrier layer, and the grid electrode is manufactured above the N-type semiconductor layer and is in contact with the N-type semiconductor layer.
2. The semiconductor device according to claim 1, wherein a through hole is formed in the N-type semiconductor layer, and the gate electrode is in contact with the P-type semiconductor layer through the through hole.
3. The semiconductor device according to claim 1, wherein the N-type semiconductor layer is doped with 1e17～1e19cm-3The thickness of the N-type semiconductor layer is 10 nm-200 nm.
4. The semiconductor device according to any one of claims 1 to 3, wherein the heterostructure further comprises a low-temperature semiconductor cap layer formed by in-situ growth based on a surface of the N-type semiconductor layer away from the P-type semiconductor layer; or,
and a low-temperature semiconductor cap layer which is formed on the basis that the P-type semiconductor layer is close to the surface of the N-type semiconductor layer and is grown in situ.
5. The semiconductor device according to claim 4, wherein the formation temperature of the low-temperature semiconductor cap layer is 450 ℃ to 600 ℃.
6. The semiconductor device according to claim 4, wherein the thickness of the low-temperature semiconductor cap layer is 2nm to 50 nm.
7. The semiconductor device according to claim 1, wherein the base includes a substrate, and a buffer layer formed on the basis of the substrate fabrication, the buffer layer being located between the substrate and the channel layer.
8. A method for manufacturing a semiconductor device, the method comprising:
providing a substrate;
forming a channel layer on the basis of the substrate;
manufacturing and forming a source electrode, a drain electrode and a barrier layer on one side of the channel layer, wherein the source electrode and the drain electrode are respectively positioned at two ends of the barrier layer;
manufacturing and forming a P-type semiconductor layer on one side of the barrier layer away from the channel layer;
forming an N-type semiconductor layer on the surface of the P-type semiconductor layer far away from the barrier layer through in-situ growth;
and manufacturing and forming a grid on the surface of the N-type semiconductor layer far away from the P-type semiconductor layer.
9. The method for manufacturing a semiconductor device according to claim 8, wherein before the step of forming a gate electrode on the surface of the N-type semiconductor layer away from the P-type semiconductor layer, the method further comprises:
and etching the N-type semiconductor layer to form a through hole on the N-type semiconductor layer, so that a grid electrode manufactured and formed on the basis of the N-type semiconductor layer can be in contact with the P-type semiconductor layer through the through hole.
10. The method for manufacturing a semiconductor device according to claim 8, wherein the step of forming a gate electrode on the surface of the N-type semiconductor layer away from the P-type semiconductor layer comprises:
forming a low-temperature semiconductor cap layer on the surface of the N-type semiconductor layer far away from the P-type semiconductor layer through in-situ growth;
etching the N-type semiconductor layer and the low-temperature semiconductor cap layer to form through holes on the N-type semiconductor layer and the low-temperature semiconductor cap layer;
and manufacturing and forming a grid electrode on the basis of one side of the low-temperature semiconductor cap layer, which is far away from the N-type semiconductor layer, and enabling the grid electrode to be in contact with the P-type semiconductor layer through the through hole.
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