CN110008145B

CN110008145B - Data protection method, memory control circuit unit and memory storage device

Info

Publication number: CN110008145B
Application number: CN201810011370.3A
Authority: CN
Inventors: 叶志刚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2018-01-05
Filing date: 2018-01-05
Publication date: 2022-10-21
Anticipated expiration: 2038-01-05
Also published as: CN110008145A

Abstract

The invention provides a data protection method, a memory control circuit unit and a memory storage device. The method includes generating a first temporary parity group based on first data written to a first super-physical unit; performing a logical operation on the second data written to the second super-physical unit and the first temporary parity group to generate a second temporary parity group; and performing a logical operation on the second temporary parity and the first data to generate an updated parity group when all data of the first super-physical unit is invalid.

Description

Data protection method, memory control circuit unit and memory storage device

Technical Field

The invention relates to a data protection method for a rewritable nonvolatile memory, a memory control circuit unit using the method and a memory storage device.

Background

Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable nonvolatile memory module (e.g., flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices as described above.

Generally, the rewritable nonvolatile memory module includes a plurality of super-physical units, the physical erase unit of each super-physical unit includes a plurality of physical programming units, and each super-physical unit may have a plurality of super-physical programming units. That is, one of the super-physical programming units of each super-physical unit is composed of one of the physical programming units of each physical erasing unit of each super-physical unit. In particular, different ones of the one of the super-physical cells may be programmed simultaneously or partially simultaneously.

Take an example that a plurality of physical erase units included in a super-physical unit belong to 8 different memory planes (i.e. planes). In the prior art, when data stored in a rewritable nonvolatile memory module is protected, each entity erasing unit belonging to different memory planes in the rewritable nonvolatile memory module is protected by a group of parity check codes. For example, when a write command is received to write data into a super-physical unit, parity codes for protecting the data are generated based on the data in each physical erase unit while the data are being written into the super-physical unit. Since the physically erased cells are used as protection cells, the generated parity check codes need to be stored in one physically erased cell. That is, when parity codes are configured by grouping 8 physically erasable units belonging to different memory planes, one physically erasable unit is required to store parity codes, so that the total storage space is reduced by 1/8.

Based on the above, the prior art needs a large amount of storage space to use the physically erased cells as the data protection unit. However, since the storage space of the rewritable nonvolatile memory module is limited, how to maintain the reliability of the stored data while reducing the data amount of the stored parity code is a subject of attention of those skilled in the art.

Disclosure of Invention

The invention provides a data protection method, a memory control circuit unit and a memory storage device. The method not only effectively protects the data stored in the rewritable nonvolatile memory module, but also protects a certain number of super entity units, thereby saving the space required by the storage of the parity check code.

An exemplary embodiment of the present invention provides a data protection method for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of super entity units. The data protection method comprises the following steps: writing first data to the first super entity unit; generating a first temporary parity block based on the first data; writing second data into the second super entity unit; the second data and the first temporary parity group are subjected to a logical operation to generate a second temporary parity group. In addition, the data protection method further includes performing a logic operation on the second temporary parity group and the first data stored in the first super-physical unit to generate an updated parity group when all data of the first super-physical unit is invalid.

In an exemplary embodiment of the invention, the data protection method further includes: associating the first and second super entity units as a first array of entity units; and using the updated parity code group as a first parity code group of the first physical unit array.

In an exemplary embodiment of the invention, the data protection method further includes: writing third data into a third super-physical unit of the plurality of super-physical units before all data of the first super-physical unit of the first physical unit array is invalid data; and performing a logical operation on the third data and the second temporary parity group to generate a third temporary parity group.

In an exemplary embodiment of the invention, the first super-physical unit includes a plurality of physically erased units, the physically erased units of the first super-physical unit respectively include a plurality of physically programmed units, and each of the physically erased units of the first super-physical unit belongs to a different memory plane.

In an exemplary embodiment of the invention, the data protection method further includes: merging the super entity unit of the first entity unit array and the super entity unit of the other entity unit array into a new entity unit array; and taking the value obtained by performing the logical operation on the first parity code group of the first physical unit array and the other parity code group of the other physical unit array as a new parity code group corresponding to the new physical unit array.

In an exemplary embodiment of the invention, the number of the super-entity cells associated with the first entity cell array is not greater than a predefined threshold, the number of the super-entity cells associated with the other entity cell array is not greater than a predefined threshold, and the number of the super-entity cells associated with the new entity cell array is not greater than a predefined threshold.

In an exemplary embodiment of the invention, the logic operation is an XOR operation.

An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is used for electrically connecting to a host system. The memory interface is electrically connected to the rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of super entity units. The memory management circuit is electrically connected to the host interface and the memory interface. Here, the memory management circuit is configured to write the first data to the first super-physical unit. The memory management circuit is further configured to generate a first set of temporary parity blocks based on the first data, write the second data to the second super-physical unit, and perform a logical operation on the second data and the first set of temporary parity blocks to generate a second set of temporary parity blocks. In addition, the memory management circuit is further configured to perform a logical operation on the second temporary parity block and the first data stored in the first super-physical unit to generate an updated parity block when all data of the first super-physical unit is invalid.

In an example embodiment of the present invention, a memory management circuit is configured to associate a first super-entity cell and a second super-entity cell as a first entity cell array; and a memory management circuit for using the updated parity block as a first parity block for the first physical unit array.

In an exemplary embodiment of the invention, before all data of the first super-physical unit of the first physical unit array is invalid data, the memory management circuit is further configured to write third data into a third super-physical unit, and perform a logic operation on the third data and the second temporary parity group to generate a third temporary parity group.

In an exemplary embodiment of the invention, the memory management circuit is further configured to merge the super-solid unit of the first solid unit array and the super-solid unit of the another solid unit array into a new solid unit array, and use a value obtained by performing a logical operation on the first parity group of the first solid unit array and the first parity group of the another solid unit array as the first parity group corresponding to the new solid unit array.

An exemplary embodiment of the present invention provides a memory storage device, which includes a connector, a rewritable nonvolatile memory module and a memory control circuit unit. The connector is used for electrically connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of super entity units. The memory control circuit unit is electrically connected to the connector and the rewritable nonvolatile memory module. The memory control circuit unit is configured to write first data into the first super-entity unit, generate a first temporary parity group according to the first data, write second data into the second super-entity unit, and perform a logical operation on the second data and the first temporary parity group to generate a second temporary parity group. In addition, the memory control circuit unit is further configured to perform a logic operation on the second temporary parity group and the first data stored in the first super-physical unit to generate an updated parity group when all the data of the first super-physical unit is invalid.

In an exemplary embodiment of the invention, the memory control circuit unit is configured to associate the first super physical unit and the second super physical unit into a first physical unit array; and the memory control circuit unit is used for using the updated parity code group as a first parity code group of the first physical unit array.

In an exemplary embodiment of the invention, before all data of the first super-physical unit of the first physical unit array is invalid data, the memory control circuit unit is further configured to write third data into the third super-physical unit, and perform a logic operation on the third data and the second temporary parity group to generate a third temporary parity group.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to merge the super-entity unit of the first entity unit array and the super-entity unit of the other entity unit array into a new entity unit array, and use a value obtained by performing a logical operation on the first parity group of the first entity unit array and the other parity group of the other entity unit array as a new parity group corresponding to the new entity unit array.

Based on the above, the data protection method, the memory control circuit unit and the memory storage device according to the exemplary embodiments of the present invention can recover the data stored in the entity erasing unit having an error by using the data of other entity erasing units and the generated parity, so as to effectively protect the data stored in the rewritable nonvolatile memory module, and also protect a certain number of super entity units by using the parity code group, and simultaneously save the space required for storing the parity.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another example embodiment;

FIG. 4 is a schematic block diagram illustrating a host system and a memory storage device according to an example embodiment;

FIG. 5 is a schematic block diagram illustrating a memory control circuit module according to an example embodiment;

FIG. 6 is a schematic block diagram illustrating a super entity unit in accordance with an exemplary embodiment of the present invention;

FIGS. 7-10 are schematic diagrams illustrating writing data to a super entity unit according to an example embodiment of the invention;

FIG. 11 is a schematic diagram illustrating a first physical cell array in accordance with an exemplary embodiment of the present invention;

FIGS. 12 and 13 are diagrams illustrating generation of updated parity code groups according to an exemplary embodiment of the present invention;

FIGS. 14-16 are schematic diagrams illustrating a physical cell array merge operation performed in accordance with an exemplary embodiment of the present invention;

FIG. 17 is a flowchart illustrating a data protection method according to an example embodiment of the present invention;

fig. 18 is a flowchart illustrating a data protection method according to another example embodiment of the present invention;

fig. 19 is a flowchart illustrating a data protection method according to another example embodiment of the present invention.

Description of the reference numerals

10: a memory storage device;

11: a host system;

12: input/output (I/O) devices;

110: a system bus;

111: a processor;

112: random Access Memory (RAM);

113: read Only Memory (ROM);

114: a data transmission interface;

20: a main board;

201: a U disk;

202: a memory card;

203: a solid state disk;

204: a wireless memory storage device;

205: a global positioning system module;

206: a network interface card;

207: a wireless transmission device;

208: a keyboard;

209: a screen;

210: a horn;

30: a memory storage device;

31: a host system;

32: an SD card;

33: a CF card;

34: an embedded storage device;

341: an embedded multimedia card;

342: an embedded multi-chip package storage device;

402: a connection interface unit;

404: a memory control circuit unit;

406: a rewritable non-volatile memory module;

502: a memory management circuit;

504: a host interface;

506: a memory interface;

508: a buffer memory;

510: a power management circuit;

512: an error checking and correcting circuit;

310. 320, 330, 340, 430, 440: a super entity unit;

3101. 3102, 3103, 3104, 3105, 3106, 3107, 3108: a physical erase unit;

31011. 31021, 31031, 31041, 31051, 31061, 31071, 31081: a physical programming unit;

311. 312, 313, 314, 315, 316, 321, 322, 323, 324, 325, 326, 331, 332, 333, 334, 335, 336, 341, 342, 343, 344, 345, 346: a super-entity programming unit;

d1: first data;

d2: a second data;

d3: third data;

d4: fourth data;

p1: a first temporary parity code group;

p2: a second temporary parity group;

p3: a third temporary parity code group;

p4: a fourth temporary parity block;

PA, PC: a first parity code group;

PA': a first updated parity group;

PA': a second updated parity code group;

PB: a second parity code group;

r1: a first array of physical units;

r2: a second physical array;

r3: a new physical cell array;

s1701: writing the first data into a first super entity unit of the plurality of super entity units of the rewritable nonvolatile memory module 406;

s1703: a step of generating a first temporary parity group based on the first data;

s1705: writing the second data into a second super entity unit of the plurality of super entity units of the rewritable nonvolatile memory module 406;

s1707: a step of performing a logical operation on the second data and the first temporary parity group to generate a second temporary parity group;

s1801: a step of executing valid data merging operation on the first super entity unit;

s1803: judging whether all the data of the first super entity unit are invalid data;

s1805: a step of performing a logical operation on the second temporary parity group with the first data stored in the first super physical unit to generate an updated parity group;

s1901: associating the first super entity unit and the second super entity unit as a first entity unit array;

s1903: a step of setting the updated parity block as a first parity block of the first physical unit array;

s1905: merging the entity erasing unit of the first entity unit array and the entity erasing unit of the other entity unit array into a new entity unit array;

s1907: and a step of setting a value obtained by performing a logical operation on the first parity code group of the first physical unit array and the other parity code group of the other physical unit array as a new parity code group corresponding to the new physical unit array.

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module and a controller (also referred to as a control circuit unit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

Fig. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment, and fig. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 are all electrically connected to a system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 over the system bus 110.

In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 are disposed on the motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. The motherboard 20 may be electrically connected to the memory storage device 10 through the data transmission interface 114 by wire or wirelessly. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory Storage device 204 can be a memory Storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory Storage device, wireless facsimile (WiFi) memory Storage device, bluetooth (Bluetooth) memory Storage device, or Bluetooth low energy memory Storage device (e.g., iBeacon). In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded Multi-media cards (eMMC) 341 and/or embedded Multi-Chip Package memory devices (eMCP) 342, and various types of embedded memory devices electrically connecting the memory module to the substrate of the host system.

FIG. 4 is a schematic block diagram illustrating a host system and a memory storage device according to an example embodiment.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

In the exemplary embodiment, the connection interface unit 402 is compatible with Secure Digital (SD) interface standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to Serial Advanced Technology Attachment (SATA) standard, parallel Advanced Technology Attachment (PATA) standard, institute of Electrical and Electronic Engineers (IEEE) 1394 standard, high-Speed Peripheral Component connection interface (PCI Express) standard, universal Serial Bus (USB) standard, ultra High Speed-I (UHS-I) interface standard, ultra High Speed secondary (Ultra High Speed-II, UHS-II) interface standard, memory Stick (MS) interface standard, multi-Chip Package (Multi-Chip Package) interface standard, multimedia Memory Card (MMC) interface standard, embedded Multimedia Memory Card (eMMC) interface standard, universal Flash Storage (UFS) interface standard, embedded Multi-Chip Package (eMCP) interface standard, compact Flash (CF) interface standard, integrated Device Electronics (IDE) standard, or other suitable standard. In the present exemplary embodiment, the connection interface unit 402 and the memory control circuit unit 404 may be packaged in one chip, or the connection interface unit 402 is disposed outside a chip including the memory control circuit module.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a solid state type, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable non-volatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.

FIG. 5 is a schematic block diagram of a memory control circuit block shown in accordance with an example embodiment.

Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504 and a memory interface 506.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10.

In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in a solid state form. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a driver, and when the memory control circuit 404 is enabled, the microprocessor first executes the driver to load the control command stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 can also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the entity erasing unit of the rewritable nonvolatile memory module 406; the memory writing circuit is used for issuing a writing instruction to the rewritable nonvolatile memory module 406 so as to write data into the rewritable nonvolatile memory module 406; the memory reading circuit is used for sending a reading instruction to the rewritable nonvolatile memory module 406 so as to read data from the rewritable nonvolatile memory module 406; the memory erasing circuit is used for issuing an erasing instruction to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406; the data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406.

The host interface 504 is electrically connected to the memory management circuit 502 and is electrically connected to the connection interface unit 402 for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data sent from the host system 11 are sent to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the UHS-I interface standard, the UHS-II interface standard, the SD standard, the MS standard, the MMC standard, the CF standard, the IDE standard, or other suitable data transfer standards.

The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 508, a power management circuit 510 and an error checking and correcting circuit 512.

The buffer memory 508 is electrically connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406.

The power management circuit 510 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.

The error checking and correcting circuit 512 is electrically connected to the memory management circuit 502 and is used for performing an error checking and correcting process to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the Error Checking and Correcting circuit 512 generates a corresponding Error Checking and Correcting Code (ECC Code) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC Code into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the corresponding error checking and correcting codes are simultaneously read, and the error checking and correcting circuit 512 performs an error checking and correcting process on the read data according to the error checking and correcting codes.

In the exemplary embodiment, the error checking and correcting circuit 512 is implemented by a low density parity check code (LDPC). However, in another exemplary embodiment, the error checking and correcting circuit 512 may also be implemented with BCH code, convolutional code (convolutional code), turbo code (turbo code), bit flipping (bit flipping), and other encoding/decoding algorithms.

Specifically, the memory management circuit 202 generates an error correction Frame (ECC Frame) according to the received data and corresponding error checking and correcting codes (hereinafter also referred to as error correction codes) and writes the ECC Frame into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error checking and correcting circuit 512 verifies the correctness of the read data according to the error correction codes in the error correction code frame.

Operations performed by the memory management circuit 502, the host interface 504 and the memory interface 506, the buffer memory 508, the power management circuit 510, and the error checking and correcting circuit 512 are described below, and may also be referred to as being performed by the memory control circuit unit 404.

In the present exemplary embodiment, the rewritable nonvolatile memory module 406 includes a plurality of physically erased cells and each physically erased cell includes a plurality of physically programmed cells. In particular, the memory management circuit 502 combines a plurality of physical erase units belonging to different memory planes (planes) into a super-physical unit for performing operations (e.g., data writing operation, data erasing operation), and each super-physical program unit of the super-physical unit is composed of one of the physical program units of each physical erase unit.

FIG. 6 is a schematic block diagram of a super-entity unit in accordance with an exemplary embodiment of the present invention.

Referring to fig. 6, a super entity unit 310 is taken as an example for explanation. Memory management circuit 502 groups physical erase cells 3101, physical erase cells 3102, physical erase cells 3103, physical erase cells 3104, physical erase cells 3105, physical erase cells 3106, physical erase cells 3107, and physical erase cells 3108 (hereinafter referred to as physical erase cells 3101-3108) into super-physical cells 310.

More specifically, as shown in FIG. 6, the entity programming unit 31011 of the entity erasing unit 3101, the entity programming unit 31021 of the entity erasing unit 3102, the entity programming unit 31031 of the entity erasing unit 3103, the entity programming unit 31041 of the entity erasing unit 3104, the entity programming unit 31051 of the entity erasing unit 3105, the entity programming unit 31061 of the entity erasing unit 3106, the entity programming unit 31071 of the entity erasing unit 3107 and the entity programming unit 31081 of the entity erasing unit 3108 together form the super entity programming unit 311 of the super entity unit 310. In the present exemplary embodiment, the physically erased cells included in the super-entity cells 310 belong to different memory planes, so that different ones of the super-entity programmed cells 311 of the super-entity cells 310 can be programmed at the same time.

In the present exemplary embodiment, for convenience of description, in the present exemplary embodiment, each of the

super entity cells

310, 320, 330, 340 (hereinafter, referred to as super entity cells 310 to 340) includes 6 super entity programming cells, but the present invention is not limited thereto.

Specifically, the super entity unit 310 includes super entity programming units 311 to 316. The super entity unit 320 includes super entity program units 321 to 326. The super entity unit 330 includes super entity programming units 331-336. The super entity unit 340 includes super entity programming units 341-346.

Fig. 7-10 are schematic diagrams illustrating writing data to a super-physical unit according to an exemplary embodiment of the invention.

Referring to fig. 7 to 10, it is assumed that the memory control circuit unit 404 receives a write command and first data D1 corresponding to the write command from the host system 11, and writes the first data D1 into the super entity unit 310 of the rewritable nonvolatile memory module 406. Here, the memory management circuit 502 divides the first data D1 into a plurality of sub-data according to the size of the super entity programming unit, and sequentially writes the sub-data according to the size of the super entity programming unit into the super entity programming units 311 to 316 in the super entity unit 310.

While the memory management circuit 502 sequentially writes the sub-data of the first data D1 conforming to the size of the "super-entity programming unit" into the super-entity programming units 311 to 316 of the super-entity unit 310, a plurality of first temporary parity codes respectively corresponding to the sub-data of the first data D1 are generated according to the sub-data of the first data D1, and the first temporary parity codes form a first temporary parity code group P1.

When the memory management circuit 502 is to write the second data D2 into the super entity unit 320 of the rewritable non-volatile memory module 406, the memory management circuit 502 divides the second data D2 into a plurality of sub-data according to the size of the super entity programming unit, and sequentially writes the sub-data according to the size of the super entity programming unit into the super entity programming units 321 to 326 of the super entity unit 320.

While the memory management circuit 502 sequentially writes the sub-data of the second data D2 corresponding to the size of the "super-entity programming unit" into the super-entity programming units 321 to 326 in the super-entity unit 320, the memory management circuit 502 performs a logic operation on the sub-data of the second data D2 sequentially written into the super-entity programming units 321 to 326 in the super-entity unit 320 and the first temporary parity codes of the first temporary parity code group P1 to generate a plurality of second temporary parity codes, respectively, and the second temporary parity codes form the second temporary parity code group P2. Here, the logical operation is, for example, an XOR operation.

Referring to fig. 9, when the memory management circuit 502 is to write the third data D3 into the super entity unit 330 of the rewritable nonvolatile memory module 406, the memory control circuit unit 404 divides the third data D3 into a plurality of sub-data according to the size of the super entity programming unit, and sequentially writes the sub-data conforming to the size of the super entity programming unit into the super entity programming units 331 to 336 in the super entity unit 330.

While the memory management circuit 502 sequentially writes the sub-data of the third data D3 corresponding to the size of the "super-entity programming unit" into the super-entity programming units 331 to 336 in the super-entity unit 330, the memory management circuit 502 performs a logic operation on the sub-data of the third data D3 sequentially written into the super-entity programming units 331 to 336 in the super-entity unit 330 and the second temporary parity codes of the second temporary parity code group P2 to generate a plurality of third temporary parity code groups P3.

Similarly, when the memory management circuit 502 is about to write the fourth data D4 into the super entity unit 340 of the rewritable nonvolatile memory module 406, the memory management circuit 502 divides the fourth data D4 into a plurality of sub-data according to the size of the "super entity programming unit" and sequentially writes the plurality of sub-data conforming to the size of the "super entity programming unit" into the super entity programming units 341 to 346 in the super entity unit 340.

While the memory management circuit 502 sequentially writes the sub-data of the fourth data D4 corresponding to the size of the super-entity programming unit into the super-entity programming units 341 to 346 in the super-entity unit 340, the memory management circuit 502 performs a logic operation on the sub-data of the fourth data D4 sequentially written into the super-entity programming units 341 to 346 in the super-entity unit 340 and the third temporary parity codes of the third temporary parity code group P3 to generate a plurality of fourth temporary parity code groups P4.

In particular, in the exemplary embodiment, the memory management circuit 502 associates a plurality of super-physical units associated with the calculated temporary parity groups into a physical unit array and stores the corresponding parity groups, so as to correct the error bits through the stored parity groups when the data in any super-physical unit in the physical unit array cannot be corrected.

Fig. 11 is a schematic diagram illustrating a physical cell array according to an exemplary embodiment of the invention.

In the present exemplary embodiment, memory management circuit 502 associates super physical units 310-340 as a first physical unit array R1. A plurality of fourth temporary parity codes of the fourth temporary parity code group P4 are used as a plurality of first parity codes of the first physical unit array R1, and these first parity codes constitute the first parity code group PA of the first physical unit array R1.

In the present exemplary embodiment, when an error bit occurs in any one of the super-physical units 310-340 of the first physical unit array R1, the data originally stored in the physical erase unit in which the error bit occurs can be obtained according to the data stored in other physical erase units and the first parity check code group PA of the first physical unit array R1, so as to correct the error bit. For example, if there are too many error bits in the data stored in the erase block 3101 of the super-entity unit 310, the data originally stored in the erase block 3101 of the super-entity unit 310 can be obtained according to the data stored in the erase blocks 3102 to 3108 of the super-entity unit 310 and the first parity code group PA. That is, the first parity code group PA of the first physical cell array R1 can protect the super physical cells 310-340 associated with the first physical cell array R1, and even if the data on any one of the physical erase cells has too many error bits, the data stored on the physical erase cell can still be recovered.

Fig. 12 and 13 are diagrams illustrating generation of an updated parity group according to an exemplary embodiment of the invention.

Referring to fig. 12 and 13, in the present exemplary embodiment, when the first data D1 written into the super cell 310 of the first physical cell array R1 are all invalid data, all the invalid data of the super cell 310 needs to be deleted. The memory management circuit 502 performs the logical operation on the first parity of the first parity group PA of the first physical cell array R1 and the sub-data of the first data D1 stored in the super physical cell 310 of the first physical cell array R1 to generate a plurality of first update parity codes, and the first update parity codes form a first update parity group PA'. Thereafter, the memory management circuit 502 performs an erase operation on the super physical unit 310 of the first physical unit array R1. That is, the first data D1 stored in the super entity programming cells 311-316 of the super entity cells 310 of the first entity cell array R1 is deleted. At this time, since super entity unit 310 is a null super entity unit, memory management circuit 502 re-associates other non-null super entity units 320-340 with first entity unit array R1, and uses the first updated parity code group PA' as the first parity code group PA of the re-associated first entity unit array R1.

Similarly, when the second data D2 of the super cells 320 of the first physical cell array R1 are all invalid data, all the invalid data of the super cells 320 need to be deleted. The memory management circuit 502 performs the logical operation on the plurality of first parity codes (i.e., the plurality of first update parity codes of the first parity code group PA' of the first physical unit array R1) and the plurality of sub-data of the second data D2 stored in the super physical unit 320 of the first physical unit array R1 to generate a plurality of second update parity codes, and the second update parity codes form a second update parity code group PA ″. Thereafter, the memory management circuit 502 performs an erase operation on the super physical unit 320 of the first physical unit array R1. That is, the second data D2 stored in the super cells 321-326 of the super cell 320 of the first solid cell array R1 is erased. At this time, super entity unit 320 is an empty super entity unit, and memory management circuit 502 re-associates other non-empty

super entity units

330 and 340 with first entity unit array R1, and uses the second updated parity code group PA ″ as the first parity code group PA of the re-associated first entity unit array R1.

It is worth mentioning that, in an exemplary embodiment, when the number of super-physical cells of the plurality of physical cell arrays is smaller than the predefined threshold, the memory management circuit 502 performs the physical cell array merging operation. Here, the predefined threshold may be considered as a maximum number of super-solid cells that can be associated with a solid cell array. For example, the predefined threshold is set to 4, i.e., the number of super-physical units associated with a physical unit array is not greater than 4.

FIGS. 14-16 are diagrams illustrating a physical cell array merge operation performed according to an exemplary embodiment of the invention.

Referring to fig. 14, the second physical array R2 includes a super physical unit 430 and a super physical unit 440.

In the present exemplary embodiment, the sub-data associated with the super entity unit 430 and the super entity unit 440 of the second entity array R2 are logically operated to generate a plurality of second parity codes corresponding to the second parity code group PB of the second entity array R2.

As described above, invalid data of

super entity units

310 and 320 are deleted, only

super entity units

330 and 340 are associated with first entity array R1, and first parity group PA of first entity unit array R1 only protects

super entity units

330 and 340. To avoid the redundant parity codes wasting storage space, the memory management circuit 502 may merge the super-entity units of the first entity array R1 and the super-entity units of the second entity array R2 into a new entity unit array R3, perform a logical operation on the first parity code group PA (i.e., the second updated parity code group PA ") of the first entity array R1 and the second parity code group PB of the second entity array R2 to obtain a plurality of new parity codes, and use the first parity code group PC formed by the plurality of new parity codes as the first parity code group PC corresponding to the new entity unit array R3, and then the memory management circuit 502 may delete the first parity code group PA and the second parity code group PB.

By the above mode, not only can the number of the super entity units associated to the entity unit array be ensured not to be larger than the predefined threshold value, but also the parity check code group can be ensured to protect the most super entity units, and redundant parity check code groups can be deleted to avoid wasting the storage space.

It should be noted that although the exemplary embodiment of the invention is described by taking the example that the rewritable nonvolatile memory module 406 includes two physical cell arrays, each of the physical cell arrays includes 4 super-physical cells, and each of the super-physical cells includes 6 super-physical programming cells. But the invention is not limited thereto. In other embodiments, the rewritable nonvolatile memory module 406 may also include more or less physical cell arrays, each physical cell array may also include more or less super-physical cells, and each super-physical cell may also include more or less super-physical programming cells.

Fig. 17 is a flowchart illustrating a data protection method according to an exemplary embodiment of the present invention.

Referring to fig. 17, in step S1701, the memory management circuit 502 writes the first data into a first super-entity unit of the plurality of super-entity units of the rewritable nonvolatile memory module 406.

In step S1703, the memory management circuit 502 generates a first temporary parity group according to the first data. In step S1705, the memory management circuit 502 writes the second data into a second super entity unit of the plurality of super entity units of the rewritable non-volatile memory module 406.

In step S1707, the memory management circuit 502 performs a logical operation on the second data and the first temporary parity block to generate a second temporary parity block.

Fig. 18 is a flowchart illustrating a data protection method according to another example embodiment of the present invention.

In step S1801, the memory management circuit 502 performs a valid data merge operation on the first super entity unit, and in step S1803, determines whether all data of the first super entity unit are invalid data.

If all the data of the first super-physical unit is invalid, in step S1805, the memory management circuit 502 performs a logic operation on the first parity block and the first data stored in the first super-physical unit to generate an updated parity block.

Referring to fig. 19, in step S1901, the memory management circuit 502 associates the first super physical unit and the second super physical unit into a first physical unit array. In step S1903, the memory management circuit 502 sets the updated parity code group as the first parity code group of the first physical unit array. In step S1905, the memory management circuit 502 merges the physical erase cells of the first physical cell array and the physical erase cells of the other physical cell array into a new physical cell array. In step S1907, the memory management circuit 502 uses the value obtained by performing a logical operation on the first parity group of the first physical unit array and the first parity group of the other physical unit array as a new parity group corresponding to the new physical unit array.

In summary, the data protection method, the memory control circuit unit and the memory storage device of the present invention can recover the data stored in the entity erasing unit with the error bit by using the data of other entity erasing units and the generated parity code group when any entity erasing unit has too many error bits, thereby not only effectively protecting the data stored in the rewritable nonvolatile memory module, but also protecting a certain number of super entity units by using the parity code group, and saving the storage space required by the parity code group.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A data protection method is used for a rewritable nonvolatile memory module, the rewritable nonvolatile memory module comprises a plurality of super entity units, and the data protection method comprises the following steps:

writing first data to a first super entity unit among the plurality of super entity units;

generating a first temporary parity group based on the first data;

writing second data to a second super entity unit among the plurality of super entity units;

performing a logical operation on the second data and the first set of temporary parity blocks to generate a second set of temporary parity blocks;

associating the first and second super entity units as a first array of entity units;

setting the second temporary parity group as the first parity group for the first physical unit array; and

when all data of the first super-physical unit is invalid data, performing the logical operation on the first parity group and the first data stored in the first super-physical unit to generate an updated parity group.

2. The data protection method of claim 1, further comprising:

using the updated parity code group as the first parity code group of the first physical unit array.

3. The data protection method of claim 2, further comprising:

writing third data into a third super physical unit of the plurality of super physical units before all data of a first super physical unit of the first physical unit array is invalid data; and

performing the logical operation on the third data and the second temporary parity group to generate a third temporary parity group.

4. The data protection method of claim 1, wherein the first super-physical cell includes a plurality of physically erased cells, the physically erased cells of the first super-physical cell respectively include a plurality of physically programmed cells, and each physically erased cell of the first super-physical cell belongs to a different memory plane.

5. The data protection method of claim 2, further comprising:

merging the super entity unit of the first entity unit array and the super entity unit of the other entity unit array into a new entity unit array;

and taking the value obtained by performing the logical operation on the first parity code group of the first physical unit array and the other parity code group of the other physical unit array as a new parity code group corresponding to the new physical unit array.

6. The data protection method of claim 5, wherein the number of super entity units associated with the first array of entity units is not greater than a predefined threshold, the number of super entity units associated with the other array of entity units is not greater than the predefined threshold, and the number of super entity units associated with the new array of entity units is not greater than the predefined threshold.

7. The data protection method of claim 1, wherein the logical operation is an XOR operation.

8. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:

a host interface for electrically connecting to a host system;

a memory interface electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of super entity units; and

a memory management circuit electrically connected to the host interface and the memory interface,

wherein the memory management circuitry is to write first data into a first super-physical cell among the plurality of super-physical cells;

wherein the memory management circuitry is to generate a first set of temporary parity blocks from the first data;

wherein the memory management circuitry is to write second data into a second super-entity cell among the plurality of super-entity cells;

wherein the memory management circuitry is to perform a logical operation on the second data and the first set of temporary parity blocks to generate a second set of temporary parity blocks;

wherein the memory management circuitry is to associate the first and second super-entity cells as a first array of entity cells;

wherein the memory management circuitry is to use the second temporary parity code group as a first parity code group for the first array of physical units; and

when all data of the first super-physical unit is invalid data, the memory management circuit is configured to perform the logic operation on the first parity block and the first data stored in the first super-physical unit to generate an updated parity block.

9. The memory control circuit cell of claim 8,

the memory management circuit is configured to use the updated parity code group as the first parity code group of the first physical unit array.

10. The memory control circuit cell of claim 9,

wherein the memory management circuit is configured to write third data into a third super physical unit of the plurality of super physical units before all data of the first super physical unit of the first physical unit array is invalid data; and

wherein the memory management circuitry is further to perform the logical operation on the third data and the second set of temporary parity blocks to generate a third set of temporary parity blocks.

11. The memory control circuit unit of claim 8, wherein the first super-physical unit comprises a plurality of physically erased units, the physically erased units of the first super-physical unit respectively comprise a plurality of physically programmed units, and each physically erased unit of the first super-physical unit belongs to a different memory plane.

12. The memory control circuit unit of claim 9,

the memory management circuit is used for merging the super entity unit of the first entity unit array and the super entity unit of the other entity unit array into a new entity unit array;

wherein the memory management circuit is configured to use a value obtained by performing the logical operation on the first parity code group of the first physical unit array and the other parity code group of the other physical unit array as a new parity code group corresponding to the new physical unit array.

13. The memory control circuit cell of claim 12,

wherein the number of super-entity cells associated with the first array of entity cells is not greater than a predefined threshold, the number of super-entity cells associated with the other array of entity cells is not greater than the predefined threshold, and the number of super-entity cells associated with the new array of entity cells is not greater than the predefined threshold.

14. A memory storage device, comprising:

a connector for electrically connecting to a host system;

the rewritable nonvolatile memory module comprises a plurality of super entity units; and

a memory control circuit unit electrically connected to the connector and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to write first data to a first super-entity unit among the plurality of super-entity units;

wherein the memory control circuit unit is configured to generate a first temporary parity group according to the first data;

wherein the memory control circuit unit is configured to write second data to a second super-entity unit among the plurality of super-entity units;

wherein the memory control circuit unit is to perform a logical operation on the second data and the first temporary parity group to generate a second temporary parity group;

wherein the memory control circuitry is to associate the first and second super-entity cells as a first array of entity cells;

wherein the memory control circuit unit is configured to treat the second temporary parity group as a first parity group of the first physical unit array; and

when all data of the first super-physical unit is invalid data, the memory control circuit unit is configured to perform the logical operation on the first parity block and the first data stored in the first super-physical unit to generate an updated parity block.

15. The memory storage device of claim 14,

the memory control circuit unit is configured to use the updated parity group as the first parity group of the first physical unit array.

16. The memory storage device of claim 15,

before all data of a first super-physical unit of the first physical unit array is invalid data, the memory control circuit unit is used for writing third data into a third super-physical unit of the plurality of super-physical units; and

wherein the memory control circuit unit is to perform the logical operation on the third data and the second temporary parity group to generate a third temporary parity group.

17. The memory storage device of claim 14, wherein the first super-physical cell comprises a plurality of physically-erased cells, the physically-erased cells of the first super-physical cell respectively comprise a plurality of physically-programmed cells, and each physically-erased cell of the first super-physical cell belongs to a different memory plane.

18. The memory storage device of claim 15,

wherein the memory control circuit unit is used for merging a super entity unit of the first entity unit array and a super entity unit of another entity unit array into a new entity unit array; and

wherein the memory control circuit unit is configured to use a value obtained by performing the logical operation on the first parity code group of the first physical unit array and the other parity code group of the other physical unit array as a new parity code group corresponding to the new physical unit array.

19. The memory storage device of claim 18,

the number of super-entity cells associated with the first entity cell array is not greater than a predefined threshold, the number of super-entity cells associated with the other entity cell array is not greater than the predefined threshold, and the number of super-entity cells associated with the new entity cell array is not greater than the predefined threshold.

20. The memory storage device of claim 14, wherein the logical operation is an XOR operation.