CN109994467A - ESD-protection structure and forming method thereof, working method - Google Patents
ESD-protection structure and forming method thereof, working method Download PDFInfo
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- CN109994467A CN109994467A CN201910362876.3A CN201910362876A CN109994467A CN 109994467 A CN109994467 A CN 109994467A CN 201910362876 A CN201910362876 A CN 201910362876A CN 109994467 A CN109994467 A CN 109994467A
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- 238000000034 method Methods 0.000 title claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 93
- 150000002500 ions Chemical class 0.000 claims description 180
- -1 boron ion Chemical class 0.000 claims description 20
- 239000002019 doping agent Substances 0.000 claims description 14
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 10
- 229910001449 indium ion Inorganic materials 0.000 claims description 10
- 239000004744 fabric Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 35
- 239000000463 material Substances 0.000 description 20
- 239000004065 semiconductor Substances 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 230000015556 catabolic process Effects 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 230000005669 field effect Effects 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- CKUAXEQHGKSLHN-UHFFFAOYSA-N [C].[N] Chemical compound [C].[N] CKUAXEQHGKSLHN-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 125000006239 protecting group Chemical group 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A kind of ESD-protection structure and forming method thereof, working method, forming method include: offer substrate, and substrate includes the firstth area, the secondth area and third area；The first well region is formed in substrate, it is the first ion of the first concentration that the first well region, which has concentration,；First grid structure is formed on the second area surface；The first doped region, the second ion that the first doped region has conduction type opposite with the first ion are formed in the firstth area；The second doped region is formed in third area, it is the second ion of the second concentration that the second doped region, which has concentration, and the second concentration is greater than the first concentration；Third doped region is formed in third area, second doped region and third doped region are arranged along first direction is parallel to, and second doped region it is adjacent with third doped region, it is the third ion of third concentration that third doped region, which has concentration, the conduction type of third ion and the second ion are on the contrary, third concentration is greater than the first concentration.The method improves the performance of ESD-protection structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of ESD-protection structure and forming method thereof, work
Make method.
Background technique
ESD (Electrostatic Discharge, static discharge) is that most important reliability is asked in current integrated circuit
One of topic.ESD event mainly can cause damage below to electronic device: be caused in the semiconductor device due to dielectric breakdown
Breaks down.
The effect of esd protection circuit is: after esd pulse occurs, can provide a low-impedance discharge path, and can
Clamp the voltage at certain level.The access is faster than internal circuit to the opening speed of esd pulse, on work normally influence compared with
It is small, including smaller leakage current, parasitism, bolt-lock etc..Esd protection circuit is typically designed in integrated circuit design to be welded in chip pin
By disk PAD, to protect the internal circuit of chip.Esd protection circuit usually is constituted with one or more devices, for constituting
There are many kinds of the devices of esd protection circuit, metal-oxide-semiconductor (Metal-Oxide-Semiconductor Field-Effect
Transistor, metal oxide semiconductor field effect tube) it is exactly one of which, including NMOS tube (N-Channel MOS, N ditch
Road metal-oxide-semiconductor) and PMOS tube (P-Channel MOS, P-channel metal-oxide-semiconductor).The main instant failure (Snapback) for utilizing NMOS tube
Effect is carried out clamper instantaneous pressure and is shunted.GGNMOS pipe (Gate ground NMOS, grounded-grid metal oxide half
Conductor field-effect tube) as ESD device forward direction rely on NPN (N+ active area-P type substrate-source electrode N+ active area of drain electrode) BJT
(parasitic bipolar transistor) releases ESD circuit；The NMOS that reversed PN diode (P type substrate-N+ active area) and grid source connect
Diode composition.
However, the performance of metal-oxide-semiconductor electrostatic discharge protection circuit is poor in the prior art.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of ESD-protection structure and forming method thereof, working method,
To improve the electrostatic protection performance of field effect transistor.
In order to solve the above technical problems, the present invention provides a kind of ESD-protection structure, comprising: substrate, the substrate
Including the firstth area, the secondth area and third area, secondth area is between the firstth area and third area, secondth area and the firstth area
It is adjacent, and secondth area is adjacent with third area；The first well region in firstth area of substrate and third area, described first
Well region has the first ion, and the first ion in first well region has the first concentration；Positioned at the of the secondth area of substrate surface
One gate structure；The first doped region in the firstth area of substrate, first doped region have the second ion, described second from
The conduction type of son is opposite with the conduction type of the first ion；The second doped region and third doping in substrate third area
Area, second doped region and third doped region are arranged along first direction, and the second doped region is adjacent with third doped region, and first
Perpendicular to first direction, second doped region has the second ion, the tool of the second ion in second doped region in direction
There is the second concentration, the second concentration is greater than the first concentration, and the third doped region has third ion, the conduction of the third ion
The conduction type of type and the second ion is on the contrary, the third ion in the third doped region has third concentration, third concentration
Greater than the first concentration.
Optionally, the second ion in first doped region has the 4th concentration, and it is dense that the 4th concentration is greater than first
Degree.
Optionally, the number of second doped region is one, and the number of the third doped region is one.
Optionally, the number of second doped region is multiple, and the number of the third doped region be it is multiple, described the
Two doped regions and the third doped region are arranged alternately along first direction.
Optionally, the number of second doped region is equal with the number of third doped region.
Optionally, first ion is P-type ion；First ion includes: boron ion or indium ion；Described second
Ion is N-type ion；Second ion includes: phosphonium ion or arsenic ion.
Optionally, first ion is N-type ion, and first ion includes: phosphonium ion or arsenic ion；Described second
Ion is P-type ion, second ion: including boron ion or indium ion.
Optionally, the third doped region connects electrostatic input terminal；The first grid structure, the first doped region and second are mixed
Miscellaneous area's ground connection.
The present invention also provides a kind of forming methods of any one of the above ESD-protection structure, comprising: substrate is provided,
The substrate includes the firstth area, the secondth area and third area, and secondth area is between the firstth area and third area, secondth area
It is adjacent with the firstth area, and secondth area is adjacent with third area；The first well region is formed in firstth area of substrate and third area,
First well region has the first ion, and the first ion in first well region has the first concentration；In the secondth area of substrate table
Face forms first grid structure, and the first grid parallelism structural is in first direction；The first doping is formed in the firstth area of substrate
Area, first doped region have the second ion, and the conduction type of second ion is opposite with the conduction type of the first ion；
Forming the second doped region in substrate third area, second doped region has the second ion, and the in second doped region
Two ions have the second concentration, and the second concentration is greater than the first concentration；Form third doped region in substrate third area, described the
Two doped regions and third doped region are along being parallel to first direction arrangement, and the second doped region is adjacent with third doped region, and described the
Three doped regions have third ion, and the conduction type of the third ion and the conduction type of the second ion are on the contrary, the third
Third ion in doped region has third concentration, and third concentration is greater than the first concentration.
Optionally, the forming method of second doped region includes: using the first doping process the of substrate third area
The second doped region is formed in one well region.
Optionally, the forming method of the third doped region includes: using the second doping process the of substrate third area
Third doped region is formed in one well region.
Optionally, after forming third doped region, the second doped region is formed.
Optionally, after forming the second doped region, third doped region is formed.
Optionally, the forming method of first doped region, the second doped region and third doped region includes: to mix using first
General labourer's skill forms the first doped region and initial second doped region in the first well region of first grid structure two sides, and described
There is second ion in one doped region and initial second doped region；The first grid structure, the first doped region and just
Begin the second doped region surface formation mask layer, has the first opening in the mask layer, and first opening exposes partially just
Begin the second doped region surface；Using the mask layer as exposure mask, using the second doping process in initial second doped region shape
At third doped region, there is third ion in the third doped region, the conduction type of the third ion and the second ion
Conduction type is on the contrary, initial first doped region for being located at the mask layer bottom forms second doped region.
Optionally, the substrate further includes the 4th area, has the second well region, second well region in the 4th area of substrate
Inside there is the 4th ion, the conduction type of the 4th ion is opposite with the conduction type of the first ion；The static discharge is protected
The forming method of protection structure further include: form second grid structure on the 4th area surface of substrate；In the second grid knot
The second source dopant region and the second leakage doped region, second source dopant region and the second leakage doping are formed in second well region of structure two sides
There is third ion in area；It is formed during third doped region, forms second source dopant region and the second leakage doped region.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In the forming method for the ESD-protection structure that technical solution of the present invention provides, the second doped region and third doping
Area is located in third area and arranges along first direction, and the depth of third doped region is shallower, reduces the mistake to form third doped region
To the damage of substrate in journey.On the other hand, second doped region is the leakage doped region of ESD-protection structure, the second doping
The concentration of the first ion is higher in area, and the second doped region and adjacent third doped region are formed by the thinner thickness of depletion layer,
Then the reversed avalanche breakdown voltage between the second doped region and adjacent third doped region or tunnelling breakdown voltage are smaller, simultaneously
Second doped region, third doped region and the first doped region are formed by parasitic bipolar transistor and are easy to open；Therefore anti-in electrostatic
It can be protected in protection circuit and ESD-protection structure and transistor even.To sum up, the property of ESD-protection structure is improved
Energy.
Further, the third doped region is formed simultaneously with the second source dopant region and the second leakage doped region, can be reduced figure
The number of chemical industry skill, to improve the performance of electrostatic protection field effect transistor.
In the ESD-protection structure that technical solution of the present invention provides, second doped region is electrostatic discharge (ESD) protection
The leakage doped region of structure, the concentration of the first ion is higher in the second doped region, the second doped region and adjacent third doped region institute
The thinner thickness of the depletion layer of formation, then the reversed avalanche breakdown voltage between the second doped region and adjacent third doped region or
Tunnelling breakdown voltage is smaller, while the second doped region, third doped region and the first doped region are formed by parasitic bipolar crystal
Pipe is easy to open；Therefore it can be protected in electrostatic discharge protection circuit and ESD-protection structure and transistor even.Third doping
Area is consistent with the second doped region depth, therefore the depth of third doped region is shallower, and it is right during forming third doped region to reduce
The damage of substrate improves the performance of ESD-protection structure.
Detailed description of the invention
Fig. 1 is a kind of the schematic diagram of the section structure of ESD-protection structure；
Fig. 2 to Fig. 7 is the structural schematic diagram of ESD-protection structure forming process in one embodiment of the invention.
Specific embodiment
As described in background, the performance of the ESD-protection structure of the prior art is poor.
Fig. 1 is a kind of the schematic diagram of the section structure of ESD-protection structure, referring to FIG. 1, the electrostatic discharge (ESD) protection
Structure includes: substrate 100, has well region in the substrate 100, and the well region has the first ion, first ion it is dense
Degree is the first concentration；Gate structure 110 positioned at 100 surface of substrate；It is located in the substrate 100 of 110 two sides of gate structure
Leakage doped region 131 and source dopant region 132, there is the second ion, institute in the leakage doped region 131 and the source dopant region 132
The conduction type for stating the second ion is opposite with the first ion；Electrostatic protection doped region positioned at leakage 131 bottom of doped region
140, the electrostatic protection doped region 140 is interior to have the first ion, and the first ion in the electrostatic protection doped region 140 has
Second concentration, second concentration are greater than the first concentration.
In above-mentioned ESD-protection structure, the technique for forming electrostatic protection doped region 140 is ion implantation technology, electrostatic
Protect the depth of doped region 140 deeper, the Implantation Energy needed is higher, and it is larger to the damage of substrate 100, so as to cause being formed
ESD-protection structure performance it is poor.
In the forming method of ESD-protection structure provided in an embodiment of the present invention, substrate is provided, the substrate includes
Firstth area, the secondth area and third area, form the first well region in firstth area of substrate and third area, and first well region has
First ion, the first ion in first well region have the first concentration；First grid knot is formed on substrate the secondth area surface
Structure；The second doped region and third doped region are formed in substrate third area, the second ion in second doped region has
Second concentration, the second concentration are greater than the first concentration, and the third doped region has third ion, the conductive-type of the third ion
For the conduction type of type and the second ion on the contrary, the third ion in the third doped region has third concentration, third concentration is big
In the first concentration.The depth of third doped region is shallower, reduces the damage during forming third doped region to substrate, improves
The performance of ESD-protection structure.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
" surface " in this specification is not limited to directly contact for describing the relative positional relationship in space.
Fig. 2 to Fig. 7 is the structural schematic diagram of ESD-protection structure forming process in one embodiment of the invention.
Referring to FIG. 2, providing substrate 200.
The substrate 200 include the first area I, the second area II and third area III, the secondth area II be located at the first area I with
Between third area III, the secondth area II is adjacent with the first area I, and the secondth area II is adjacent with third area III.
It is that example is illustrated using the ESD-protection structure as the MOS transistor of plane formula in the present embodiment,
It is semiconductor devices as fin formula field effect transistor using the ESD-protection structure in other embodiments.
In the present embodiment, the substrate 200 is the semiconductor substrate of plane formula.In other embodiments, when the electrostatic
When discharge prevention structure is fin formula field effect transistor, the substrate includes semiconductor substrate and the fin in semiconductor substrate
Portion.
The material of the substrate 200 includes the semiconductor materials such as silicon, germanium, SiGe, GaAs, indium gallium arsenic, wherein silicon material
Material includes monocrystalline silicon, polysilicon or amorphous silicon.The substrate 200 can also be semiconductor-on-insulator structure, the insulator
Upper semiconductor structure includes insulator and the semiconductor material layer on insulator, and the material of the semiconductor material layer includes
The semiconductor materials such as silicon, germanium, SiGe, GaAs, indium gallium arsenic.
In the present embodiment, the material of the substrate 200 is monocrystalline silicon.
Form the first well region in the 200 first area I of substrate and third area III, first well region have first from
Son, the first ion in first well region have the first concentration.
In the present embodiment, first ion is P-type ion, and first ion includes: boron ion or indium ion.Other
In embodiment, first ion is N-type ion, and first ion includes: phosphonium ion or arsenic ion.
In the present embodiment, in the present embodiment, the substrate 200 further includes the 4th area, is had in the 4th area of substrate 200
Second well region, second well region is interior to have the 4th ion, the conduction type of the 4th ion and the conductive-type of the first ion
Type is opposite.
In the present embodiment, the 4th ion is N-type ion, and the 4th ion includes: phosphonium ion or arsenic ion.Other
In embodiment, the 4th ion is P-type ion, and the 4th ion includes: boron ion or indium ion.
With continued reference to FIG. 2, forming first grid structure 210 on the 200 second area surface II of substrate.
The first grid structure 210 includes the first gate dielectric layer 211 and the first grid positioned at first grid dielectric layer surface
Pole layer 212.
In the present embodiment, the material of first gate dielectric layer 211 is silica, the material of the first grid layer 212
For polysilicon.
In other embodiments, the material of first gate dielectric layer is high K (K is greater than 3.9) dielectric material, the first grid
The material of electrode layer is metal, such as tungsten.
In the present embodiment, the forming method of the first grid structure 210 includes: to form the on 200 surface of substrate
One gate structure film, the first grid structural membrane include the first gate dielectric film and the first grid positioned at the first gate dielectric film surface
Pole film；The first grid structural membrane for removing 200 surface of part of substrate, forms the first grid on the 200 second area surface II of substrate
Pole structure 210.
In the present embodiment, second grid structure also is formed in the 4th area of substrate 200.The second grid structure includes
Second gate dielectric layer and second grid layer positioned at second gate dielectric layer surface.
In the present embodiment, is formed in first grid configuration process, form the second grid structure.In other embodiments,
After forming first grid structure, second grid structure is formed；Or after forming second grid structure, first grid structure is formed.
Referring to FIG. 3, form the first doped region 230 in 200 first area I of substrate, first doped region 230 has the
The conduction type of two ions, second ion is opposite with the conduction type of the first ion.
The second ion in first doped region 230 has the 4th concentration, and the 4th concentration is greater than the first concentration.
Then, the second doped region is formed in 200 third area III of substrate, second doped region has the second ion.?
Third doped region is formed in 200 third area III of substrate, second doped region and third doped region are arranged along first direction is parallel to
Cloth, and the second doped region is adjacent with third doped region, the third doped region has third ion, the conduction of the third ion
Type is opposite with the conduction type of the second ion.
It is formed before the second doped region and third doped region, further includes being formed initially in the 200 third area III of substrate
Second doped region 240, it is subsequent to form the second doped region and third doped region on the basis of initial second doped region 240.
In the present embodiment, first doped region 230 and initial second doped region 240 are formed simultaneously, in other embodiments,
First doped region and initial second doped region are not formed simultaneously.
The forming method of first doped region 230 and initial second doped region 240 includes: to be existed using the first doping process
The first doped region 230 of formation and initial second doped region 240 in first well region of first grid structure two sides, described first
There is second ion in doped region 230 and initial second doped region 240；First doped region 230 is located at substrate 200
One area I, initial second doped region 240 are located at 200 third area III of substrate.
First doping process includes: ion implantation technology, solid-source doping technique or epitaxial growth technology.
In the present embodiment, first doping process is ion implantation technology.
In one embodiment, first doping process is solid-source doping technique.
In other embodiments, first doped region and initial second doped region are formed using epitaxial growth technology, extension
Growth technique further includes to first doped region and initial the during forming the first doped region and initial second doped region
Two doped regions carry out doping in situ.
In the present embodiment, second ion is N-type ion, and second ion includes: phosphonium ion or arsenic ion.Other
In embodiment, second ion is P-type ion, and second ion includes: boron ion or indium ion.
In the present embodiment, the forming method of the ESD-protection structure further include: using the first doping process in institute
It states in the first well region of first grid structure two sides and is formed before the first doped region 230 and initial second doped region 240, described
First grid structure side wall forms the first side wall 221, and first side wall 221 covers first grid dielectric layer 211 and the first grid
Pole 212 side wall of layer；After forming the first side wall 221, in the first well region of 221 two sides of the first grid structure and the first side wall
Form the first lightly doped district 201；After forming the first lightly doped district 201, the second side wall is formed in 211 side wall of the first side wall
222。
First side wall 221 is used to define the position of the first lightly doped district 201.First lightly doped district 201 is used for
Adjust the threshold voltage of ESD-protection structure.First side wall 221 and the second side wall 222 are for defining the first doped region
230 and initial second doped region 240 position.
The material of first side wall 221 include: silica, silicon nitride, silicon oxynitride, silicon oxide carbide, carbonitride of silicium or
Carbon silicon oxynitride.The material of second side wall 222 includes: silica, silicon nitride, silicon oxynitride, silicon oxide carbide, carbonitride of silicium
Or carbon silicon oxynitride.
In the present embodiment, first side wall 221 is identical with the material of the second side wall 222.In other embodiments, described
One side wall 221 is different with the material of the second side wall 222.
In the present embodiment, the material of first side wall 221 and the second side wall 222 is silicon nitride.
In the present embodiment, the substrate further includes the 4th area, using the first doping process in the first grid structure two
It is formed before the first doped region 230 and initial second doped region 240 in first well region of side, further includes: in the substrate the 4th
Area and second grid body structure surface form protective layer.Protective layer protecting group bottom the 4th during using the first doping process
Area and second grid structure.
Then, the second doped region 241 and third doped region 242 are formed in 200 third area III of substrate.Described second mixes
The forming method of miscellaneous area 241 and the third doped region 242 please refers to Fig. 4 to Fig. 7.
Referring to FIG. 4, being formed on the first grid structure, the first doped region 230 and initial second doped region, 240 surface
Mask layer 202, the mask layer 202 is interior to have the first opening, and first opening exposes initial second doped region 240 in part
Surface.
In the present embodiment, the material of the mask layer 202 is photoresist.In other embodiments, the mask layer 202 is hard
Mask layer, the material of the hard mask layer include: silica, silicon nitride, silicon oxynitride, silicon oxide carbide, carbonitride of silicium or carbon nitrogen
Silica.
In the present embodiment, the substrate 200 further includes the 4th area；The mask layer 202 exposes the 4th area of substrate 200
Second well region surface of two gate structure two sides.The forming method of the ESD-protection structure further include: form mask layer
Before 202, the protective layer on the second well region surface of the 4th area second grid structure two sides of substrate 200 is removed.
Referring to FIG. 5, being exposure mask with the mask layer 202, using the second doping process in initial second doped region
Third doped region 242 is formed in 240, and there is third ion, the conduction type of the third ion in the third doped region 242
Conduction type with the second ion is on the contrary, initial second doped region 240 for being located at 202 bottom of mask layer forms described second
Doped region 241.
Second doped region 241 and third doped region 242 are arranged along first direction, and the second doped region 241 and third
Doped region 242 is adjacent, and second doped region 241 has the second ion, the tool of the second ion in second doped region 241
There is the second concentration, the second concentration is greater than the first concentration, and the third doped region 242 has third ion, the third ion
The conduction type of conduction type and the second ion is on the contrary, third ion in the third doped region 242 has third concentration, and the
Three concentration are greater than the first concentration.
In the present embodiment, the third ion is P-type ion, and the third ion includes: boron ion or indium ion.Other
In embodiment, the third ion is N-type ion, and the third ion includes: phosphonium ion or arsenic ion.
Third concentration is greater than the first concentration, then the breakdown reverse voltage between the second doped region 241 and third doped region 242
Less than the breakdown reverse voltage between the second doped region and the first well region, the second doped region 241 is easy quilt with third doped region 242
Breakdown, and the parasitic bipolar diode of ESD-protection structure is easy to open.
In the present embodiment, the number of second doped region 241 is multiple, and the number of the third doped region 242 is
Multiple, multiple second doped regions 241 and multiple third doped regions 242 are arranged alternately along first direction.
In the present embodiment, the number of second doped region 241 is equal with the number of third doped region 242.
In one embodiment, the number of second doped region is one, and the number of the third doped region is one.
Second doping process includes: ion implantation technology or solid-source doping technique.
In the present embodiment, second doping process is ion implantation technology.In other embodiments, the second doping work
Skill is solid-source doping technique.
Second doped region 241 and third doped region 242 are located in 200 third area III of substrate along first direction, third doping
The depth in area 242 is shallower, avoids damage of the deep doping process to substrate, improves the performance of ESD-protection structure.
In the present embodiment, the substrate 200 further includes the 4th area；The forming method of the ESD-protection structure is also wrapped
Include: formed in the second well region of second grid structure two sides the second source dopant region and second leakage doped region, described second
There is the second ion in source dopant region and the second leakage doped region.
In the present embodiment, the second source dopant region and the second leakage doping are formed during forming the third doped region 242
Area.
The third doped region 242 is formed simultaneously with the second source dopant region and the second leakage doped region, can be reduced figure chemical industry
The number of skill, to improve the performance of electrostatic protection field effect transistor.
In other embodiments, after forming third doped region, the second source dopant region and the second leakage doped region are formed；Or it is formed
Behind second source dopant region and the second leakage doped region, third doped region is formed.
In one embodiment, after forming the second doped region, third doped region is formed.
The forming method of second doped region include: using the first doping process in first well region in substrate third area
Form the second doped region.
The forming method of the third doped region include: using the second doping process in first well region in substrate third area
Form third doped region.
In another embodiment, after forming third doped region, the second doped region is formed.
Fig. 6 and Fig. 7 are please referred to, Fig. 7 is that ESD-protection structure forms the second doping along the top view of Z-direction in Fig. 6
Behind area 241 and third doped region 242, the mask layer 202 is removed.
The technique for removing the mask layer 202 includes: dry etch process or wet-etching technology.
In the present embodiment, the material of the mask layer 202 is photoresist, removes the technique of the mask layer 202 as ashing
Technique.
Second doped region 241 and third doped region 242 constitute the leakage doped region of ESD-protection structure, the second doped region
The concentration of first ion is higher in 241, and the second doped region 241 and adjacent third doped region 242 are formed by the thickness of depletion layer
Spend relatively thin, the then reversed avalanche breakdown voltage or tunnelling breakdown potential between the second doped region 241 and adjacent third doped region 242
Pressure is smaller, while the second doped region 241, third doped region 242 and the first doped region 230 are formed by parasitic bipolar transistor
It is easy to open；Therefore it can be protected in electrostatic discharge protection circuit and ESD-protection structure and transistor even.
Correspondingly, the embodiment of the present invention also provides a kind of ESD-protection structure formed using the above method, please join
Examine Fig. 6 and Fig. 7, comprising: substrate 200, the substrate 200 include the first area I, the second area II and third area III, secondth area
For II between the first area I and third area II, the secondth area II is adjacent with the first area I, and the secondth area II and third area
III is adjacent；There is the first well region in the 200 first area I of substrate and third area III, first well region has the first ion,
The first ion in first well region has the first concentration；First grid structure positioned at the 200 second area surface II of substrate；Position
The first doped region 230 in 200 first area I of substrate, first doped region 230 have the second ion, second ion
Conduction type it is opposite with the first ion；The second doped region 241 and third doped region in 200 third area III of substrate
242, second doped region 241 and third doped region 242 are arranged along first direction, and the second doped region 241 is adulterated with third
Area 242 is adjacent, and second doped region 241 has the second ion, and the second ion in second doped region 241 has the
Two concentration, the second concentration are greater than the first concentration, and the third doped region 242 has third ion, the conduction of the third ion
For the conduction type of type and the second ion on the contrary, the third ion in the third doped region 242 has third concentration, third is dense
Degree is greater than the first concentration.
The second ion in first doped region 230 has the 4th concentration, and the 4th concentration is greater than the first concentration.
In the present embodiment, the number of second doped region 241 is multiple, and the number of the third doped region 242 is
Multiple, the second doped region 241 and third doped region 242 are arranged alternately along first direction.
In the present embodiment, the number of second doped region 241 is equal with the number of third doped region 242.
In one embodiment, the number of second doped region is one, and the number of the third doped region is one.
The number of second doped region 241 is equal with the number of third doped region 242.
First ion is P-type ion, and first ion includes: boron ion or indium ion；Second ion is N
Type ion, second ion include: phosphonium ion or arsenic ion.
First ion is N-type ion, and first ion includes: phosphonium ion or arsenic ion；Second ion is P
Type ion, second ion: including boron ion or indium ion.
In the present embodiment, the ESD-protection structure further include: the third doped region 242 connects electrostatic input terminal；
The first grid structure, the first doped region 230 and the second doped region 241 ground connection.
There is the second ion in second doped region 241；The third doped region 242 has a third ion, and described the
The conduction type of three ions is opposite with the conduction type of the second ion.
In the present embodiment, second ion is N-type ion, and the third ion is P-type ion.
When the voltage for connecing electrostatic input terminal is negative pressure, adulterated by the third in reverse breakdown ESD-protection structure
PN junction between area 242 and the second doped region 241 is by charge discharging resisting to ground terminal.
When the voltage for connecing electrostatic input terminal is positive pressure, by ESD-protection structure the second doped region 241, the
Three doped regions 242 and the first doped region 230 are formed by parasitic bipolar transistor and release charge to ground terminal.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (15)
1. a kind of ESD-protection structure characterized by comprising
Substrate, the substrate include the firstth area, the secondth area and third area, secondth area between the firstth area and third area,
Secondth area is adjacent with the firstth area, and secondth area is adjacent with third area；
The first well region in firstth area of substrate and third area, first well region have the first ion, described first
The first ion in well region has the first concentration；
First grid structure positioned at the secondth area of substrate surface, the first grid parallelism structural is in first direction；
The first doped region in the firstth area of substrate, first doped region have the second ion, and second ion is led
Electric type is opposite with the conduction type of the first ion；
The second doped region and third doped region in substrate third area, second doped region and third doped region are along first
Direction arrangement, and the second doped region is adjacent with third doped region, second doped region has the second ion, second doping
The second ion in area has the second concentration, and the second concentration is greater than the first concentration, and the third doped region has third ion,
The conduction type of the third ion is with the conduction type of the second ion on the contrary, the third ion in the third doped region has
Third concentration, third concentration are greater than the first concentration.
2. ESD-protection structure according to claim 1, which is characterized in that in first doped region second from
Son has the 4th concentration, and the 4th concentration is greater than the first concentration.
3. ESD-protection structure according to claim 1, which is characterized in that the number of second doped region is one
It is a, and the number of the third doped region is one.
4. ESD-protection structure according to claim 1, which is characterized in that the number of second doped region is more
It is a, and the number of the third doped region be it is multiple, second doped region and the third doped region replace along first direction
Arrangement.
5. ESD-protection structure according to claim 1 or 4, which is characterized in that the number of second doped region
It is equal with the number of third doped region.
6. ESD-protection structure according to claim 2, which is characterized in that first ion is P-type ion；Institute
Stating the first ion includes: boron ion or indium ion；Second ion is N-type ion；Second ion include: phosphonium ion or
Arsenic ion.
7. ESD-protection structure according to claim 2, which is characterized in that first ion is N-type ion, institute
Stating the first ion includes: phosphonium ion or arsenic ion；Second ion is P-type ion, second ion: including boron ion or
Indium ion.
8. ESD-protection structure according to claim 1, which is characterized in that the third doped region connects electrostatic input
End；The first grid structure, the first doped region and the second doped region ground connection.
9. a kind of forming method of the ESD-protection structure as described in claim 1 to 8 any one, which is characterized in that
Include:
Substrate is provided, the substrate includes the firstth area, the secondth area and third area, secondth area be located at the firstth area and third area it
Between, secondth area is adjacent with the firstth area, and secondth area is adjacent with third area；
Forming the first well region in firstth area of substrate and third area, first well region has the first ion, and described first
The first ion in well region has the first concentration；
First grid structure is formed on substrate the secondth area surface, the first grid parallelism structural is in first direction；
The first doped region is formed in the firstth area of substrate, first doped region has the second ion, and second ion is led
Electric type is opposite with the conduction type of the first ion；
Form the second doped region in substrate third area, second doped region has the second ion, in second doped region
The second ion have the second concentration, the second concentration be greater than the first concentration；
Third doped region is formed in substrate third area, second doped region and third doped region are arranged along first direction is parallel to
Cloth, and the second doped region is adjacent with third doped region, the third doped region has third ion, the conduction of the third ion
The conduction type of type and the second ion is on the contrary, the third ion in the third doped region has third concentration, third concentration
Greater than the first concentration.
10. the forming method of ESD-protection structure according to claim 9, which is characterized in that second doping
The forming method in area includes: to form the second doped region in first well region in substrate third area using the first doping process.
11. the forming method of ESD-protection structure according to claim 9 or 10, which is characterized in that the third
The forming method of doped region includes: to form third doped region in first well region in substrate third area using the second doping process.
12. the forming method of ESD-protection structure according to claim 11, which is characterized in that form third doping
Qu Hou forms the second doped region.
13. the forming method of ESD-protection structure according to claim 11, which is characterized in that form the second doping
Qu Hou forms third doped region.
14. the forming method of ESD-protection structure according to claim 11, which is characterized in that first doping
The forming method in area, the second doped region and third doped region includes: using the first doping process in the first grid structure two
The first doped region and initial second doped region are formed in first well region of side, in first doped region and initial second doped region
With second ion；Mask layer is formed on the first grid structure, the first doped region and initial second doped region surface,
There is the first opening, first opening exposes part initial second doped region surface in the mask layer；With the exposure mask
Layer is exposure mask, and third doped region, the third doped region are formed in initial second doped region using the second doping process
It is interior that there is third ion, the conduction type of the third ion and the conduction type of the second ion on the contrary, being located at the mask layer
Initial first doped region of bottom forms second doped region.
15. the forming method of ESD-protection structure according to claim 11, which is characterized in that the substrate is also wrapped
The 4th area is included, there is the second well region in the 4th area of substrate, there is the 4th ion, the 4th ion in second well region
Conduction type it is opposite with the conduction type of the first ion；The forming method of the ESD-protection structure further include: in institute
It states the 4th area surface of substrate and forms second grid structure；The second source is formed in the second well region of second grid structure two sides
There is third ion in doped region and the second leakage doped region, second source dopant region and the second leakage doped region；Third is formed to mix
During miscellaneous area, second source dopant region and the second leakage doped region are formed.
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| CN116230754A (en) * | 2023-05-04 | 2023-06-06 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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| CN101099239A (en) * | 2005-09-30 | 2008-01-02 | 株式会社理光 | Semiconductor device |
| CN103178058A (en) * | 2013-03-29 | 2013-06-26 | 中国航天科技集团公司第九研究院第七七一研究所 | Diode-assisting triggering ESD (Electro-Static Discharge) protection circuit based on PD (Potential Difference) SOI (Silicon On Insulator) |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101099239A (en) * | 2005-09-30 | 2008-01-02 | 株式会社理光 | Semiconductor device |
| CN103178058A (en) * | 2013-03-29 | 2013-06-26 | 中国航天科技集团公司第九研究院第七七一研究所 | Diode-assisting triggering ESD (Electro-Static Discharge) protection circuit based on PD (Potential Difference) SOI (Silicon On Insulator) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116230754A (en) * | 2023-05-04 | 2023-06-06 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN116230754B (en) * | 2023-05-04 | 2023-09-12 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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Application publication date: 20190709 |