CN109975764A - A kind of transmission of general purpose radar integratedization high speed fibre and control interface plate and its application - Google Patents

A kind of transmission of general purpose radar integratedization high speed fibre and control interface plate and its application Download PDF

Info

Publication number
CN109975764A
CN109975764A CN201910209633.6A CN201910209633A CN109975764A CN 109975764 A CN109975764 A CN 109975764A CN 201910209633 A CN201910209633 A CN 201910209633A CN 109975764 A CN109975764 A CN 109975764A
Authority
CN
China
Prior art keywords
data
interface
syn
rate
length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910209633.6A
Other languages
Chinese (zh)
Inventor
曹明晶
王宝
张锐
张宁明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anhui Leiyan Electronic Technology Co Ltd
Original Assignee
Anhui Leiyan Electronic Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anhui Leiyan Electronic Technology Co Ltd filed Critical Anhui Leiyan Electronic Technology Co Ltd
Priority to CN201910209633.6A priority Critical patent/CN109975764A/en
Publication of CN109975764A publication Critical patent/CN109975764A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01SRADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B10/00Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/25Arrangements specific to fibre transmission
    • H04B10/2589Bidirectional transmission
    • H04B10/25891Transmission components
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026PCI express

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electromagnetism (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)

Abstract

The present invention discloses a kind of transmission of general purpose radar integratedization high speed fibre and control interface plate, including PCIE fiber optic communication card, the PCIE fiber optic communication card includes pcie2.0 interface, FPGA, the optical module of four hairs four of MPO interface are received all the way optical module or four road LC/FC interfaces;The pcie2.0 interface is used reaches rate in a manner of configuration file, the customized adjustment of interface protocol.It is highly reliable, it is provided simultaneously with transmission-receiving function, it is versatile.

Description

A kind of transmission of general purpose radar integratedization high speed fibre and control interface plate and its Using
Technical field
The invention belongs to technical field of optical fiber communication, and in particular to a kind of general purpose radar integratedization high speed fibre biography Defeated and control interface plate and its application.
Background technique
With Radar Signal Processing Technology, the development of computer technology, general purpose computer is wide in terms of Radar Signal Processing General application.Modern computer can flexibly, quickly, accurately complete data processing work.Computer is easy to the software technology developed Gradually replace traditional hardware handles mode, brings great convenience for the debugging efforts of Radar Signal Processing program, and provide New developing direction.
How by the radar echo signal of big data rate be sent to GPU or CPU be processing core computer, server In, become and how radar return data to be refined with using GPU or CPU as the computer of processing core, server The a great problem of processing.
Summary of the invention
It is an object of the present invention to provide a kind of general purpose radar integratedization high speed fibre transmission and control interface plate and its Using, it is highly reliable, it is provided simultaneously with transmission-receiving function, it is versatile.
(1) it is directed to the deficiency of traditional collecting fiber card, transmission rate is small, and rate can not using focusing on solving by the present invention It adjusts, has increased sending function newly simultaneously with the insecure problem of server connecting interface.
(2) present invention substantially increases transmission rate using pcie2.0 interface;It uses and is reached in a manner of configuration file simultaneously To rate, the customized adjustment of interface protocol.Transmission-receiving function can be carried out simultaneously by having transmitting-receiving doubleclocking, and interface is taken using reinforced Business device special purpose interface improves reliability.
(3) optical fiber interface agreement is adjusted by the way of configuration file and adjustment rate is user-friendly and more general Change.
In order to achieve the goal above, the technical solution adopted by the present invention are as follows:
A kind of transmission of general purpose radar integratedization high speed fibre and control interface plate, including PCIE fiber optic communication card, The PCIE fiber optic communication card includes pcie2.0 interface, FPGA, the optical module or four tunnels that four hairs four of MPO interface are received all the way The optical module of LC/FC interface;The pcie2.0 interface is used reaches rate in a manner of configuration file, interface protocol from Definition adjustment.
Further, the PCIE fiber optic communication card FPGA uses 7 Series FPGA of xilinx company.
Further, the connector interface of PCIE collecting fiber card is connected by signal connector (S1/S2/S3), power supply Device (PW) and positioning column (GM) composition.
In addition, invention additionally discloses a kind of transmission of general purpose radar integratedization high speed fibre and control interface plate to answer With including the following steps:
A) data are received:
A.1) transmission rate is set, the driving of PCIE fiber optic communication card is loaded;
A.2) the optical module receiving end of PCIE fiber optic communication card is converted to electric signal transmission to FPGA after receiving optical signal In;
A.3 the data) being driven through in dma mode access FPGA;
A.4 it) is transferred data in server by pcie2.0 interface, server receives after data in local DDR Carry out secondary data caching;
A.5) user carries out reading data and obtains status information simultaneously by calling driving equipment file;
B) data are sent:
B.1) transmission rate is set, the driving of PCIE fiber optic communication card is loaded;
B.2) user is by calling driving equipment file, carrying out data write-in while obtaining status information;
B.3 it) is transferred data in PCIE fiber optic communication card by pcie2.0 interface, PCIE fiber optic communication card receives number Secondary data caching is carried out in local DDR after;
B.4) FPGA reads the data in the DDR of local, carries out alignment coding, is sent to optical module;
B.5) optical module will receive electric signal and be converted to optical signal is sent out by sending port.
Further, optical fiber interface use custom protocol, external clock support multiple choices, traffic rate support 1~ Common rate in 10G, fiber optic communication rate can be configured by software port, and configurable rate is as follows:
Velocity encoded cine Optical fiber rate Gbps
1 1.6
2 2.0
3 2.4
4 2.5
5 3.125
6 3.2
7 4.0
8 4.8
9 5
10 6.25
It receives starting to need to be synchronized by sync byte, communication protocol is 16 customized 8/10b codings, rate and same Step prefix can be configured by software.
Further, synchronous prefix and bell idles can also be configured by software, had ft.conf file in driving, pressed It is configured according to following content:
Syn_length synchronizes prefix byte length, may be configured as 2 or 4,2 as 2 bytes, 4 be nybble;
Whether the synchronous each byte of prefix of syn_kcode is K code mark, 4bit hexadecimal number, the corresponding word of each bit Section, 0 is data, and 1 is K code;
Syn_value synchronizes prefix data, and 32 hexadecimal numbers, when syn_length is 2, low 16 are effectively, When syn_length is 4,32 all effectively.If such as prefix be 0xbc75, wherein bc be K code, 75 be data, then syn_ Length is set as 2, syn_kcode and is set as 0x2, and syn_value is set as 0xbc75;
Idle_length bell idles byte length may be configured as 2 or 4,2 as 2 bytes, and 4 be nybble;
Whether each byte of idle_kcode bell idles is K code mark, 4bit hexadecimal number, the corresponding word of each bit Section, 0 is data, and 1 is K code;
Idle_value bell idles data, 32 hexadecimal numbers, when syn_length is 2, low 16 effectively, syn_ When length is 4,32 all effectively.If such as bell idles be 0xbc3c, wherein bc and 3c is K code, then idle_length It is set as 2, idle_kcode and is set as 0x3, idle_value is set as 0xbc3c.
The technical effects of the invention are that:
(1) it is directed to the deficiency of traditional collecting fiber card, transmission rate is small, and rate can not using focusing on solving by the present invention It adjusts, has increased sending function newly simultaneously with the insecure problem of server connecting interface.
(2) present invention substantially increases transmission rate using pcie2.0 interface;It uses and is reached in a manner of configuration file simultaneously To rate, the customized adjustment of interface protocol.Transmission-receiving function can be carried out simultaneously by having transmitting-receiving doubleclocking, and interface is taken using reinforced Business device special purpose interface improves reliability.
(3) optical fiber interface agreement is adjusted by the way of configuration file and adjustment rate is user-friendly and more general Change.
Detailed description of the invention
Fig. 1 is application architecture figure of the invention;
Fig. 2 is applicating flow chart of the invention;
Fig. 3 connect architecture diagram with server master board for the customized PCIE collecting fiber card of the present invention;
Fig. 4 is board socket type selecting of the present invention and pin definitions figure, wherein the connector of customized PCIE collecting fiber card Interface is made of signal connector (S1/S2/S3), power connector (PW) and positioning column (GM);Shadow region is to place component Wiring region;
Fig. 5 is board interface schema of the present invention;In figure, optical module is on the left of board, respectively interface 1~4 from top to bottom, with Pcie_ft1~pcie_ft4 in driving is corresponding.
Specific embodiment
Based on this problem in background technique, according to traditional PCIE capture card, using PCIE1.0 interface, Transmission rate is unable to meet demand and interface uses " golden finger " interface, and reliability is insufficient, and traditional PCIE interface card speed Rate is non-adjustable, does not have sending function.A kind of common software radar integratedization high speed fibre is arranged in the present invention thus Transmission and control interface plate, the data optical fiber of high-speed transfer is logical under especially a kind of server platform based on GPU or CPU Letter card.Its advantage:
(1) it is directed to the deficiency of traditional collecting fiber card, transmission rate is small, and rate can not using focusing on solving by the present invention It adjusts, has increased sending function newly simultaneously with the insecure problem of server connecting interface.
(2) present invention substantially increases transmission rate using pcie2.0 interface;It uses and is reached in a manner of configuration file simultaneously To rate, the customized adjustment of interface protocol.Transmission-receiving function can be carried out simultaneously by having transmitting-receiving doubleclocking, and interface is taken using reinforced Business device special purpose interface improves reliability.
(3) optical fiber interface agreement is adjusted by the way of configuration file and adjustment rate is user-friendly and more general Change.
In conjunction with attached drawing, customized PCIe card, that is, customized PCIE collecting fiber card in figure, referring to Fig.1, present invention design are adopted With customized PCIE fiber optic communication card, PCIE fiber optic communication card FPGA design uses 7 Series FPGA of xilinx company, supports 8 interface of PCIe2.0 standard x, 2GB DDR3 external memory, the optical module or four road LC/FC interfaces that four hairs four of MPO interface are received all the way Optical module, optical module single channel flank speed support 10Gbps, and DMA transfer read or write speed is not less than 2.8GB/s.
Practical application of the invention:
A) data are received:
A.1) transmission rate is set, the driving of PCIE fiber optic communication card is loaded.
A.2) optical module receiving end is converted to electric signal transmission into FPGA after receiving optical signal.
A.3 the data) being driven through in dma mode access FPGA, guarantee the stable transmission of data high-speed.
A.4 it) is transferred data in server by pcie2.0 interface, server receives after data in local DDR Secondary data caching is carried out, guarantees safety of the CPU in real-time processing data.
A.5) user carries out reading data and obtains status information simultaneously by calling driving equipment file.
B) data are sent:
B.1) transmission rate is set, the driving of PCIE fiber optic communication card is loaded.
B.2) user is by calling driving equipment file, carrying out data write-in while obtaining status information.
B.3 it) is transferred data in PCIE fiber optic communication card by pcie2.0 interface, PCIE fiber optic communication card receives number Secondary data caching is carried out in local DDR after, guarantees that processing data guarantee the stable transmission of data high-speed.
B.4) FPGA reads the data in the DDR of local, carries out alignment coding, is sent to optical module.
B.5) optical module will receive electric signal and be converted to optical signal is sent out by sending port.
Optical fiber interface uses custom protocol, and external clock supports multiple choices, and traffic rate is supported normal in 1~10G With rate, fiber optic communication rate can be configured by software port, and configurable rate is as follows:
Velocity encoded cine Optical fiber rate Gbps
1 1.6
2 2.0
3 2.4
4 2.5
5 3.125
6 3.2
7 4.0
8 4.8
9 5
10 6.25
It receives starting to need to be synchronized by sync byte, communication protocol is 16 customized 8/10b codings, rate and same Step prefix can be configured by software.
Meanwhile synchronous prefix and bell idles can also be configured by software, there is ft.conf file in driving, it can be according to Following content is configured:
Syn_length synchronizes prefix byte length, may be configured as 2 or 4,2 as 2 bytes, 4 be nybble.
Whether the synchronous each byte of prefix of syn_kcode is K code mark, 4bit hexadecimal number, the corresponding word of each bit Section, 0 is data, and 1 is K code.
Syn_value synchronizes prefix data, and 32 hexadecimal numbers, when syn_length is 2, low 16 are effectively, When syn_length is 4,32 all effectively.If such as prefix be 0xbc75, wherein bc be K code, 75 be data, then syn_ Length is set as 2, syn_kcode and is set as 0x2, and syn_value is set as 0xbc75.
Idle_length bell idles byte length may be configured as 2 or 4,2 as 2 bytes, and 4 be nybble.
Whether each byte of idle_kcode bell idles is K code mark, 4bit hexadecimal number, the corresponding word of each bit Section, 0 is data, and 1 is K code.
Idle_value bell idles data, 32 hexadecimal numbers, when syn_length is 2, low 16 effectively, syn_ When length is 4,32 all effectively.If such as bell idles be 0xbc3c, wherein bc and 3c is K code, then idle_length It is set as 2, idle_kcode and is set as 0x3, idle_value is set as 0xbc3c.

Claims (6)

1. a kind of general purpose radar integratedization high speed fibre transmission and control interface plate, which is characterized in that including PCIE light Fiber communication card, the PCIE fiber optic communication card include pcie2.0 interface, FPGA, the optical mode that four hairs four of MPO interface are received all the way The optical module of tetra- road LC/FC interface of Kuai Huo;The pcie2.0 interface is used reaches rate in a manner of configuration file, interface The customized adjustment of agreement.
2. a kind of general purpose radar integratedization high speed fibre transmission according to claim 1 and control interface plate, It is characterized in that, the PCIE fiber optic communication card FPGA uses 7 Series FPGA of xilinx company.
3. a kind of general purpose radar integratedization high speed fibre transmission according to claim 2 and control interface plate, It is characterized in that, the connector interface of PCIE collecting fiber card by signal connector (S1/S2/S3), power connector (PW) and is determined Position column (GM) forms.
4. a kind of general purpose radar integratedization high speed fibre transmission according to claim 1 and control interface plate are answered With, which comprises the steps of:
A) data are received:
A.1) transmission rate is set, the driving of PCIE fiber optic communication card is loaded;
A.2) the optical module receiving end of PCIE fiber optic communication card is converted to electric signal transmission into FPGA after receiving optical signal;
A.3 the data) being driven through in dma mode access FPGA;
A.4 it) is transferred data in server by pcie2.0 interface, server carries out in local DDR after receiving data Secondary data caching;
A.5) user carries out reading data and obtains status information simultaneously by calling driving equipment file;
B) data are sent:
B.1) transmission rate is set, the driving of PCIE fiber optic communication card is loaded;
B.2) user is by calling driving equipment file, carrying out data write-in while obtaining status information;
B.3 it) is transferred data in PCIE fiber optic communication card by pcie2.0 interface, after PCIE fiber optic communication card receives data Secondary data caching is carried out in local DDR;
B.4) FPGA reads the data in the DDR of local, carries out alignment coding, is sent to optical module;
B.5) optical module will receive electric signal and be converted to optical signal is sent out by sending port.
5. a kind of general purpose radar integratedization high speed fibre transmission according to claim 4 and control interface plate are answered With, which is characterized in that
Optical fiber interface uses custom protocol, and external clock supports multiple choices, and traffic rate supports the common speed in 1~10G Rate, fiber optic communication rate can be configured by software port, and configurable rate is as follows:
Velocity encoded cine Optical fiber rate Gbps 1 1.6 2 2.0 3 2.4 4 2.5 5 3.125 6 3.2 7 4.0 8 4.8 9 5 10 6.25
It receives starting to need to be synchronized by sync byte, communication protocol is 16 customized 8/10b codings, rate and synchronization character Head can be configured by software.
6. a kind of general purpose radar integratedization high speed fibre transmission according to claim 5 and control interface plate are answered With, which is characterized in that
Synchronous prefix and bell idles can also be configured by software, there is ft.conf file in driving, according to following content into Row configuration:
Syn_length synchronizes prefix byte length, may be configured as 2 or 4,2 as 2 bytes, 4 be nybble;
Whether the synchronous each byte of prefix of syn_kcode is K code mark, 4bit hexadecimal number, the corresponding byte of each bit, 0 It is K code for data, 1;
Syn_value synchronizes prefix data, and 32 hexadecimal numbers, when syn_length is 2, low 16 effectively, syn_ When length is 4,32 all effectively.If such as prefix be 0xbc75, wherein bc be K code, 75 be data, then syn_length is set It is set to 2, syn_kcode and is set as 0x2, syn_value is set as 0xbc75;
Idle_length bell idles byte length may be configured as 2 or 4,2 as 2 bytes, and 4 be nybble;
Whether each byte of idle_kcode bell idles is K code mark, 4bit hexadecimal number, the corresponding byte of each bit, 0 It is K code for data, 1;
Idle_value bell idles data, 32 hexadecimal numbers, when syn_length is 2, low 16 effectively, syn_ When length is 4,32 all effectively.If such as bell idles be 0xbc3c, wherein bc and 3c is K code, then idle_length is set It is set to 2, idle_kcode and is set as 0x3, idle_value is set as 0xbc3c.
CN201910209633.6A 2019-03-19 2019-03-19 A kind of transmission of general purpose radar integratedization high speed fibre and control interface plate and its application Pending CN109975764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910209633.6A CN109975764A (en) 2019-03-19 2019-03-19 A kind of transmission of general purpose radar integratedization high speed fibre and control interface plate and its application

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910209633.6A CN109975764A (en) 2019-03-19 2019-03-19 A kind of transmission of general purpose radar integratedization high speed fibre and control interface plate and its application

Publications (1)

Publication Number Publication Date
CN109975764A true CN109975764A (en) 2019-07-05

Family

ID=67079505

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910209633.6A Pending CN109975764A (en) 2019-03-19 2019-03-19 A kind of transmission of general purpose radar integratedization high speed fibre and control interface plate and its application

Country Status (1)

Country Link
CN (1) CN109975764A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111367837A (en) * 2020-03-03 2020-07-03 山东超越数控电子股份有限公司 Data interface board of reconfigurable radar signal processing hardware platform
CN112444814A (en) * 2020-11-11 2021-03-05 安徽四创电子股份有限公司 Digital array weather radar signal processor based on PCIE optical fiber acquisition card
CN113691468A (en) * 2021-08-23 2021-11-23 北京电子工程总体研究所 Configuration method of full-wire-speed distribution switching device for realizing port self-adaption

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202662887U (en) * 2012-03-13 2013-01-09 聚信科技有限公司 PCIE (peripheral component interconnect express) card and network interface connector device thereof
CN103513994A (en) * 2012-06-19 2014-01-15 记忆科技(深圳)有限公司 Method and system for carrying out FPGA on-line upgrading through PCIE
CN104808198A (en) * 2015-05-25 2015-07-29 扬州宇安电子科技有限公司 Active and passive integration system of radar
CN106294222A (en) * 2016-08-03 2017-01-04 浪潮电子信息产业股份有限公司 A kind of method and device determining PCIE device and slot corresponding relation
CN106445869A (en) * 2016-09-20 2017-02-22 烟台大学 FPGA (field programmable gate array) and PCIe (peripheral component interface express) based high-speed data exchange architecture
CN108627805A (en) * 2018-03-28 2018-10-09 安徽四创电子股份有限公司 A kind of radar signal data acquisition and analysis system and its analysis method
CN108762939A (en) * 2018-06-29 2018-11-06 郑州云海信息技术有限公司 A kind of PCIe port resource allocation methods, system and equipment and storage medium
CN109471679A (en) * 2018-11-19 2019-03-15 郑州云海信息技术有限公司 The method that a kind of pair of PCIE exchange chip configuration file is configured

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202662887U (en) * 2012-03-13 2013-01-09 聚信科技有限公司 PCIE (peripheral component interconnect express) card and network interface connector device thereof
CN103513994A (en) * 2012-06-19 2014-01-15 记忆科技(深圳)有限公司 Method and system for carrying out FPGA on-line upgrading through PCIE
CN104808198A (en) * 2015-05-25 2015-07-29 扬州宇安电子科技有限公司 Active and passive integration system of radar
CN106294222A (en) * 2016-08-03 2017-01-04 浪潮电子信息产业股份有限公司 A kind of method and device determining PCIE device and slot corresponding relation
CN106445869A (en) * 2016-09-20 2017-02-22 烟台大学 FPGA (field programmable gate array) and PCIe (peripheral component interface express) based high-speed data exchange architecture
CN108627805A (en) * 2018-03-28 2018-10-09 安徽四创电子股份有限公司 A kind of radar signal data acquisition and analysis system and its analysis method
CN108762939A (en) * 2018-06-29 2018-11-06 郑州云海信息技术有限公司 A kind of PCIe port resource allocation methods, system and equipment and storage medium
CN109471679A (en) * 2018-11-19 2019-03-15 郑州云海信息技术有限公司 The method that a kind of pair of PCIE exchange chip configuration file is configured

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
乞耀龙 等: "基于光纤模式数据采集方案的阵列快拍成像雷达", 《信号处理》 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111367837A (en) * 2020-03-03 2020-07-03 山东超越数控电子股份有限公司 Data interface board of reconfigurable radar signal processing hardware platform
CN111367837B (en) * 2020-03-03 2022-05-31 超越科技股份有限公司 Data interface board of reconfigurable radar signal processing hardware platform
CN112444814A (en) * 2020-11-11 2021-03-05 安徽四创电子股份有限公司 Digital array weather radar signal processor based on PCIE optical fiber acquisition card
CN113691468A (en) * 2021-08-23 2021-11-23 北京电子工程总体研究所 Configuration method of full-wire-speed distribution switching device for realizing port self-adaption

Similar Documents

Publication Publication Date Title
CN109975764A (en) A kind of transmission of general purpose radar integratedization high speed fibre and control interface plate and its application
CN102833002B (en) Data transmission device and method supporting fibre channel protocol
CN111090221B (en) PCIe DMA data transmission system and method for direct-write lithography system
CN103106169B (en) Based on the expansion framework of the high speed bus interface of aurora agreement
CN203224621U (en) Weather radar high-speed data transmission device based on PCI-E bus
CN105281783A (en) Signal decoding unit based on FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) and realization method for signal decoding unit based on FPGA and DSP
CN103605632A (en) Method and device for communication between AXI (advanced extensible interface) bus and AHB (advanced high-performance bus)
US20040205276A1 (en) USB interface extension through split transaction protocol
CN116647247B (en) Signal transceiver and signal receiving and transmitting system suitable for flexible connection
CN114297124B (en) Communication system of SRIO high-speed bus based on FPGA
CN108462620B (en) Gilbert-level SpaceWire bus system
CN104991880A (en) FC-AE-ASM communication board card based on PCI-E interface
CN208538025U (en) A kind of server for supporting 10 hot-plug hard disks
CN105159850A (en) FPGA based multi-channel data transmission system
CN104346310A (en) Data exchange circuit and method of high-performance I2C slave equipment
CN212647461U (en) Synchronous or asynchronous serial communication control circuit based on PCI bus
CN109062837A (en) A kind of usb signal light teletransmission control module and method based on FPGA
CN100349153C (en) Method for realizing output control and device for controlling interface card by mainboard
CN201487546U (en) Gas filling machine with USB storage and transmission module
CN206805410U (en) A kind of PCIE expansion board clampings applied on the server
CN110012369A (en) A kind of FC sonet card
CN110502070A (en) Node mainboard device suitable for super integration rack
CN215006296U (en) Distributed data transmission system based on FPGA
CN215072416U (en) Centralized KVM receiver
CN113051208B (en) Clock control circuit and terminal equipment

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20190705