CN109972204B

CN109972204B - Ultra-thin ultra-flat wafer and method for manufacturing the same

Info

Publication number: CN109972204B
Application number: CN201711458484.4A
Authority: CN
Inventors: 朱厚彬; 张秀全; 胡卉; 薛海蛟; 李真宇
Original assignee: Jinan Jingzheng Electronics Co Ltd
Current assignee: Jinan Jingzheng Electronics Co Ltd
Priority date: 2017-12-28
Filing date: 2017-12-28
Publication date: 2021-09-17
Anticipated expiration: 2037-12-28
Also published as: CN109972204A

Abstract

An ultra-thin ultra-flat wafer and a method of manufacturing an ultra-thin ultra-flat wafer are provided, which may include the steps of: providing a substrate base plate and a target wafer base plate both having polishing surfaces; spin-coating a protective adhesive layer on the polished surface of the substrate base plate, and then grinding and thinning the back surface of the substrate base plate opposite to the polished surface; cleaning the target wafer substrate and the ground and thinned substrate; directly contacting the polished surface of the target wafer substrate with the polished surface of the substrate to form a bond; grinding and thinning a target wafer substrate in the bonding body, and polishing to enable the target wafer substrate to reach a target thickness; and immersing the polished bonding body into a selective corrosion dissolving solution to remove the substrate base plate, thereby obtaining the ultrathin ultra-flat wafer.

Description

Ultra-thin ultra-flat wafer and method for manufacturing the same

Technical Field

The invention relates to an ultrathin hyperplane and a preparation method thereof, in particular to a self-supporting quartz, lithium tantalate and lithium niobate ultrathin hyperplane with the thickness of 1-100 mu m, double-sided mirror polishing, the total thickness deviation of 0.005-1 mu m and the size of 2-12 inches, and a method for preparing the ultrathin hyperplane by using a grinding and polishing process.

Background

In order to meet the requirements of miniaturization, intellectualization, integration and energy conservation of electronic components, the packaging industry focuses on three-dimensional packaging, so that the packaging volume is reduced, and the device performance is improved. With the trend of decreasing packaging space, the thickness requirement of the wafer is also increasingly developing towards ultra-thinning. Generally, the thickness of the chip used in the more advanced stack package is less than 100 μm. As packaging technology develops and the demand for electronic devices increases, the number of layers stacked increases, requiring the thickness of the wafer to be thinner. Therefore, the ultra-thin ultra-flat chip plays a more important role in the future packaging industry, and has a very wide application prospect. In the field of pyroelectric sensing, ultrathin lithium tantalate is required because the sensitivity of the device is inversely proportional to the thickness. In the field of crystal oscillators, quartz wafers as low as 10 μm or less are required to achieve applications of 100MHz and above due to frequency and thickness dependence. In the field of true zero-order wave plates, the phase retardation is directly related to the thickness, and ultrathin quartz wafers with the thickness of 10-60 mu m are also needed according to different used wavelengths.

At present, the mainstream process for thinning the chip is based on wafer self-rotation grinding, namely, a wafer to be processed is fixed on a rotating porous ceramic sucking disc by using a vacuum sucking disc, and a grinding wheel rotating at a high speed downwards grinds and thins the wafer from the surface layer. Then, the surface of the wafer thinned by grinding is polished to remove surface damage caused by grinding, and a surface with a mirror surface effect is obtained. In general, a common wafer thinning technique is only required to thin a wafer to a thickness of 200 μm to 400 μm from the time of completion of wafer processing. Within this range, the wafer is sufficiently thick to be strong enough to tolerate damage and stress to the wafer during thinning and polishing, while also being sufficiently rigid to maintain the wafer in its original flat condition.

However, ultra-thin wafer thinning techniques require thinning the wafer thickness to below 100 μm, even to several microns. As the thickness of the wafer decreases, the strength of the wafer decreases, and the micro-cracks formed during the thinning process have an increasing effect on the wafer, and the wafer is greatly deformed and curled under the action of its own weight, which may be fatally damaged by any hard edge contact. The preparation and industrial processing of the ultra-thin and ultra-flat wafer substrate are difficult points in the industry at present, and the processing method of the ultra-thin and ultra-flat wafer at present mainly comprises the following steps: firstly, a wafer to be ground is attached to a substrate wafer by wax or other bonding agents, then the top layer wafer is thinned and polished, the bonding agents are removed by heating or chemical solution dissolving, and the ultrathin ultra-flat wafer is taken down and cleaned. The biggest difficulty faced by the process is that after the wafer is thinned to the thickness of several microns to dozens of microns, the mechanical strength of the wafer is greatly reduced, mechanical acting force needs to be applied to the surface of the wafer in the subsequent processes of grinding, polishing, taking a wafer and cleaning, the wafer is very easy to crack, and the yield is low. These problems are solved by expensive equipment, which is very expensive due to various factors. Furthermore, since wax or other adhesives are used in the mounting process, the thickness uniformity of the wafer is affected by the uniformity of the adhesives, and it is difficult to achieve an overall thickness deviation of less than 3 μm. The thickness distribution of the film is tested by using thickness testing equipment, and then the ion beam thinning method is used, so that the ultra-flat wafer with the thickness uniformity as low as a few microns or tens of nanometers can be obtained, but the processing cost is high and the efficiency is low.

In addition, the method for thinning the lithium niobate and lithium tantalate wafers by corrosion has low processing efficiency because the lithium niobate and lithium tantalate wafers have low chemical activity and are very difficult to corrode, and the wafers prepared by the corrosion process have high surface roughness, which causes light scattering to influence optical performance and high noise in electrical use, thus being not suitable for preparing ultrathin and ultra-flat wafers.

Disclosure of Invention

In order to solve the above problems in the prior art, it is an object of the present invention to provide an ultra-thin ultra-flat wafer and a method of manufacturing the ultra-thin ultra-flat wafer.

According to the invention, the ultrathin ultra-flat wafer is provided, the thickness range of the ultrathin ultra-flat wafer can be 1-100 mu m, the total thickness deviation can be 0.005-1 mu m, both surfaces are mirror polished, the surface roughness can be lower than 1nm, and the size can be 2-12 inches.

According to the present invention, there is provided a method of manufacturing an ultra-thin ultra-flat wafer, which may include the steps of: providing a substrate base plate and a target wafer base plate both having polishing surfaces; spin-coating a protective adhesive layer on the polished surface of the substrate base plate, and then grinding and thinning the back surface of the substrate base plate opposite to the polished surface; cleaning the target wafer substrate and the ground and thinned substrate; directly contacting the polished surface of the target wafer substrate with the polished surface of the substrate to form a bond; grinding and thinning a target wafer substrate in the bonding body, and polishing to enable the target wafer substrate to reach a target thickness; and immersing the polished bonding body into a selective corrosion dissolving solution to remove the substrate base plate, thereby obtaining the ultrathin ultra-flat wafer.

In example embodiments, the ultra-thin ultra-flat wafer may have a diameter of 2 inches to 12 inches, a thickness of 1 μm to 100 μm, and an overall thickness deviation of 0.005 to 1 μm.

In example embodiments, the target wafer substrate may be a single-crystal lithium tantalate substrate, a single-crystal lithium niobate substrate, a quartz substrate, a silicon carbide substrate, a gallium arsenide substrate, or the like, the substrate may be a silicon substrate, a quartz substrate, a glass substrate, or the like, the target wafer substrate and the substrate may be different from each other in material, and the adhesive layer may include at least one of a strengthener, a photoresist, and a liquid wax.

In an example embodiment, in the step of cleaning the target wafer substrate and the ground thinned substrate, the cleaning is semiconductor level clean cleaning.

In an example embodiment, in the step of grinding and thinning the back surface of the substrate base plate opposite to the polished surface, the thickness of the thinning removal of the back surface of the substrate base plate opposite to the polished surface may be greater than 2 μm.

In an example embodiment, the method may further include performing an annealing process on the bonded body after forming the bonded body, wherein the annealing temperature may be 100 ℃ to 300 ℃ and the annealing time may be 0.5h to 4 h.

In an example embodiment, in the step of grinding and thinning the target wafer substrate in the bond, the thickness of the target wafer substrate of the bond may be thinned to be 0.3 μm to 10 μm greater than the target thickness.

In an exemplary embodiment, in the steps of grinding and thinning the back surface of the substrate base opposite to the polished surface and grinding and thinning the target wafer substrate in the bond, grinding may be performed using a vacuum chuck having the same inclination angle of the spindle of the grinder and the same taper so as to obtain a uniform front-to-back surface profile.

In an example embodiment, the method may further include: before polishing the target substrate after being thinned, a circle of the edge of the target wafer substrate may be trimmed, and the width of the trimming cut may be 0.3mm to 3 mm.

In example embodiments, the base substrate may be thinned to 50-200 μm before immersing the polished bond in a selective etching solution to reduce the time required to remove the base substrate.

The beneficial effects of the invention are: the method for preparing the ultrathin ultra-flat wafer can prepare the ultrathin ultra-flat wafer with the large size diameter of 2-12 inches, the micron-sized thickness of 1-100 mu m, the TTV of less than 1 mu m, low residual stress and low defect density and self-supporting double-sided mirror polishing.

Drawings

These and/or other aspects will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a flowchart illustrating a method of fabricating an ultra-thin ultra-flat wafer according to an exemplary embodiment of the present invention.

Fig. 2 is a schematic view illustrating a structure of spin coating a layer on a polishing surface of a substrate base according to an exemplary embodiment of the present invention.

Fig. 3 is a schematic diagram illustrating a structure of forming a bond according to an exemplary embodiment of the present invention.

Fig. 4 is a schematic structural diagram illustrating grinding and thinning of a target wafer substrate in a bond according to an exemplary embodiment of the invention.

Fig. 5 is a schematic structural view illustrating a trimming process of a target wafer substrate in a bond according to an exemplary embodiment of the present invention.

Fig. 6 is a schematic configuration diagram illustrating a polishing process performed on a target wafer substrate in a bond according to an exemplary embodiment of the present invention.

Fig. 7 is a schematic structural view illustrating an ultra-thin ultra-flat wafer according to an exemplary embodiment of the present invention.

Detailed Description

Embodiments of the present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the embodiments of the invention to those skilled in the art. In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant teachings. However, it will be apparent to one skilled in the art that the present teachings may be practiced without such details. In other instances, well known methods, procedures, and components have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings. Like reference numerals in the drawings denote like elements, and thus their description will not be repeated. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.

A method of fabricating an ultra-thin, ultra-flat wafer according to an exemplary embodiment of the present invention will now be described in detail below with reference to fig. 1 to 7.

Referring to fig. 1, a method of fabricating an ultra-thin ultra-flat wafer according to an exemplary embodiment of the present invention includes the steps of: providing a substrate base plate and a target wafer base plate both having polishing surfaces; spin-coating a protective adhesive layer on the polished surface of the substrate base plate, and then grinding and thinning the back surface of the substrate base plate opposite to the polished surface; cleaning the target wafer substrate and the ground and thinned substrate; directly contacting the polished surface of the target wafer substrate with the polished surface of the substrate to form a bond; grinding and thinning a target wafer substrate in the bonding body, and polishing to enable the target wafer substrate to reach a target thickness; and immersing the polished bonding body into a selective corrosion dissolving solution to remove the substrate base plate, thereby obtaining the ultrathin ultra-flat wafer.

The method illustrated in fig. 1 will be described in detail below with reference to fig. 2 to 7. Fig. 2 to 7 are sectional views illustrating a method of fabricating an ultra-thin ultra-flat wafer according to an exemplary embodiment of the present invention. Specifically, fig. 2 is a schematic structural view showing a spin-on-coat layer on a polished surface of a substrate according to an exemplary embodiment of the present invention, fig. 3 is a schematic structural view showing formation of a bond according to an exemplary embodiment of the present invention, fig. 4 is a schematic structural view showing grinding and thinning of a target wafer substrate in the bond according to an exemplary embodiment of the present invention, fig. 5 is a schematic structural view showing a trimming process of the target wafer substrate in the bond according to an exemplary embodiment of the present invention, fig. 6 is a schematic structural view showing a polishing process of the target wafer substrate in the bond according to an exemplary embodiment of the present invention, and fig. 7 is a schematic structural view showing an ultra-thin ultra-flat wafer according to an exemplary embodiment of the present invention.

First, a base substrate and a target wafer substrate each having a polished surface are provided.

According to an exemplary embodiment of the present invention, the substrate may be a silicon substrate having a single-sided or double-sided mirror polishing, a quartz substrate, a glass substrate, or the like, but the present invention is not limited thereto. According to an exemplary embodiment of the present invention, the target wafer substrate may be a single-crystal lithium tantalate substrate, a single-crystal lithium niobate substrate, a quartz substrate, a silicon carbide substrate, a gallium arsenide substrate, or the like, which has a single-sided or double-sided mirror polishing, but the present invention is not limited thereto. According to an exemplary embodiment of the present invention, the target wafer substrate and the substrate are selected from different materials as long as the combination of the target substrate, the substrate and the etching solution conforms to the principle of removing only the substrate without etching and dissolving the target substrate. According to an exemplary embodiment of the present invention, the substrate base plate and the target wafer base plate may be subjected to a surface polishing process by means of, for example, chemical mechanical polishing such that the surface roughness of the substrate base plate and the target wafer base plate is less than 1nm so that the requirement of direct bonding can be satisfied.

Then, a glue coating layer is screwed on the polished surface of the substrate base plate, and then the back surface of the substrate base plate opposite to the polished surface is ground and thinned; and cleaning the target wafer substrate and the ground and thinned substrate.

Referring to fig. 2, in an exemplary embodiment of the present invention, the adhesive layer 1 is spin-coated on the polished surface of the base substrate 2, and optionally, the adhesive layer 1 is heated, and the adhesive layer and the base substrate 2 are simultaneously heated to obtain a protective layer having a certain strength. The adhesive layer 1 includes at least one of an enhancer, a photoresist, and a liquid paraffin, and preferably, may include an enhancer and a photoresist, but the present invention is not limited thereto. The protective layer can prevent the polished surface of the base substrate 2 from being scratched or damaged, so as to avoid adverse effects on the subsequent bonding process. Then, the surface with the protective layer is fixed on a porous ceramic chuck of a grinder with the surface facing downward, the back surface of the substrate base plate 2 opposite to the polished surface is ground and thinned to remove a thickness larger than 2 μm (for example, about 10 μm), and the thickness uniformity of the substrate base plate 2 is adjusted by adjusting the inclination angle of the main axis of the grinder to obtain a substrate base plate having a specific thickness profile.

Next, the target wafer substrate and the ground and thinned substrate are cleaned.

In an exemplary embodiment of the present invention, a substrate and a target wafer substrate are cleaned in order to obtain a clean surface advantageous for a subsequent bonding process. For example, the substrate base substrate and the target wafer substrate may be cleaned using a semiconductor-level clean cleaning process, but the present invention is not limited thereto.

Alternatively, the polished substrate may be soaked with acetone and then an absolute ethanol solution before the substrate and the target wafer substrate are cleaned using a semiconductor-grade cleaning process to remove the organic protective layer, but the present invention is not limited thereto.

Next, the polished surface of the target wafer substrate 3 is brought into direct contact with the polished surface of the base substrate 2 to form a bond.

In the exemplary embodiment of the present invention, the polished surface of the target wafer substrate 3, each having a clean surface, is brought into direct contact with the polished surface of the base substrate 2 by a direct bonding method at room temperature, and a bond including a two-layer structure of the target wafer substrate 3 and the base substrate 2 is formed by intermolecular forces (for example, van der waals forces) of the surfaces of the polished surfaces of the target wafer substrate 3 and the base substrate 2, as shown in fig. 3.

In an exemplary embodiment of the present invention, an annealing process is optionally performed on the formed bond. For example, the annealing process may be performed on the bond at a temperature of 100 ℃ to 300 ℃ for 0.5h to 4h (preferably, 3h to 4h), so as to convert intermolecular forces between the target wafer substrate 3 and the substrate 2 into oxygen bonds having stronger bond energy, which greatly increases the bonding force between the target wafer substrate 3 and the substrate 2, so that the integrity of the bond can be well ensured even if the target wafer substrate 3 is thinned to a thickness of several micrometers in the subsequent steps. However, the exemplary embodiments of the present invention are not limited thereto. For example, in the case where the bonding force between the target wafer substrate 3 and the substrate 2 is strong, the step of performing the annealing process on the bond may be omitted.

And then, grinding and thinning the target wafer substrate in the bonding body, and polishing to enable the target wafer substrate to reach the target thickness.

In an exemplary embodiment of the present invention, as shown in fig. 4, in order to thin the target wafer substrate 3 'as much as possible, it may be ground down to be 0.3 to 10 μm greater than the target thickness, for example, to thin the target wafer substrate 3' to 2 to 101 μm. And grinding the back surface of the substrate base plate 2 opposite to the polished surface by using a vacuum chuck with the same inclination angle of a main shaft of the grinder and the same taper while grinding and thinning so as to ensure that the surface types of the two grinding processes are consistent.

In the exemplary embodiment of the present invention, the target wafer substrate 3' after grinding thinning is optionally subjected to a trimming process as needed, as shown in fig. 5. Since the edge corner of the target wafer substrate 3 'may become sharp after being thinned from a thickness of 250 to 1000 μm to a thickness of 5 to 100 μm, which may cause a problem of chipping in a subsequent polishing process, a round of the target wafer substrate 3' having a size of 0.3 to 3mm at the edge thereof needs to be cut off by a dicing saw or a chamfering machine to improve the yield.

In the exemplary embodiment of the present invention, as shown in fig. 6, the target wafer substrate 3 ″ after being ground to be thinned is subjected to a surface polishing treatment to remove a thickness of 0.5 μm to 2 μm to reach the target thickness while obtaining a mirror-polished surface. When the surface polishing treatment is performed on the target wafer substrate 3 ″, a sufficient polishing removal amount should be ensured to completely remove the grinding lines of the ground surface, and to obtain a relatively good surface quality of an ultra-thin and ultra-flat wafer. According to an exemplary embodiment of the present invention, the surface polishing process may be performed by chemical mechanical polishing, but the present invention is not limited thereto.

Finally, the polished bond is immersed in a selective etching solution to remove the base substrate, thereby obtaining an ultra-thin ultra-flat wafer 3 ″.

In an exemplary embodiment of the invention, as shown in fig. 7, the polished bond is immersed in a selective etch dissolution solution, which may be a chemical solution having significant selective etch dissolution for the substrate base plate 2 and the target wafer base plate 3 ", i.e., the substrate base plate 2 can be etched quickly and without etching or etching the target wafer base plate 3 very slightly. The selective etching solution dissolves the substrate base plate 2 completely to obtain an ultra-thin self-supporting double-polished ultra-thin ultra-flat wafer. According to an exemplary embodiment of the present invention, the selective etching dissolution solution may be a tetramethylammonium hydroxide (TMAH) solution, HF: HNO₃CHECOOH solution, oxalic acid catechol solution, sodium hydroxide (NaOH) solution, potassium hydroxide (KOH) strong alkali solution, etc., but the present invention is not limited theretoThe exemplary embodiments of (1) are not limited thereto.

The ultra-thin ultra-flat wafer manufactured according to the method of manufacturing an ultra-thin ultra-flat wafer of the exemplary embodiment of the present invention may have a diameter of 2 inches to 12 inches, a thickness of 1 μm to 100 μm, and an overall thickness deviation of 0.005 to 1 μm.

In addition, before the polished bonding body is immersed in the selective etching solution, the substrate base plate can be thinned to 50-200 μm, and then the substrate base plate 2 can be removed by etching and dissolving. Thus, the amount of the substrate 2 to be removed by etching and dissolving can be reduced, thereby reducing the etching and dissolving time and improving the efficiency.

Hereinafter, a specific example of preparing an ultra-thin ultra-flat wafer according to the present invention will be described in detail.

Example 1

Providing a lithium tantalate wafer with the thickness of 0.2 mm-1 mm in Z-cut of 3 inches as a target wafer substrate, providing a 3-inch monocrystalline silicon wafer as a substrate, spin-coating an enhancer and a photoresist on the surface of the monocrystalline silicon wafer, heating and curing the photoresist to form a protective layer on a polished surface, placing the protective layer on a porous ceramic sucker of a grinder with the protective layer facing downwards, adjusting the inclination angle of a main shaft of the grinder, grinding to remove the thickness of 10 mu m, and adjusting the TTV of the substrate to be less than 1 mu m, thereby obtaining the monocrystalline silicon wafer with the surface type of which the center is slightly higher and the edge is slightly lower. Soaking the ground monocrystalline silicon wafer by using acetone and then absolute ethyl alcohol solution to remove the organic matter protective layer; and (3) carrying out grade cleaning on the monocrystalline silicon wafer and the lithium tantalate wafer to obtain a clean surface capable of being directly bonded.

And directly contacting the polished surface of the lithium tantalate wafer with the polished surface of the monocrystalline silicon wafer at room temperature by using a direct bonding process to obtain a composite substrate bonding body of the monocrystalline silicon wafer with a bottom layer of 3 inches and the Z-cut lithium tantalate wafer at the top layer.

And annealing the bonding body of the composite substrate at 220 ℃ for 4h in an atmosphere to enhance the bonding force of the bonding body.

The inclination angle of the main shaft of the grinder was adjusted to a value of the inclination angle of the main shaft which was the same as that when the single crystal silicon wafer was ground, and the lithium tantalate wafer was thinned to 21 μm by the wafer grinding process.

And (4) performing edge cutting treatment on the ground bonding body, and removing a circle of lithium tantalate wafer with the edge size of 1mm on the top layer by using an edge cutting machine. Performing surface polishing treatment by adopting chemical mechanical polishing, and polishing the lithium tantalate wafer to the thickness of 20 mu m; and immersing the polished bonding body into TMAH solution with the mass fraction of 25%, corroding at the temperature of 90 ℃ for 5h, and completely corroding and dissolving the monocrystalline silicon wafer to obtain the self-supporting ultrathin ultra-flat wafer with the thickness of 20 mu m, the TTV of 0.5 mu m and the diameter of 74.2 +/-0.5 mm.

Example 2

Providing a single crystal lithium niobate wafer with 6 inches X-cut thickness of 0.2 mm-1 mm as a target wafer substrate, providing a single crystal silicon substrate wafer with 6 inches as a substrate, spin-coating a reinforcer and a photoresist on the surface of the single crystal silicon substrate wafer, heating and curing the photoresist to form a protective layer on a polished surface, placing the protective layer downwards on a porous ceramic sucker of a grinder, adjusting the inclination angle of a spindle of the grinder, grinding to remove the thickness of 10 mu m, adjusting the TTV of the single crystal silicon substrate wafer to be less than 1 mu m, and obtaining the single crystal silicon substrate wafer with a surface type with a slightly higher center and a slightly lower edge. Soaking the ground monocrystalline silicon substrate wafer by using acetone and then absolute ethyl alcohol solution to remove the organic matter protective layer; and (3) carrying out grade cleaning on the monocrystalline silicon substrate wafer and the monocrystalline lithium niobate wafer to obtain a clean surface capable of being directly bonded.

And directly attaching the polished surface of the single-crystal lithium niobate wafer and the polished surface of the silicon wafer by using a bonding process at room temperature to obtain a bonded body.

And annealing the bonding body, wherein the annealing temperature is 180 ℃, the annealing time is 4h, and the environment is the atmosphere.

And grinding the single crystal lithium niobate wafer in the bonding body to reduce the thickness of the single crystal lithium niobate wafer to 12 mu m.

After the edge cutting treatment of the grinded bonding body, the surface polishing treatment is carried out by adopting a chemical mechanical polishing mode, the thickness of the single crystal lithium niobate wafer is reduced to 10 mu m, and the single crystal lithium niobate wafer is immersed in HF (hydrogen fluoride) HNO (hydrogen fluoride oxide)₃The single crystal silicon substrate wafer was thoroughly dissolved by etching at room temperature for 4 hours in a solution of 3:1.5:0.5 CHECOOH to obtain a wafer having a thickness of 10 μm.

Example 3

Providing a monocrystalline quartz wafer with the thickness of 0.2-1 mm as a target wafer substrate, providing a 3-inch monocrystalline silicon wafer as a substrate, spin-coating an enhancer and a photoresist on the polished surface of the monocrystalline silicon wafer, heating and curing the photoresist to form a protective layer on the polished surface, placing the protective layer downwards on a porous ceramic sucker of a grinding machine, adjusting the inclination angle of a main shaft of the grinding machine, grinding and removing the thickness of 10 mu m, and adjusting the TTV of the monocrystalline silicon wafer to be less than 1 mu m to obtain the substrate wafer substrate with a surface type with a slightly higher center and a slightly lower edge. Soaking the ground monocrystalline silicon wafer by using acetone and then absolute ethyl alcohol solution to remove the organic matter protective layer; and (3) carrying out grade clean cleaning on the monocrystalline silicon wafer and the monocrystalline quartz wafer to obtain a clean surface capable of being directly bonded.

And bonding the polished surface of the monocrystalline silicon quartz wafer and the polished surface of the monocrystalline silicon wafer by using a bonding process at room temperature to obtain the bonded body.

And annealing the bonding body, wherein the annealing temperature is 250 ℃, the annealing time is 4h, and the environment is the atmosphere.

And grinding the monocrystalline quartz wafer in the bonding body to reduce the thickness of the monocrystalline quartz wafer to 22 mu m.

And after the edge cutting treatment is carried out on the ground bonding body, the surface polishing treatment is carried out in a chemical mechanical polishing mode, the monocrystalline quartz wafer is thinned to the thickness of 20 mu m, then the monocrystalline quartz wafer is immersed in NaOH solution with the mass fraction of 30% and is corroded for 3h at the temperature of 80-90 ℃ so as to completely dissolve the monocrystalline silicon wafer, and therefore the wafer with the thickness of 20 mu m is obtained.

It can be seen from examples 1 to 3 that the ultra-thin ultra-flat wafer of the self-supporting double-sided mirror polishing having a large size diameter of 2-12 inches, a micron-sized thickness of 1-100 μm, a TTV of less than 1 μm, a low residual stress and a low defect density can be prepared by using the bonding technique and the wafer etching process according to the present invention.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. The embodiments should be considered in descriptive sense only and not for purposes of limitation. Therefore, the scope of the invention is defined not by the detailed description of the invention but by the appended claims, and all differences within the scope will be construed as being included in the present invention.

Claims

1. A method of making an ultra-thin, ultra-flat wafer, the method comprising the steps of:

providing a substrate base plate and a target wafer base plate both having polishing surfaces;

spin-coating a protective adhesive layer on the polished surface of the substrate base plate, and then grinding and thinning the back surface of the substrate base plate opposite to the polished surface;

cleaning the target wafer substrate and the ground and thinned substrate;

directly contacting the polished surface of the target wafer substrate with the polished surface of the substrate to form a bond;

grinding and thinning a target wafer substrate in the bonding body, and polishing to enable the target wafer substrate to reach a target thickness; and

immersing the polished bonding body into a selective corrosion dissolving solution to remove the substrate base plate so as to obtain an ultrathin ultra-flat wafer,

wherein, in the step of grinding and thinning the back surface of the substrate base plate opposite to the polished surface, the thinned and removed thickness of the back surface of the substrate base plate opposite to the polished surface is more than 2 μm, and the thickness uniformity of the substrate base plate is adjusted by adjusting the inclination angle of the main shaft of the grinder to obtain the substrate base plate with a predetermined thickness profile,

in the step of grinding and thinning the target wafer substrate in the bonding body, the thickness of the target wafer substrate of the bonding body is thinned to be 0.3-10 mu m larger than the target thickness.

2. The method of claim 1, wherein the ultra-thin ultra-flat wafer has a diameter of 2 to 12 inches, a thickness of 1 to 100 μm, and an overall thickness variation of 0.005 to 1 μm.

3. The method of claim 1, wherein,

the target wafer substrate is a single crystal lithium tantalate substrate, a single crystal lithium niobate substrate, a quartz substrate, a silicon carbide substrate or a gallium arsenide substrate,

the substrate base plate is a silicon base plate, a quartz base plate or a glass base plate,

the target wafer substrate and the substrate are of different materials from each other,

the glue layer comprises at least one of a reinforcer, photoresist and liquid paraffin.

4. The method of claim 1, wherein in the step of cleaning the target wafer substrate and the ground thinned substrate, the cleaning is a semiconductor grade clean cleaning.

5. The method of claim 1, further comprising performing an annealing process on the bond after forming the bond, the annealing temperature being between 100 ℃ and 300 ℃ and the annealing time being between 0.5h and 4 h.

6. The method as claimed in claim 1, wherein in the steps of grinding and thinning a back surface of the substrate base opposite to the polished surface and grinding and thinning a target wafer substrate in the bond, grinding is performed with a vacuum chuck of the same inclination of a main axis of the grinder and the same taper to obtain a uniform front-to-back surface profile.

7. The method of claim 1, further comprising: before polishing the target substrate after the grinding and thinning, performing trimming treatment on one circle of the edge of the target wafer substrate,

wherein the width of the cut edge is 0.3 mm-3 mm.

8. The method of claim 1, further comprising:

before immersing the polished bonding body into the selective corrosion dissolving solution, the substrate base plate is thinned to 50-200 mu m so as to reduce the time required for removing the substrate base plate.

9. An ultra-thin, ultra-flat wafer prepared according to the method of any one of claims 1 to 8, having a thickness in the range of 1 to 100 μm, an overall thickness variation of 0.005 to 1 μm, mirror-polished on both sides, a surface roughness below 1nm, and a size of 2 to 12 inches.