CN109941962B - Method for electrically connecting high-density slope step nanowires - Google Patents
Method for electrically connecting high-density slope step nanowires Download PDFInfo
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- CN109941962B CN109941962B CN201910240844.6A CN201910240844A CN109941962B CN 109941962 B CN109941962 B CN 109941962B CN 201910240844 A CN201910240844 A CN 201910240844A CN 109941962 B CN109941962 B CN 109941962B
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Abstract
The invention discloses a method for electrically connecting high-density slope surface step nanowires, which utilizes photoresist to realize different recession rates caused by different local curvatures in an alternate etching process, thereby realizing a step surface which is much wider than a low-curvature (or straight) position at a high-curvature (such as two ends of a strip) position of a step, being beneficial to conveniently preparing electrodes on a wide step, realizing respective electrical connection of high-density nanowire arrays on steep walls and providing great convenience for realizing a discrete nanowire field effect device stacked in high density.
Description
Technical Field
The invention relates to a method for obtaining high-density slope steps by a cyclic alternating etching process, in particular to a method for electrically connecting high-density slope step nanowires.
Background
Crystalline silicon or related semiconductor nanowires (Nanowire) are key building blocks for developing a new generation of high-performance micro-nano electronic logic, sensing and display applications. To better comply with planar electronic technology and achieve position integration, the inventor of the present application originally proposed a planar solid-liquid-solid (IP SLS) growth mode: amorphous silicon is used as a precursor, and the crystalline silicon nanowire structure grows by absorbing the amorphous silicon by low-melting-point metal indium and tin nanoparticles. Meanwhile, by utilizing different etching responses of the mask layer and the substrate to etching gas, the multistage slope nano-step can be prepared by a circular alternative etching method, the three-dimensional step is taken as a guide, and metal liquid drops move along the step edge under the attraction of amorphous silicon covered by the step edge, so that nanowires grow on the step edge, and the high-density slope step nanowire array is realized.
However, such high density nanowire arrays face problems of difficult application in electronic devices. In a micro-nano electronic device, in order to meet the requirements of testing, packaging and the like, the size of a metal electrode electrically connected with a nanowire channel is often micron-sized, the distance between slope steps realized before is only nano-sized, and the metal electrode cannot be fully and reliably connected with the nanowire due to a large size difference, so that great challenges are brought to a manufacturing process, the utilization rate of the nanowire as the channel is reduced, and the electronic device with high current and high integration level is difficult to prepare.
Disclosure of Invention
The purpose of the invention is as follows: the invention provides a method for electrically connecting high-density slope surface step nano wires, which is characterized in that the shapes of mask layers are designed, namely the short sides have larger curvature and the long sides have smaller curvature, and the mask layer etching gas etches the short sides with larger curvature more quickly, so that densely-arranged guide nano steps with different and controllable intervals in the length and width directions can be formed on the slope surface by utilizing a cyclic alternative etching method, thereby being beneficial to conveniently preparing electrodes on wide steps, realizing respective electrical connection of high-density nano wire arrays on steep walls and providing great convenience for realizing discrete nano wire field effect devices stacked in high density.
The technical scheme is as follows:
a method of electrically connecting high density slope step nanowires, comprising the steps of:
1) depositing an insulating dielectric layer with the thickness of 200-1000 nm on a substrate by utilizing a PECVD (plasma enhanced chemical vapor deposition) or PVD (physical vapor deposition) process;
2) defining the step edge by utilizing photoetching, electron beam direct writing or mask plate technology, so that the short side curvature is larger and the long side curvature is smaller; etching the insulating medium layer by utilizing an inductive coupling plasma etching or reactive plasma etching process to form a vertical step side wall; the etching thickness cannot exceed the thickness of the insulating medium layer;
3) covering a photoresist mask layer on the top of the step, and etching by an ICP (inductively coupled plasma) etching process; then SF is introduced6、C4F8、CF4Or Ar etches the silicon oxide dielectric layer exposed at the edge of the photoresist mask layer; performing cyclic etching on the two steps for a plurality of times to obtain a multistage slope surface nanometer step, wherein the stage number of the step corresponds to the number of the cyclic etching times;
4) locally depositing a band-shaped catalytic metal layer with the thickness of 20-100 nm at one end of the slope nano step through photoetching, thermal evaporation technology or sputtering technology; raising the temperature to be higher than the melting point of the catalytic metal layer, and introducing reducing gas plasma for treatment to convert the catalytic metal layer covering one end of the slope nano step into separated metal nano particles;
5) reducing the temperature below the melting point of the metal nano particles, and depositing and covering an amorphous semiconductor precursor film layer corresponding to the nanowire to be grown on the surface of the whole structure;
6) in a vacuum or inert gas protection environment, raising the temperature to be higher than the melting point of the catalytic metal, so that the metal nano particles are re-melted, the front end of the metal nano particles starts to absorb the amorphous silicon layer, and the rear end of the metal nano particles deposits crystalline nano wires; the nano wires grow in parallel by taking the multistage steps on the slope nano steps as guide channels, and a nano wire array growing on the slope nano steps in parallel is obtained;
7) removing the residual amorphous silicon precursor film layer by hydrogen plasma, ICP or RIE etching process;
8) and forming patterns at two ends of the slope nano step by utilizing photoetching or electron beam direct writing, and then depositing a layer of discrete metal electrode with the thickness of 50-200 nm by utilizing a thermal evaporation or sputtering process to form reliable electrical connection for the nanowires respectively.
In the step 1), the substrate is made of crystalline silicon, glass, aluminum foil, silicon nitride, silicon oxide, silicon carbide, sapphire, polyimide or poly-p-phthalic plastic.
In the step 1), the thickness of the insulating medium layer is 100-600 nm.
In the step 1), the insulating dielectric layer is made of silicon oxide.
In the step 3), the height of each step is within the range of 1-1000 nanometers, and the circulating etching frequency is 1-10; the distance in the length direction is 2-3 times of the distance in the width direction.
The catalytic metal is indium.
The precursor film layer is amorphous silicon a-Si, amorphous germanium a-Ge, amorphous carbon a-C or other amorphous alloy layers or a heterogeneous laminated structure.
And on the slope nano-step, the covering thickness of each layer of the precursor thin film layer is 2-500 nm.
Has the advantages that: 1) by utilizing different etching responses of the mask layer and the substrate to etching gas, the multistage slope surface nanometer step can be obtained by circularly and alternately etching only through one-time photoetching and etching process. The nano wire array can be directly used for guiding the parallel growth of the nano wire on the slope surface to obtain a high-density three-dimensional slope surface nano wire array structure; 2) by the specific design of the mask layer shape, the difference of the mask layer etching gas to the etching speed of the mask layer in two directions is utilized, the step surface with the high curvature (such as two ends of a strip) position much wider than the low curvature (or straight) position is realized, and then the nano wire parallel to the step is grown; 3) the larger distance in the length direction of the slope steps is convenient for preparing metal electrodes in the subsequent process, and the possibility is provided for realizing a high-integration-level and large-current micro-nano electronic device; 4) the discrete electrode fully utilizes each nanowire, the nanowires on one step are not used as a whole, and the number of steps can be controlled by the number of times of circular alternate etching, so that the form is expected to greatly improve the integration level of the device.
Drawings
Fig. 1 is a schematic flow chart of a process for preparing a nanowire electrically connected with a high-density slope step. Wherein, fig. 1a substrate pretreatment, fig. 1b substrate deposition a layer of dielectric layer, fig. 1c etching dielectric layer to form vertical step and cover mask layer, fig. 1d etch back technology to form multi-level slope step, fig. 1e step one end deposition strip catalytic metal layer, fig. 1f hydrogen plasma treatment to form catalytic metal liquid drop, fig. 1g cover amorphous precursor layer, fig. 1h begins to grow nano wire, fig. 1i step two end deposition discrete metal electrode.
Fig. 2 is a SEM schematic view of an electrical connection high density slope step structure provided in the present invention.
Detailed Description
The invention is further elucidated with reference to the drawings and the embodiments.
Fig. 1 is a schematic flow chart of a process for preparing a nanowire electrically connected with a high-density slope step. As shown in fig. 1, the method for electrically connecting high-density slope step nanowires of the invention comprises the following steps:
1) using crystal silicon, glass, aluminium foil, silicon nitrideSilicon oxide, silicon carbide, sapphire, PI (polyimide) or PET (poly terephthalic acid plastic) are used as a substrate, and a layer of insulating medium layer with the thickness of 200-1000 nm is deposited by utilizing a PECVD (plasma enhanced chemical vapor deposition) or PVD (physical vapor deposition) process; in the invention, a more preferable scheme is that a layer of insulating dielectric layer with the thickness of 100-600 nm is deposited by utilizing a PECVD (plasma enhanced chemical vapor deposition) or PVD (physical vapor deposition) process, and the insulating dielectric layer is made of silicon oxide, such as SiO2，Si3N4Etc.;
2) defining the step edge by utilizing photoetching, electron beam direct writing or mask plate technology to ensure that the short side has larger curvature and the long side has smaller curvature, which is beneficial to forming the required step appearance in the subsequent steps; etching the dielectric layer by using an Inductively Coupled Plasma (ICP) etching or reactive plasma etching (RIE) process to form a vertical step side wall; the etching thickness cannot exceed the thickness of the silicon oxide dielectric layer;
3) covering a photoresist mask layer on the top of the step, and introducing O in the ICP etching process2、Cl2Or the etching gas corresponding to the mask layer forms plasma, the photoresist retracts inwards for a certain distance in the horizontal direction while being etched in the vertical direction, and retracts more in the direction of the short side with larger curvature, and then SF is introduced6、C4F8、CF4Or Ar etches the silicon oxide dielectric layer exposed at the edge of the photoresist mask layer; the two steps are carried out alternately in a circulating way, and due to the fact that successive ablation of the mask layer and different ablation rates caused by different local curvatures, the multistage slope nanometer steps with larger step spacing in the length direction and smaller step spacing in the width direction can be finally obtained, and the stage number of the steps corresponds to the number of times of circulating etching; the height of each step is within the range of 1-1000 nanometers, and the cycle period can be 1-10; the distance in the length direction is about 2-3 times of the distance in the width direction;
4) locally depositing a band-shaped catalytic metal layer with the thickness of 20-100 nm at one end of the slope nano step through photoetching, thermal evaporation technology or sputtering technology; raising the temperature to be above the melting point of the catalytic metal layer, introducing reductive gas plasmas such as hydrogen and ammonia gas for treatment, and converting the catalytic metal layer covering one end of the slope nano step into separated metal nano particles; in the present invention, the catalytic metal is indium;
5) reducing the temperature below the melting point of the metal nano particles, and depositing and covering an amorphous semiconductor precursor film layer corresponding to the nanowire to be grown on the surface of the whole structure; the precursor film layer is an amorphous silicon a-Si, amorphous germanium a-Ge, amorphous carbon a-C or other amorphous alloy layers and has a heterogeneous laminated layer (such as a-Ge/a-Si) structure; on the slope nano-step, the thickness of each layer of film is 2-500 nm;
6) in a vacuum or inert gas protection environment, raising the temperature to be higher than the melting point of the catalytic metal, so that the metal nano particles are re-melted, the front end of the metal nano particles starts to absorb the amorphous silicon layer, and the rear end of the metal nano particles deposits crystalline nano wires; by taking the multi-stage steps on the slope as guide channels, nanowire arrays grown on the steps of the slope in parallel are obtained;
7) the residual amorphous silicon precursor film layer can be removed by hydrogen plasma, ICP or RIE etching process; the diameter of the nanowire growing on the slope steps is larger than that of the amorphous film precursor layer remaining on the slope, the diameter is usually 2-3 times of the thickness of the film, and in an ICP (inductively coupled plasma) and RIE (reactive ion etching) process, the etching rate of the amorphous layer is usually higher than that of the crystalline nanowire, so that the amorphous layer on the slope steps is selectively removed;
8) patterns are formed at two ends of the slope nano step by photoetching or electron beam direct writing, and then a layer of discrete metal electrode with the thickness of 50-200 nm is deposited by thermal evaporation or sputtering process to form reliable electrical connection of the nanowires respectively.
Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the details of the foregoing embodiments, and various equivalent changes (such as number, shape, position, etc.) may be made to the technical solution of the present invention within the technical spirit of the present invention, and the equivalents are protected by the present invention.
Claims (8)
1. A method for electrically connecting high-density slope step nanowires is characterized by comprising the following steps: the method comprises the following steps:
1) depositing an insulating dielectric layer with the thickness of 200-1000 nm on a substrate by utilizing a PECVD (plasma enhanced chemical vapor deposition) or PVD (physical vapor deposition) process;
2) defining the step edge by utilizing photoetching or electron beam direct writing technology, so that the short side of the step edge has larger curvature and the long side of the step edge has smaller curvature; etching the insulating medium layer by utilizing an inductive coupling plasma etching or reactive plasma etching process to form a vertical step side wall; the etching thickness cannot exceed the thickness of the insulating medium layer;
3) covering a photoresist mask layer on the top of the step, and etching by an ICP (inductively coupled plasma) etching process; then SF is introduced6、C4F8、CF4Or Ar etches the insulating medium layer exposed at the edge of the photoresist mask layer; performing cyclic etching on the two steps for a plurality of times to obtain a multistage slope surface nanometer step, wherein the stage number of the step corresponds to the number of the cyclic etching times;
4) locally depositing a band-shaped catalytic metal layer with the thickness of 20-100 nm at one end of the slope nano step through photoetching, thermal evaporation technology or sputtering technology; raising the temperature to be higher than the melting point of the catalytic metal layer, and introducing reducing gas plasma for treatment to convert the catalytic metal layer covering one end of the slope nano step into separated metal nano particles;
5) reducing the temperature below the melting point of the metal nano particles, and depositing and covering an amorphous semiconductor precursor film layer corresponding to the nanowire to be grown on the surface of the whole structure;
6) in the environment protected by vacuum or inert gas, the temperature is raised to be higher than the melting point of the catalytic metal, so that the metal nano particles are re-melted, the amorphous semiconductor precursor film layer is absorbed at the front end of the metal nano particles, and the crystalline nano wires are deposited at the rear end of the metal nano particles; the nano wires grow in parallel by taking the multistage steps on the slope nano steps as guide channels, and a nano wire array growing on the slope nano steps in parallel is obtained;
7) removing the residual amorphous semiconductor precursor film layer by an ICP or RIE etching process;
8) and forming patterns at two ends of the slope nano step by utilizing photoetching or electron beam direct writing, and then depositing a layer of discrete metal electrode with the thickness of 50-200 nm by utilizing a thermal evaporation or sputtering process to form reliable electrical connection to the nanowire.
2. The method of claim 1, wherein the method comprises: in the step 1), the substrate is made of crystalline silicon, glass, aluminum foil, silicon nitride, silicon oxide, silicon carbide, sapphire, polyimide or poly-p-phthalic plastic.
3. The method of claim 1, wherein the method comprises: in the step 1), the thickness of the insulating medium layer is 200-600 nm.
4. The method of claim 1, wherein the method comprises: in the step 1), the insulating dielectric layer is made of silicon oxide.
5. The method of claim 1, wherein the method comprises: in the step 3), the height of each step is within the range of 1-1000 nm, and the circulating etching frequency is 1-10; the distance in the length direction is 2-3 times of the distance in the width direction.
6. The method of claim 1, wherein the method comprises: the catalytic metal is indium.
7. The method of claim 1, wherein the method comprises: the precursor film layer is amorphous silicon (a-Si), amorphous germanium (a-Ge), amorphous carbon (a-C) or other amorphous alloy layers or a heterogeneous laminated structure.
8. The method of claim 1, wherein the method comprises: and on the slope nano-step, the covering thickness of each layer of the precursor thin film layer is 2-500 nm.
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| CN113247860B (en) * | 2020-06-24 | 2022-06-21 | 南京大学 | Preparation method of embedded cross-surface growth three-dimensional nanowire spiral structure |
| CN113428832B (en) * | 2021-06-25 | 2024-02-02 | 杭州电子科技大学温州研究院有限公司 | High-density multi-mode nerve microelectrode array and preparation and integration methods thereof |
| CN113968571B (en) * | 2021-10-21 | 2023-06-06 | 南京大学 | Preparation method of crosstalk-prevention self-limiting superfine closely-spaced crystalline silicon nanowire |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040040683A (en) * | 2002-11-07 | 2004-05-13 | 삼성전자주식회사 | Method of processing exposure for semiconductor device fabrication |
| CN101208776A (en) * | 2005-05-27 | 2008-06-25 | 都柏林伊丽莎白女皇神学院 | Method of forming conducting nanowires |
| CN108217591A (en) * | 2018-01-04 | 2018-06-29 | 南京大学 | A kind of method of heterogeneous alternative stacked step guiding growing three-dimensional slope surface nano-wire array |
| CN108557758A (en) * | 2018-02-08 | 2018-09-21 | 南京大学 | A kind of method of cycle alternation etching homogeneity multistage slope step guiding growth nano-wire array |
| CN108878398A (en) * | 2017-05-16 | 2018-11-23 | 晟碟半导体（上海）有限公司 | Semiconductor devices including conductive bump interconnection |
| CN109496354A (en) * | 2018-10-18 | 2019-03-19 | 长江存储科技有限责任公司 | The method for forming the multi partition hierarchic structure of three-dimensional storage equipment |
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|---|---|---|---|---|
| US9035408B2 (en) * | 2013-05-06 | 2015-05-19 | The United States Of America, As Represented By The Secretary Of The Navy | Nanometer-scale level structures and fabrication method for digital etching of nanometer-scale level structures |
-
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040040683A (en) * | 2002-11-07 | 2004-05-13 | 삼성전자주식회사 | Method of processing exposure for semiconductor device fabrication |
| CN101208776A (en) * | 2005-05-27 | 2008-06-25 | 都柏林伊丽莎白女皇神学院 | Method of forming conducting nanowires |
| CN108878398A (en) * | 2017-05-16 | 2018-11-23 | 晟碟半导体（上海）有限公司 | Semiconductor devices including conductive bump interconnection |
| CN108217591A (en) * | 2018-01-04 | 2018-06-29 | 南京大学 | A kind of method of heterogeneous alternative stacked step guiding growing three-dimensional slope surface nano-wire array |
| CN108557758A (en) * | 2018-02-08 | 2018-09-21 | 南京大学 | A kind of method of cycle alternation etching homogeneity multistage slope step guiding growth nano-wire array |
| CN109496354A (en) * | 2018-10-18 | 2019-03-19 | 长江存储科技有限责任公司 | The method for forming the multi partition hierarchic structure of three-dimensional storage equipment |
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