CN109920359B

CN109920359B - Display panel, display panel driving method and display device

Info

Publication number: CN109920359B
Application number: CN201910247762.4A
Authority: CN
Inventors: 李玥; 高娅娜; 周星耀
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2019-03-29
Filing date: 2019-03-29
Publication date: 2022-06-10
Anticipated expiration: 2039-03-29
Also published as: CN109920359A

Abstract

The invention provides a display panel, a display panel driving method and a display device. The display panel includes: the display area comprises a first display area, a second display area and a third display area, wherein the second display area is positioned between the first display area and the third display area, the edge of the second display area comprises a concave edge section, and the concave direction of the concave edge section faces to the second display area; the display device comprises a plurality of pixels, a first display area and a second display area, wherein the plurality of pixels are arranged in an array manner, the first display area comprises a first pixel row, the second display area comprises a second pixel row, the third display area comprises a third pixel row, and the number of pixels in the second pixel row is respectively smaller than that of the pixels in the first pixel row and that of the pixels in the third pixel row; the display device comprises a first pixel column and a second pixel column, wherein the number of pixels in the first pixel column is smaller than that of pixels in the second pixel column, the second pixel column comprises a common data line positioned in a second display area, and the first pixel column and the second pixel column share the common data line. The display panel achieves narrow frame.

Description

Display panel, display panel driving method and display device

[ technical field ] A method for producing a semiconductor device

The present invention relates to the field of display technologies, and in particular, to a display panel, a display panel driving method, and a display device.

[ background of the invention ]

With the development of display technology, the fully-screened special-shaped display panel has a large screen ratio and an ultra-narrow frame, so that the visual effect of a viewer can be greatly improved, and the display panel is widely concerned.

Fig. 1 is a schematic structural diagram of a special-shaped display panel in the prior art.

As shown in fig. 1, in the prior art, the irregular display panel 100 includes two first data lines 110, a first connection line 120, and a concave edge section 130, the two first data lines 110 are respectively located at the upper side and the lower side of the concave edge section 130, the first connection line 120 is located at the adjacent side of the concave edge section 130, and the two first data lines 110 are electrically connected through the first connection line 120. However, the first connection line 120 occupies a space.

[ summary of the invention ]

In order to solve the above technical problems, the present invention provides a display panel, a display panel driving method, and a display device.

In one aspect, the present invention provides a display panel comprising:

the display area comprises a first display area, a second display area and a third display area, wherein the second display area is positioned between the first display area and the third display area, the edge of the second display area comprises a concave edge section, and the concave direction of the concave edge section faces to the second display area;

the pixels are arranged in an array, the first display area comprises a first pixel row, the second display area comprises a second pixel row, the third display area comprises a third pixel row, and the number of the pixels in the second pixel row is smaller than that of the pixels in the first pixel row and the third pixel row respectively;

the display device comprises a first pixel column and a second pixel column, wherein the number of pixels in the first pixel column is smaller than that of pixels in the second pixel column, the second pixel column comprises a common data line located in the second display area, and the first pixel column and the second pixel column share the common data line.

Optionally, the non-display area comprises a first sub non-display area, the first sub non-display area being adjacent to the recessed edge segment;

a plurality of first switching units, the first pixel column including a first data line including a first sub first data line and a second sub first data line, the first sub first data line and the second sub first data line being coupled to the same common data line through different first switching units, respectively, wherein the first sub first data line is located in the first display area, the second sub first data line is located in the third display area, and the first sub non-display area is located between the first sub first data line and the second sub first data line;

a plurality of second switching units, wherein the second pixel column includes a second data line, the second data line includes a first sub-second data line, a second sub-second data line, and the common data line, and the first sub-second data line and the second sub-second data line are respectively coupled to the common data line through different second switching units, wherein the first sub-second data line is located in the first display area, and the second sub-second data line is located in the third display area;

the first switching unit and the second switching unit are different in opening state.

Optionally, the first switching unit is a first switching transistor, the second switching unit is a second switching transistor, and the first switching transistor and the second switching transistor are different in type;

the display panel further comprises a first control line and a second control line, wherein a control electrode of the first switch transistor is electrically connected with the first control line, and a control electrode of the second switch transistor is electrically connected with the second control line.

Optionally, the control electrode of each first switching transistor in the first display area is electrically connected to the same first control line, and the control electrode of each first switching transistor in the third display area is electrically connected to the same first control line;

and the control electrode of each second switch transistor in the first display area is electrically connected with the same second control line, and the control electrode of each second switch transistor in the third display area is electrically connected with the same second control line.

Optionally, the control electrode of each first switching transistor is electrically connected with the same first control line;

and the control electrode of each second switch transistor is electrically connected with the same second control line.

Optionally, the display panel further includes a first sub-connection line and a second sub-connection line;

the first sub first data line is electrically connected with the first switching unit through the first sub connecting line, and the second sub first data line is electrically connected with the first switching unit through the second sub connecting line;

the sum of the resistances of the first sub-first data line, the first sub-connection line, the second sub-first data line, the second sub-connection line, and the common data line is equal to a first resistance, the sum of the resistances of the first sub-second data line, the second sub-second data line, and the common data line is equal to a second resistance, and a ratio of the first resistance to the second resistance is equal to or greater than 0.99 and equal to or less than 1.01.

the cross-sectional area of the first sub second data line is smaller than that of the first sub first data line.

Optionally, the display panel further comprises a first sub-connection line;

the first sub first data line is electrically connected with the first switching unit through the first sub connecting line;

the cross-sectional area of the first sub-connecting line is greater than that of the first sub-first data line.

Optionally, the display panel further includes a first sub-connection line, a second sub-connection line, and a first compensation resistor;

the first compensation resistor is electrically connected with the first sub second data line and the second switching unit;

the sum of the resistances of the first sub-first data line, the first sub-connection line, the second sub-first data line, the second sub-connection line, and the common data line is equal to a third resistance, the sum of the resistances of the first sub-second data line, the first compensation resistance, the second sub-second data line, and the common data line is equal to a fourth resistance, and a ratio of the third resistance to the fourth resistance is equal to or greater than 0.99 and equal to or less than 1.01.

the first compensation resistor is connected in parallel with the first sub-connecting line.

In another aspect, the present invention provides a display panel driving method;

the display panel comprises a display area and a non-display area, wherein the display area comprises a first display area, a second display area and a third display area, the second display area is positioned between the first display area and the third display area, the edge of the second display area comprises a concave edge section, and the concave direction of the concave edge section faces to the second display area;

the pixels are arranged in an array, the first display area comprises a first pixel row, the second display area comprises a second pixel row, the third display area comprises a third pixel row, and the number of the pixels in the second pixel row is respectively smaller than that of the pixels in the first pixel row and that of the pixels in the third pixel row;

a first pixel column and a second pixel column, the number of pixels in the first pixel column being less than the number of pixels in the second pixel column, the second pixel column including a common data line in the second display region, the first pixel column and the second pixel column sharing the common data line;

the display panel further includes: a plurality of first scan lines located within the first display area, a plurality of second scan lines located within the second display area, and a plurality of third scan lines located within the third display area;

the method comprises the following steps: executing a first data writing stage, executing a second data writing stage and executing a third data writing stage;

in the first data writing stage, scanning signals are transmitted line by line through a plurality of third scanning lines;

in the second data writing phase, scanning signals are transmitted line by line through a plurality of second scanning lines;

in the third data writing phase, scanning signals are transmitted line by line through a plurality of first scanning lines.

Optionally, the non-display area comprises a first sub non-display area, the first sub non-display area is adjacent to the recessed edge segment;

Optionally, in the first data writing phase, an on signal is transmitted through the first control line, and an off signal is transmitted through the second control line;

turning on the first switching transistor and turning off the second switching transistor;

transmitting a data signal through the second sub first data line and the second sub second data line.

Optionally, in the first data writing phase, an on signal is transmitted through the second control line, and an off signal is transmitted through the first control line;

turning on the second switching transistor and turning off the first switching transistor;

Optionally, in the second data writing phase, transmitting a turn-on signal through the second control line and transmitting a turn-off signal through the first control line;

transmitting a data signal through the second sub-second data line and the common data line.

Optionally, in the third data writing phase, transmitting a turn-on signal through the first control line and transmitting a turn-off signal through the second control line;

and transmitting data signals through the first data line and the common data line.

Optionally, in the third data writing phase, transmitting a turn-on signal through the second control line and transmitting a turn-off signal through the first control line;

and transmitting a data signal through the second data line.

In still another aspect, the present invention provides a display device including the display panel.

In the invention, the data lines of the second pixel column extend in the first display area, the second display area and the third display area, the data lines of the second pixel column in the first display area and the third display area are electrically connected through the data lines of the second pixel column in the second display area, and the second pixel column transmits data signals in the first display area, the second display area and the third display area; the data lines of the first pixel columns extend in the first display region and the third display region and are interrupted at the recessed edge sections, the data lines of the first pixel columns in the first display region and the third display region are electrically connected through the data lines of the second pixel columns in the second display region, and the first pixel columns transmit data signals in the first display region and the third display region. The first pixel column and the second pixel column share a data line of the second pixel column in the second display area, that is, a common data line. The data lines of the first pixel columns in the first display area and the third display area are not electrically connected through the lead wires close to the concave edge section in the non-display area, the lead wire area close to the concave edge section in the non-display area is reduced, and the display panel achieves narrow frame.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a prior art display panel with a special shape;

FIG. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 3 is a schematic view of another structure of a display panel according to an embodiment of the present invention;

FIG. 4 is a schematic view of another structure of a display panel according to an embodiment of the present invention;

FIG. 5 is a schematic view of another structure of a display panel according to an embodiment of the present invention;

FIG. 6 is a schematic view of another structure of a display panel according to an embodiment of the present invention;

FIG. 7 is a schematic view of another structure of a display panel according to an embodiment of the present invention;

FIG. 8 is a schematic view of another structure of a display panel according to an embodiment of the present invention;

FIG. 9 is a flowchart illustrating a method for driving a display panel according to an embodiment of the present invention;

FIG. 10 is a timing diagram illustrating a driving method of a display panel according to an embodiment of the present invention;

FIG. 11 is another timing diagram illustrating a driving method of a display panel according to an embodiment of the present invention;

FIG. 12 is another timing diagram illustrating a driving method of a display panel according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of a display device in an embodiment of the invention.

[ detailed description ] embodiments

For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It should be understood that although the terms first, second, etc. may be used herein to describe devices in accordance with embodiments of the present invention, these devices should not be limited by these terms. These terms are only used to distinguish one device from another. For example, a first device may also be referred to as a second device, and similarly, a second device may also be referred to as a first device, without departing from the scope of embodiments of the present invention.

Fig. 2 is a schematic structural diagram of a display panel in an embodiment of the invention.

As shown in fig. 2, the display panel 200 includes: the display area AA comprises a first display area AA1, a second display area AA2 and a third display area AA3, wherein the second display area AA2 is positioned between the first display area AA1 and the third display area AA3, the edge of the second display area AA2 comprises a concave edge section NB, and the concave direction of the concave edge section NB faces to the second display area AA 2; a plurality of pixels PX arranged in an array, the first display area AA1 including a first pixel row PXC1, the second display area AA2 including a second pixel row PXC2, the third display area AA3 including a third pixel row PXC3, the number of pixels in the second pixel row PXC2 being smaller than the number of pixels in the first pixel row PXC1 and the third pixel row PXC3, respectively; a first pixel column PXR1 (two columns are schematically drawn in the figure) and a second pixel column PXR2 (two columns are schematically drawn in the figure), the number of pixels in the first pixel column PXR1 is smaller than the number of pixels in the second pixel column PXR2, the second pixel column PXR2 includes a common data line DL0 located in the second display area AA2, and the first pixel column PXR1 and the second pixel column PXR2 share the common data line DL 0.

In the embodiment of the present invention, the concave direction of the concave edge section NB faces to the second display area AA2, the second display area AA2 is located between the first display area AA1 and the third display area AA3, and the concave edge section NB is located between the first display area AA1 and the third display area AA 3. The first, second and third display areas AA1, AA2, AA3 have an array of pixels PX, and optionally, the area surrounded by the recessed edge segment NB is free of any pixels PX. The number of pixels in the second pixel row PXC2 is smaller than the number of pixels in the first pixel row PXC1 and smaller than the number of pixels in the third pixel row PXC 3. Optionally, the number of pixels in the first pixel row PXC1 is equal to the number of pixels in the third pixel row PXC 3. The number of pixels in the first pixel column PXR1 is smaller than the number of pixels in the second pixel column PXR2, the first pixel column PXR1 extends within the first display area AA1 and the third display area AA3 and is interrupted at the recessed edge section NB, and the second pixel column PXR2 extends within the first display area AA1, the second display area AA2, and the third display area AA 3.

As shown in fig. 2, optionally, the display panel 200 further includes a driving chip IC located in the frame area, the driving chip IC is close to the third display area AA3 and far away from the first display area AA1, the driving chip IC is electrically connected to the data lines of the third display area AA3, and the driving chip IC transmits data signals to the data lines of the third display area AA 3. It should be noted that, in the embodiment of the present application, a COF (Chip On Flex, or, Chip On Film, commonly called a Chip On Film) may also be adopted, that is, the driving IC is fixed On a Flexible Printed Circuit (FPC), and then electrically connected to the data line of the third display area AA3 through the FPC, and transmits a data signal to the data line of the third display area AA 3.

In the embodiment of the present invention, the data lines of the second pixel column PXR2 extend in the first display area AA1, the second display area AA2 and the third display area AA3, the data lines of the second pixel column PXR2 in the first display area AA1 and the third display area AA3 are electrically connected through the data lines of the second pixel column PXR2 in the second display area AA2, and the second pixel column PXR2 transmits data signals in the first display area AA1, the second display area AA2 and the third display area AA 3; the data lines of the first pixel column PXR1 extend within the first and third display areas AA1 and AA3 and are interrupted at the recessed edge segment NB, the data lines of the first pixel column PXR1 within the first and third display areas AA1 and AA3 are electrically connected through the data lines of the second pixel column PXR2 within the second display area AA2, and the first pixel column PXR1 transmits data signals within the first and third display areas AA1 and AA 3. The first pixel column PXR1 and the second pixel column PXR2 share the data line of the second pixel column PXR2 in the second display area AA2, that is, the common data line DL 0. The data lines of the first pixel column PXR1 in the first display area AA1 and the third display area AA3 are not electrically connected through the lead line near the recessed edge segment NB in the non-display area NA, the lead line area near the recessed edge segment NB in the non-display area NA can be reduced, and the display panel 200 can achieve a narrow bezel.

As shown in fig. 2, the non-display area NA includes a first sub non-display area NA1, the first sub non-display area NA1 is adjacent to the recessed edge segment NB; a plurality of first switching units SW1, the first pixel column PXR1 includes a first data line DL10, the first data line DL10 includes a first sub-first data line DL11 and a second sub-first data line DL12, the first sub-first data line DL11 and the second sub-first data line DL12 are coupled to the same common data line DL0 through different first switching units SW1, respectively, wherein the first sub-first data line DL11 is located in a first display area AA1, the second sub-first data line DL12 is located in a third display area AA3, and the first sub-non-display area NA1 is located between the first sub-first data line DL11 and the second sub-first data line DL 12; a plurality of second switching units SW2, the second pixel column PXR2 includes a second data line DL20, the second data line DL20 includes a first sub-second data line DL21, a second sub-second data line DL22 and a common data line DL0, the first sub-second data line DL21 and the second sub-second data line DL22 are respectively coupled to the common data line DL0 through different second switching units SW2, wherein the first sub-second data line DL21 is located in the first display area AA1, and the second sub-second data line DL22 is located in the third display area AA 3; the on states of the first and second switching units SW1 and SW2 are different.

In the embodiment of the present invention, the first switching unit SW1 is turned on, the first sub-first data line DL11 is electrically connected to the common data line DL0, the second sub-first data line DL12 is electrically connected to the common data line DL0, and the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 transmit data signals; the first switching unit SW1 is turned off, the first sub-first data line DL11 is not electrically connected to the common data line DL0, the second sub-first data line DL12 is not electrically connected to the common data line DL0, the first sub-first data line DL11 does not transmit data signals, and the second sub-first data line DL12 transmits data signals. The second switching unit SW2 is turned on, the first sub-second data line DL21 is electrically connected to the common data line DL0, the second sub-second data line DL22 is electrically connected to the common data line DL0, and the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL22 transmit data signals; the second switching unit SW2 is turned off, the first sub-second data line DL21 is not electrically connected to the common data line DL0, the second sub-second data line DL22 is not electrically connected to the common data line DL0, the first sub-second data line DL21 does not transmit data signals, and the second sub-second data line DL22 transmits data signals. When the first switching unit SW1 is turned on, the second switching unit SW2 is turned off; when the first switching unit SW1 is turned off, the second switching unit SW2 is turned on. The first sub-first data line DL11 and the second sub-first data line DL12 are not electrically connected through the lead of the first sub-non-display area NA1, the lead area of the first sub-non-display area NA1 is reduced, and the display panel 200 can achieve a narrow frame.

As shown in fig. 2, it is preferable that the left first data line DL10 corresponds to and is electrically connected to the left first common data line DL0, the left second data line DL10 corresponds to and is electrically connected to the left second common data line DL0, the left nth first data line DL10 corresponds to and is electrically connected to the left nth common data line DL0, and N is a natural number.

Alternatively, as shown in fig. 2, the plurality of first switching units SW1 and the plurality of second switching units SW2 are located in the first display area AA1 and adjacent to the second display area AA 2; meanwhile, the other first switching unit SW1 and the other second switching unit SW2 are located within the third display area AA3 and are adjacent to the second display area AA 2.

Fig. 3 is another schematic structural diagram of the display panel according to the embodiment of the invention.

As shown in fig. 3, the first switching unit SW1 is a first switching transistor ST1, the second switching unit SW2 is a second switching transistor ST2, and the first switching transistor ST1 and the second switching transistor ST2 are different in type; the display panel 200 further includes a first control line GL1 and a second control line GL2, wherein a control electrode of the first switching transistor ST1 is electrically connected to the first control line GL1, and a control electrode of the second switching transistor ST2 is electrically connected to the second control line GL 2.

In the embodiment of the present invention, the first control line GL1 transmits a turn-on signal, and the first switching transistor ST1 is turned on; the first control line GL1 transmits a turn-off signal, the first switching transistor ST1 is turned off; the second control line GL2 transmits a turn-on signal, and the second switching transistor ST2 is turned on; the second control line GL2 transmits an off signal, and the second switching transistor ST2 is turned off. When the first control line GL1 transmits an on signal, the second control line GL2 transmits an off signal; when the first control line GL1 transmits an off signal, the second control line GL2 transmits an on signal. When the first switching transistor ST1 is turned on, the second switching transistor ST2 is turned off; when the first switching transistor ST1 is turned off, the second switching transistor ST2 is turned on.

As shown in fig. 3, the control electrode of each first switching transistor ST1 in the first display area AA1 is electrically connected to the same first control line GL1, and the control electrode of each first switching transistor ST1 in the third display area AA3 is electrically connected to the same first control line GL 1; a control electrode of each of the second switching transistors ST2 in the first display area AA1 is electrically connected to the same second control line GL2, and a control electrode of each of the second switching transistors ST2 in the third display area AA3 is electrically connected to the same second control line GL 2.

In the embodiment of the present invention, the first control line GL1 is electrically connected to the control electrode of the first switching transistor ST1 of the first display area AA1, and the second first control line GL1 is electrically connected to the control electrode of the first switching transistor ST1 of the third display area AA 3; the first control line GL1 transmits a turn-on signal and the second first control line GL1 transmits a turn-on signal, the first switching transistor ST1 of the first display area AA1 is turned on and the first switching transistor ST1 of the third display area AA3 is turned on; the first sub first data line DL11 is electrically connected with the common data line DL0 and the second sub first data line DL12 is electrically connected with the common data line DL 0; the first sub first data line DL11, the common data line DL0, and the second sub first data line DL12 transmit data signals; the first control line GL1 transmits an off signal and the second first control line GL1 transmits an on signal, the first switching transistor ST1 of the first display area AA1 is turned off and the first switching transistor ST1 of the third display area AA3 is turned on; the first sub first data line DL11 is not electrically connected to the common data line DL0 and the second sub first data line DL12 is electrically connected to the common data line DL 0; the second sub first data line DL12, the common data line DL0 transmit data signals and the first sub first data line DL11 does not transmit data signals.

In the embodiment of the present invention, the first second control line GL2 is electrically connected to the control electrode of the second switching transistor ST2 of the first display area AA1, and the second control line GL2 is electrically connected to the control electrode of the second switching transistor ST2 of the third display area AA 3; the first second control line GL2 transmits a turn-on signal and the second control line GL2 transmits a turn-on signal, the second switching transistor ST2 of the first display area AA1 is turned on and the second switching transistor ST2 of the third display area AA3 is turned on; the first sub second data line DL21 is electrically connected to the common data line DL0 and the second sub second data line DL22 is electrically connected to the common data line DL 0; the first sub second data line DL21, the common data line DL0, and the second sub second data line DL22 transmit data signals; the first second control line GL2 transmits an off signal and the second control line GL2 transmits an on signal, the second switching transistor ST2 of the first display area AA1 is turned off and the second switching transistor ST2 of the third display area AA3 is turned on; the first sub-second data line DL21 is not electrically connected to the common data line DL0 and the second sub-second data line DL22 is electrically connected to the common data line DL 0; the second sub-second data line DL22, the common data line DL0 transmit data signals and the first sub-second data line DL21 does not transmit data signals.

In the embodiment of the present invention, the first switching transistor ST1 of the first display area AA1 and the first switching transistor ST1 of the third display area AA3 are electrically connected to different first control lines GL1, are controlled separately, and may have different switching states; the second switching transistor ST2 of the first display area AA1 and the second switching transistor ST2 of the third display area AA3 are electrically connected to different second control lines GL2, and are controlled separately, and may have different switching states.

Fig. 4 is another structural schematic diagram of the display panel in the embodiment of the invention.

As shown in fig. 4, the control electrode of each of the first switching transistors ST1 is electrically connected to the same first control line GL 1; a control electrode of each of the second switching transistors ST2 is electrically connected to the same second control line GL 2.

In the embodiment of the present invention, the same first control line GL1 is electrically connected to the control electrodes of the first switching transistor ST1 of the first display area AA1 and the third display area AA 3; the first control line GL1 transmits a turn-on signal, and the first switching transistor ST1 of the first display area AA1 and the third display area AA3 are turned on; the first sub first data line DL11 is electrically connected with the common data line DL0 and the second sub first data line DL12 is electrically connected with the common data line DL 0; the first sub first data line DL11, the common data line DL0, and the second sub first data line DL12 transmit data signals; the first control line GL1 transmits a turn-off signal, and the first switching transistor ST1 of the first display area AA1 and the third display area AA3 are turned off; the first sub-first data line DL11 is not electrically connected to the common data line DL0 and the second sub-first data line DL12 is not electrically connected to the common data line DL 0; the first sub first data line DL11 transmits no data signal and the second sub first data line DL12 transmits a data signal.

In the embodiment of the present invention, the same second control line GL2 is electrically connected to the control electrodes of the second switching transistor ST2 of the first display area AA1 and the third display area AA 3; the second control line GL2 transmits a turn-on signal, and the second switching transistor ST2 of the first display area AA1 and the third display area AA3 are turned on; the first sub second data line DL21 is electrically connected to the common data line DL0 and the second sub second data line DL22 is electrically connected to the common data line DL 0; the first sub second data line DL21, the common data line DL0, and the second sub second data line DL22 transmit data signals; the second control line GL2 transmits a turn-off signal, and the second switching transistors ST2 of the first and third display areas AA1 and AA3 are turned off; the first sub second data line DL21 is not electrically connected to the common data line DL0 and the second sub second data line DL22 is not electrically connected to the common data line DL 0; the first sub-second data line DL21 transmits no data signal and the second sub-second data line DL22 transmits a data signal.

In the embodiment of the present invention, the first switching transistor ST1 of the first display area AA1 and the first switching transistor ST1 of the third display area AA3 are electrically connected to the same first control line GL1, so that a different first control line GL1 is not provided, so as to simplify the wiring of the first control line GL 1; the second switching transistor ST2 of the first display area AA1 and the second switching transistor ST2 of the third display area AA3 are electrically connected to the same second control line GL2, so that a different second control line GL2 is not provided, in order to simplify the wiring of the second control line GL 2.

As shown in fig. 2, the display panel 200 further includes a first sub-connection line CL1, a second sub-connection line CL 2; the first sub-first data line DL11 and the first switching unit SW1 are electrically connected through a first sub-connecting line CL1, and the second sub-first data line DL12 and the first switching unit SW1 are electrically connected through a second sub-connecting line CL 2; the sum of the resistances of the first sub-first data line DL11, the first sub-link line CL1, the second sub-first data line DL12, the second sub-link line CL2, and the common data line DL0 is equal to a first resistance, the sum of the resistances of the first sub-second data line DL21, the second sub-second data line DL22, and the common data line DL0 is equal to a second resistance, and a ratio of the first resistance to the second resistance is 0.99 or more and 1.01 or less.

In the embodiment of the invention, the first switching unit SW1 is turned on, the first sub-first data line DL11 is electrically connected to the common data line DL0 through the first sub-connecting line CL1, and the second sub-first data line DL12 is electrically connected to the common data line DL0 through the second sub-connecting line CL 2; the first sub-first data line DL11, the first sub-link line CL1, the common data line DL0, the second sub-link line CL2 and the second sub-first data line DL12 sequentially transmit data signals. The second switching unit SW2 is turned on, the first sub-second data line DL21 is electrically connected to the common data line DL0, and the second sub-second data line DL22 is electrically connected to the common data line DL 0; the first sub-second data line DL21, the common data line DL0, and the second sub-second data line DL22 sequentially transmit data signals. The sum of the resistances of the first sub-first data line DL11, the first sub-link line CL1, the common data line DL0, the second sub-link line CL2 and the second sub-first data line DL12 is equal to or approximately equal to the sum of the resistances of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL 22; the load of the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 is equal to or approximately equal to the load of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL 22; the voltage of the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 is equal to or approximately equal to the voltage of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL 22; the data signals of the pixels PX in the first sub-first data line DL11, the common data line DL0, and the second sub-first data line DL12 are equal to or approximately equal to the data signals of the pixels PX in the first sub-second data line DL21, the common data line DL0, and the second sub-second data line DL22, so that the display brightness of the display panel 200 is uniform, and the split screen phenomenon is avoided.

As shown in fig. 2, the display panel 200 further includes a first sub-connection line CL1, a second sub-connection line CL 2; the first sub-first data line DL11 and the first switching unit SW1 are electrically connected through a first sub-connecting line CL1, and the second sub-first data line DL12 and the first switching unit SW1 are electrically connected through a second sub-connecting line CL 2; the cross-sectional area of the first sub-second data line DL21 is smaller than that of the first sub-first data line DL 11.

In the embodiment of the present invention, the cross-sectional area of the first sub-second data line DL21 is smaller than that of the first sub-first data line DL11, and the resistance of the first sub-second data line DL21 is greater than that of the first sub-first data line DL 11; the difference between the resistances of the first and second sub-second data lines DL21 and DL11 is equal to or approximately equal to the sum of the resistances of the first and second sub-link lines CL1 and CL 2; the sum of the resistances of the first sub-first data line DL11, the first sub-link line CL1, and the second sub-link line CL2 is equal to or approximately equal to the resistance of the first sub-second data line DL 21; the sum of the resistances of the first sub-first data line DL11, the first sub-link line CL1, the common data line DL0, the second sub-link line CL2 and the second sub-first data line DL12 is equal to or approximately equal to the sum of the resistances of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL 22; the load of the first sub-first data line DL11, the common data line DL0, the second sub-first data line DL12 is equal to or approximately equal to the load of the first sub-second data line DL21, the common data line DL0, the second sub-second data line DL 22; the voltage of the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 is equal to or approximately equal to the voltage of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL 22; the data signals of the pixels PX in the first sub-first data line DL11, the common data line DL0, and the second sub-first data line DL12 are equal to or approximately equal to the data signals of the pixels PX in the first sub-second data line DL21, the common data line DL0, and the second sub-second data line DL22, so that the display brightness of the display panel 200 is uniform, and the split screen phenomenon is avoided.

As shown in fig. 2, the display panel 200 further includes a first sub-connection line CL1, a second sub-connection line CL 2; the first sub-first data line DL11 and the first switching unit SW1 are electrically connected by a first sub-connecting line CL1, and the second sub-first data line DL12 and the first switching unit SW1 are electrically connected by a second sub-connecting line CL 2; the cross-sectional area of the first sub-second data line DL21 is smaller than that of the first sub-first data line DL11, and the cross-sectional area of the second sub-second data line DL22 is smaller than that of the second sub-first data line DL 12.

In the embodiment of the present invention, the cross-sectional area of the first sub-second data line DL21 is smaller than that of the first sub-first data line DL11, and the resistance of the first sub-second data line DL21 is greater than that of the first sub-first data line DL 11; the cross-sectional area of the second sub-second data line DL22 is less than that of the second sub-first data line DL12, and the resistance of the second sub-second data line DL22 is greater than that of the second sub-first data line DL 12; the difference between the resistances of the first and second sub-second data lines DL21 and DL11 is equal to or approximately equal to the resistance of the first sub-link line CL1, and the difference between the resistances of the second and first sub-second data lines DL22 and DL12 is equal to or approximately equal to the resistance of the second sub-link line CL 2; the sum of the resistances of the first sub-first data line DL11 and the first sub-link line CL1 is equal to or approximately equal to the resistance of the first sub-second data line DL21, and the sum of the resistances of the second sub-first data line DL12 and the second sub-link line CL2 is equal to or approximately equal to the resistance of the second sub-second data line DL 22; the sum of the resistances of the first sub-first data line DL11, the first sub-link line CL1, the common data line DL0, the second sub-link line CL2 and the second sub-first data line DL12 is equal to or approximately equal to the sum of the resistances of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL 22; the load of the first sub-first data line DL11, the common data line DL0, the second sub-first data line DL12 is equal to or approximately equal to the load of the first sub-second data line DL21, the common data line DL0, the second sub-second data line DL 22; the voltage of the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 is equal to or approximately equal to the voltage of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL 22; the data signals of the pixels PX in the first sub-first data line DL11, the common data line DL0, and the second sub-first data line DL12 are equal to or approximately equal to the data signals of the pixels PX in the first sub-second data line DL21, the common data line DL0, and the second sub-second data line DL22, so that the display brightness of the display panel 200 is uniform, and the split screen phenomenon is avoided.

As shown in fig. 2, the display panel 200 further includes a first sub-connection line CL 1; the first sub-first data line DL11 and the first switching unit SW1 are electrically connected through the first sub-connecting line CL 1; the cross-sectional area of the first sub-connecting line CL1 is greater than that of the first sub-first data line DL 11.

In the embodiment of the present invention, the cross-sectional area of the first sub-connecting line CL1 is greater than the cross-sectional area of the first sub-first data line DL11, and the resistivity of the first sub-connecting line CL1 is less than the resistivity of the first sub-first data line DL 11; the difference between the sum of the resistances of the first sub-connecting line CL1 and the first sub-first data line DL11 and the resistance of the first sub-second data line DL21 is reduced; the difference between the load of the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 and the load of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL22 is reduced; the difference between the voltage of the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 and the voltage of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL22 is reduced; the difference between the data signals of the pixels PX in the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 and the data signals of the pixels PX in the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL22 is reduced, the difference of the display luminance of the display panel 200 is reduced, and thus the split screen phenomenon is alleviated; the first sub-link line CL1 is far from the driving chip IC instead of being located between the common data line DL0 and the second sub-first data line DL12, and the first sub-link line CL1 does not affect the data signals of the pixels PX of the one way of the common data line DL0 and the one way of the second sub-first data line DL12 and does not affect the display of the second display area AA2 and the third display area AA 3.

As shown in fig. 2, the display panel 200 further includes a first sub-connection line CL 1; the first sub-first data line DL11 and the first switching unit SW1 are electrically connected through the first sub-connecting line CL 1; the cross-sectional area of the first sub-first data line DL11 is greater than that of the first sub-connecting line CL 1.

In the embodiment of the present invention, the cross-sectional area of the first sub-first data line DL11 is greater than that of the first sub-connecting line CL1, and the resistivity of the first sub-first data line DL11 is less than that of the first sub-connecting line CL; the difference between the sum of the resistances of the first sub-first data line DL11 and the first sub-connecting line CL1 and the resistance of the first sub-second data line DL21 is reduced; the difference between the load of the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 and the load of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL22 is reduced; the difference between the voltage of the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 and the voltage of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL22 is reduced; the difference between the data signal of the pixel PX in the first sub-first data line DL11, the common data line DL0, and the second sub-first data line DL12 and the data signal of the pixel PX in the first sub-second data line DL21, the common data line DL0, and the second sub-second data line DL22 is reduced, and the difference in the display luminance of the display panel 200 is reduced, which alleviates the split screen phenomenon.

Fig. 5 is another structural schematic diagram of the display panel in the embodiment of the invention.

As shown in fig. 5, the display panel 200 further includes a first sub-connection line CL1, a second sub-connection line CL2, and a first compensation resistor CR 1; the first sub-first data line DL11 and the first switching unit SW1 are electrically connected by a first sub-connecting line CL1, and the second sub-first data line DL12 and the first switching unit SW1 are electrically connected by a second sub-connecting line CL 2; the first compensation resistor CR1 is electrically connected to the first sub-second data line DL21 and to the second switching unit SW 2; the sum of the resistances of the first sub-first data line DL11, the first sub-link line CL1, the second sub-first data line DL12, the second sub-link line CL2, and the common data line DL0 is equal to a third resistance, the sum of the resistances of the first sub-second data line DL21, the first compensation resistance CR1, the second sub-second data line DL22, and the common data line DL0 is equal to a fourth resistance, and a ratio of the third resistance to the fourth resistance is 0.99 or more and 1.01 or less.

In the embodiment of the present invention, the first compensation resistor CR1 is electrically connected to the first sub-second data line DL21 and to the second switching unit SW 2; the first sub-second data line DL21, the first compensation resistor CR1, the common data line DL0 and the second sub-second data line DL22 are connected in series; the first sub-first data line DL11, the first sub-link line CL1, the common data line DL0, the second sub-link line CL2 and the second sub-first data line DL12 are connected in series; the resistance of the first compensation resistor CR1 is equal to or approximately equal to the sum of the resistances of the first sub-connection line CL1 and the second sub-connection line CL 2; the sum of the resistances of the first sub-first data line DL11, the first sub-link line CL1, the common data line DL0, the second sub-link line CL2 and the second sub-first data line DL12 is equal to or approximately equal to the sum of the resistances of the first sub-second data line DL21, the first compensation resistance CR1, the common data line DL0 and the second sub-second data line DL 22; the load of the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 is equal to or approximately equal to the load of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL 22; the voltage of the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 is equal to or approximately equal to the voltage of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL 22; the data signals of the pixels PX in the first sub-first data line DL11, the common data line DL0, and the second sub-first data line DL12 are equal to or approximately equal to the data signals of the pixels PX in the first sub-second data line DL21, the common data line DL0, and the second sub-second data line DL22, so that the display brightness of the display panel 200 is uniform, and the split screen phenomenon is avoided.

Fig. 6 is another schematic structural diagram of the display panel according to the embodiment of the invention.

As shown in fig. 6, the display panel 200 further includes a first sub-connection line CL1, a second sub-connection line CL2, a first compensation resistor CR1, and a second compensation resistor CR 2; the first sub-first data line DL11 and the first switching unit SW1 are electrically connected through a first sub-connecting line CL1, and the second sub-first data line DL12 and the first switching unit SW1 are electrically connected through a second sub-connecting line CL 2; the first compensation resistor CR1 is electrically connected to the first sub-second data line DL21 and to the second switching unit SW2, and the second compensation resistor CR2 is electrically connected to the second sub-second data line DL22 and to the second switching unit SW 2; the sum of the resistances of the first sub-first data line DL11, the first sub-connection line CL1, the second sub-first data line DL12, the second sub-connection line CL2, and the common data line DL0 is equal to a third resistance, the sum of the resistances of the first sub-second data line DL21, the first compensation resistance CR1, the second sub-second data line DL22, the second compensation resistance CR2, and the common data line DL0 is equal to a fourth resistance, and a ratio of the third resistance to the fourth resistance is equal to or greater than 0.99 and equal to or less than 1.01.

In the embodiment of the present invention, the first compensation resistor CR1 is electrically connected to the first sub-second data line DL21 and to the second switching unit SW2, and the second compensation resistor CR2 is electrically connected to the second sub-second data line DL22 and to the second switching unit SW 2; the first sub-second data line DL21, the first compensation resistor CR1, the common data line DL0, the second compensation resistor CR2 and the second sub-second data line DL22 are connected in series; the first sub-first data line DL11, the first sub-link line CL1, the common data line DL0, the second sub-link line CL2 and the second sub-first data line DL12 are connected in series; the resistance of the first compensation resistor CR1 is equal to or approximately equal to the resistance of the first sub-connection line CL1, and the resistance of the second compensation resistor CR2 is equal to or approximately equal to the resistance of the second sub-connection line CL 2; the sum of the resistances of the first sub-first data line DL11, the first sub-link line CL1, the common data line DL0, the second sub-link line CL2 and the second sub-first data line DL12 is equal to or approximately equal to the sum of the resistances of the first sub-second data line DL21, the first compensation resistor CR1, the common data line DL0, the second compensation resistor CR2 and the second sub-second data line DL 22; the load of the first sub-first data line DL11, the common data line DL0, the second sub-first data line DL12 is equal to or approximately equal to the load of the first sub-second data line DL21, the common data line DL0, the second sub-second data line DL 22; the voltage of the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 is equal to or approximately equal to the voltage of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL 22; the data signals of the pixels PX in the first sub-first data line DL11, the common data line DL0, and the second sub-first data line DL12 are equal to or approximately equal to the data signals of the pixels PX in the first sub-second data line DL21, the common data line DL0, and the second sub-second data line DL22, so that the display brightness of the display panel 200 is uniform, and the split screen phenomenon is avoided.

Fig. 7 is another structural schematic diagram of the display panel in the embodiment of the invention.

As shown in fig. 7, the display panel 200 further includes a first sub-connection line CL1, a second sub-connection line CL2, and a first compensation resistor CR 1; the first sub-first data line DL11 and the first switching unit SW1 are electrically connected by a first sub-connecting line CL1, and the second sub-first data line DL12 and the first switching unit SW1 are electrically connected by a second sub-connecting line CL 2; the first compensation resistor CR1 is connected in parallel with the first sub-connection line CL 1.

In the embodiment of the present invention, the first compensation resistor CR1 is connected in parallel with the first sub-connection line CL1, the parallel resistance between the first compensation resistor CR1 and the first sub-connection line CL1 is smaller than the resistance of the first sub-connection line CL1, the first sub-first data line DL11 is electrically connected to the first switching unit SW1 through the parallel resistance between the first compensation resistor CR1 and the first sub-connection line CL1 rather than electrically connected to the first switching unit SW1 through the first sub-connection line CL1, and the difference between the resistances of the first sub-first data line DL11, the first compensation resistor CR 1/the first sub-connection line CL1, and the common data line DL0 and the resistances of the first sub-second data line DL21 and the common data line DL0 is reduced; the difference between the load of the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 and the load of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL22 is reduced; the difference between the voltage of the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 and the voltage of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL22 is reduced; the difference between the data signal of the pixel PX in the first sub-first data line DL11, the common data line DL0, and the second sub-first data line DL12 and the data signal of the pixel PX in the first sub-second data line DL21, the common data line DL0, and the second sub-second data line DL22 is reduced, and the difference in the display luminance of the display panel 200 is reduced, which alleviates the split screen phenomenon.

Fig. 8 is a schematic structural diagram of a display panel according to another embodiment of the disclosure.

As shown in fig. 8, the display panel 200 further includes a first sub-connection line CL1, a second sub-connection line CL2, and a first compensation resistor CR 1; the first sub-first data line DL11 and the first switching unit SW1 are electrically connected by a first sub-connecting line CL1, and the second sub-first data line DL12 and the first switching unit SW1 are electrically connected by a second sub-connecting line CL 2; the first compensation resistor CR1 is connected in parallel to the first sub-first data line DL 11.

In the embodiment of the present invention, the first compensation resistor CR1 is connected in parallel to the first sub-first data line DL11, and the parallel resistance of the first compensation resistor CR1 and the first sub-first data line DL11 is smaller than the resistance of the first sub-first data line DL 11; the parallel resistance of the first compensation resistor CR1 and the first sub-first data line DL11 is smaller than the resistance of the first sub-second data line DL 21; the difference between the parallel resistance of the first compensation resistor CR1 and the first sub-first data line DL11 and the resistance of the first sub-second data line DL21 is equal to or approximately equal to the resistance of the first sub-connecting line CL 1; the difference between the resistance of the first sub-first data line DL 11/the first compensation resistor CR1, the first sub-connection line CL1 and the resistance of the common data line DL0 and the resistance of the first sub-second data line DL21 and the resistance of the common data line DL0 is reduced; the difference between the load of the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 and the load of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL22 is reduced; the voltage difference between one of the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 and one of the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL22 is reduced; the difference between the data signal of the pixel PX in the first sub-first data line DL11, the common data line DL0, and the second sub-first data line DL12 and the data signal of the pixel PX in the first sub-second data line DL21, the common data line DL0, and the second sub-second data line DL22 is reduced, and the difference in the display luminance of the display panel 200 is reduced, which alleviates the split screen phenomenon.

Fig. 9 is a flowchart illustrating a display panel driving method according to an embodiment of the invention.

As shown in fig. 2, in the display panel driving method 300, the display panel 200 includes: the display area AA comprises a first display area AA1, a second display area AA2 and a third display area AA3, wherein the second display area AA2 is positioned between the first display area AA1 and the third display area AA3, the edge of the second display area AA2 comprises a concave edge section NB, and the concave direction of the concave edge section NB faces to the second display area AA 2; a plurality of pixels PX arranged in an array, the first display area AA1 including a first pixel row PXC1, the second display area AA2 including a second pixel row PXC2, the third display area AA3 including a third pixel row PXC3, the number of pixels in the second pixel row PXC2 being smaller than the number of pixels in the first pixel row PXC1 and the third pixel row PXC3, respectively; the display device includes a first pixel column PXR1 and a second pixel column PXR2, the number of pixels in the first pixel column PXR1 is smaller than the number of pixels in the second pixel column PXR2, the second pixel column PXR2 includes a common data line DL0 located in a second display area AA2, and the first pixel column PXR1 and the second pixel column PXR2 share the common data line DL 0. The display panel 200 further includes: a plurality of first scan lines SL1 located within the first display area AA1, a plurality of second scan lines SL2 located within the second display area AA2, and a plurality of third scan lines SL3 located within the third display area AA 3.

As shown in fig. 9, the display panel driving method 300 includes: performing a first data writing stage S310, performing a second data writing stage S320, and performing a third data writing stage S330; in the first data writing phase S310, scan signals are transmitted line by line through the plurality of third scan lines SL 3; in the second data writing phase S320, scan signals are transmitted line by line through the plurality of second scan lines SL 2; in the third data writing phase S330, scan signals are transmitted line by line through the plurality of first scan lines SL 1.

In the embodiment of the present invention, in the first data writing phase S310, the scan signals are transmitted line by line through the plurality of third scan lines SL3, so as to write the data signals in the first pixel column PXR1 and the second pixel column PXR2 of the third display area AA 3; in the second data writing phase S320, scan signals are transmitted line by line through the plurality of second scan lines SL2 to write data signals in the second pixel columns PXR2 of the second display area AA 2; scan signals are transmitted row by row through the plurality of first scan lines SL1 in the third data write phase S330 to write data signals in the first and second pixel columns PXR1 and PXR2 of the first display area AA 1.

As shown in fig. 2, in the display panel driving method 300, the non-display area NA includes a first sub non-display area NA1, the first sub non-display area NA1 is adjacent to the recessed edge segment NB; a plurality of first switching units SW1, the first pixel column PXR1 includes a first data line DL10, the first data line DL10 includes a first sub-first data line DL11 and a second sub-first data line DL12, the first sub-first data line DL11 and the second sub-first data line DL12 are coupled to the same common data line DL0 through different first switching units SW1, respectively, wherein the first sub-first data line DL11 is located in a first display area AA1, the second sub-first data line DL12 is located in a third display area AA3, and the first sub-non-display area NA1 is located between the first sub-first data line DL11 and the second sub-first data line DL 12; a plurality of second switching units SW2, the second pixel column PXR2 includes a second data line DL20, the second data line DL20 includes a first sub-second data line DL21, a second sub-second data line DL22 and a common data line DL0, the first sub-second data line DL21 and the second sub-second data line DL22 are respectively coupled to the common data line DL0 through different second switching units SW2, wherein the first sub-second data line DL21 is located in the first display area AA1, and the second sub-second data line DL22 is located in the third display area AA 3; the on states of the first and second switching units SW1 and SW2 are different.

As shown in fig. 2, in the display panel driving method 300, the first switching unit SW1 is a first switching transistor ST1, the second switching unit SW2 is a second switching transistor ST2, and the first switching transistor ST1 and the second switching transistor ST2 are different in type; the display panel 200 further includes a first control line GL1 and a second control line GL2, wherein a control electrode of the first switching transistor ST1 is electrically connected to the first control line GL1, and a control electrode of the second switching transistor ST2 is electrically connected to the second control line GL 2.

FIG. 10 is a timing diagram illustrating a driving method of a display panel according to an embodiment of the invention.

As shown in fig. 10, in the process of transmitting the scan signals by the first scan line SL1 row by row, at a first time T1, the N-1 th row first scan line SL1 transmits an on signal, the N-1 th row first scan line SL1 transmits an off signal, and the N +1 th row first scan line SL1 transmits an off signal, so that the pixels of the N-1 th row write the data signals; at a second time T2, the nth row first scan line SL1 transmits an on signal, the N-1 th row first scan line SL1 transmits an off signal, and the N +1 th row first scan line SL1 transmits an off signal, so that the nth row pixels are written with the data signals; at a third time T3, the N +1 th row first scan line SL1 transmits an on signal, the N-1 th row first scan line SL1 transmits an off signal, and the N th row first scan line SL1 transmits an off signal, so that the N +1 th row pixels are written with the data signals; the plurality of rows of the first scan lines SL1 sequentially transmit turn-on signals so that a plurality of rows of pixels sequentially write data signals. The process of transmitting the scanning signals by the second scanning line SL2 and the process of transmitting the scanning signals by the third scanning line SL3 are also the same, and the description is omitted.

FIG. 11 is another timing diagram illustrating a driving method of a display panel according to an embodiment of the invention.

As shown in fig. 4 and 11, in the first data writing phase S310, an on signal is transmitted through the first control line GL1, and an off signal is transmitted through the second control line GL 2; turning on the first switching transistor ST1 and turning off the second switching transistor ST 2; data signals are transmitted through the second sub-first data line DL12 and the second sub-second data line DL 22.

In the embodiment of the invention, in the first data writing phase S310, the first switch transistor ST1 is turned on, the second switch transistor ST2 is turned off, the second sub-first data line DL12 is electrically connected to the common data line DL0, the second sub-second data line DL22 is not electrically connected to the common data line DL0, and the second sub-first data line DL12 and the second sub-second data line DL22 are not shorted; the plurality of third scan lines SL3 transmit scan signals line by line, the second sub-first data line DL12 and the second sub-second data line DL22 transmit data signals, and the first pixel column PXR1 and the second pixel column PXR2 of the third display area AA3 write the data signals to make the pixels PX of the third display area AA3 emit light.

FIG. 12 is another timing diagram illustrating a driving method of a display panel according to an embodiment of the invention.

As shown in fig. 4 and 12, in the first data writing phase S310, an on signal is transmitted through the second control line GL2, and an off signal is transmitted through the first control line GL 1; turning on the second switching transistor ST2, turning off the first switching transistor ST 1; the data signal is transmitted through the second sub-first data line DL12 and the second sub-second data line DL 22.

In the embodiment of the invention, in the first data writing phase S310, the second switch transistor ST2 is turned on, the first switch transistor ST1 is turned off, the second sub-second data line DL22 is electrically connected to the common data line DL0, the second sub-first data line DL12 is not electrically connected to the common data line DL0, and the second sub-first data line DL12 and the second sub-second data line DL22 are not shorted; the plurality of third scan lines SL3 transmit scan signals line by line, the second sub-first data line DL12 and the second sub-second data line DL22 transmit data signals, and the first pixel column PXR1 and the second pixel column PXR2 of the third display area AA3 write the data signals to make the pixels PX of the third display area AA3 emit light.

As shown in fig. 11 and 12, in the second data writing phase S320, an on signal is transmitted through the second control line GL2, and an off signal is transmitted through the first control line GL 1; turning on the second switching transistor ST2, turning off the first switching transistor ST 1; the data signal is transmitted through the second sub-second data line DL22 and the common data line DL 0.

In the embodiment of the invention, in the second data writing phase S320, the second switching transistor ST2 is turned on, the first switching transistor ST1 is turned off, and the second sub-second data line DL22 is electrically connected to the common data line DL 0; the plurality of second scan lines SL2 transmit scan signals line by line, the second sub-second data lines DL22 and the common data lines DL0 transmit data signals, and the second pixel columns PXR2 of the second display area AA2 write the data signals to make the pixels PX of the second display area AA2 emit light; alternatively, the data signals are transmitted through the second sub-second data line DL22 and the common data line DL0, instead of the data signals transmitted through the second sub-first data line DL12 and the common data line DL0, power consumption can be saved.

As shown in fig. 11 and 12, in the third data writing phase S330, an on signal is transmitted through the first control line GL1, and an off signal is transmitted through the second control line GL 2; turning on the first switching transistor ST1 and turning off the second switching transistor ST 2; data signals are transmitted through the first data line DL10 and the common data line DL 0.

In the embodiment of the invention, in the third data writing phase S330, the first switching transistor ST1 is turned on, the second switching transistor ST2 is turned off, the first sub-first data line DL11 is electrically connected to the common data line DL0, and the second sub-first data line DL12 is electrically connected to the common data line DL 0; the plurality of first scan lines SL1 transmit scan signals line by line, the first sub-first data line DL11, the common data line DL0 and the second sub-first data line DL12 transmit data signals, and the first pixel column PXR1 of the first display area AA1 writes the data signals to make the pixels PX of the first pixel column PXR1 in the first display area AA1 emit light; the first pixel column PXR1 and the second pixel column PXR2 of the first display area AA1 write data signals respectively so as not to interfere with each other.

As shown in fig. 11 and 12, in the third data writing phase S330, an on signal is transmitted through the second control line GL2, and an off signal is transmitted through the first control line GL 1; turning on the second switching transistor ST2, turning off the first switching transistor ST 1; the data signal is transmitted through the second data line DL 20.

In the embodiment of the invention, in the third data writing phase S330, the second switching transistor ST2 is turned on, the first switching transistor ST1 is turned off, the first sub-second data line DL21 is electrically connected to the common data line DL0, and the second sub-second data line DL22 is electrically connected to the common data line DL 0; the plurality of first scanning lines SL1 transmit scanning signals line by line, the first sub-second data line DL21, the common data line DL0 and the second sub-second data line DL22 transmit data signals, and the second pixel column PXR2 of the first display area AA1 writes the data signals to make the pixels PX of the second pixel column PXR2 in the first display area AA1 emit light; the first pixel column PXR1 and the second pixel column PXR2 of the first display area AA1 write data signals respectively so as not to interfere with each other.

In the embodiment of the present invention, the sequence of the first data writing stage S310, the second data writing stage S320, and the third data writing stage S330 is not limited; preferably, the first data writing stage S310, the second data writing stage S320, and the third data writing stage S330 are sequentially executed in a cycle, or the third data writing stage S330, the second data writing stage S320, and the first data writing stage S310 are sequentially executed in a cycle.

As shown in fig. 13, the display device 400 includes the display panel 200.

In an embodiment of the present invention, the display device 400 may implement a display function, such as a smart phone or a similar display device. The display panel 200 is described above and will not be described in detail.

In summary, the present invention provides a display panel, a display panel driving method and a display device. The display panel includes: the display area comprises a first display area, a second display area and a third display area, wherein the second display area is positioned between the first display area and the third display area, the edge of the second display area comprises a concave edge section, and the concave direction of the concave edge section faces to the second display area; the display device comprises a plurality of pixels, a first display area and a second display area, wherein the plurality of pixels are arranged in an array manner, the first display area comprises a first pixel row, the second display area comprises a second pixel row, the third display area comprises a third pixel row, and the number of pixels in the second pixel row is respectively smaller than that of the pixels in the first pixel row and that of the pixels in the third pixel row; the display device comprises a first pixel column and a second pixel column, wherein the number of pixels in the first pixel column is smaller than that of pixels in the second pixel column, the second pixel column comprises a common data line positioned in a second display area, and the first pixel column and the second pixel column share the common data line. The display panel achieves narrow frame.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A display panel, comprising:

a first pixel column and a second pixel column, a number of pixels in the first pixel column being smaller than a number of pixels in the second pixel column, a data line of the first pixel column extending at the first display area and the third display area and being interrupted at the recessed edge section, the second pixel column including a common data line at the second display area, the first pixel column and the second pixel column sharing the common data line.

2. The display panel according to claim 1, wherein the non-display region comprises a first sub non-display region adjacent to the recessed edge segment;

3. The display panel according to claim 2, wherein the first switching unit is a first switching transistor, the second switching unit is a second switching transistor, and types of the first switching transistor and the second switching transistor are different;

4. The display panel according to claim 3, wherein a control electrode of each of the first switching transistors in the first display region is electrically connected to a same one of the first control lines, and wherein a control electrode of each of the first switching transistors in the third display region is electrically connected to a same one of the first control lines;

5. The display panel according to claim 4, wherein a control electrode of each of the first switching transistors is electrically connected to the same one of the first control lines;

6. The display panel according to claim 2, further comprising a first sub-connection line, a second sub-connection line;

7. The display panel according to claim 2, further comprising a first sub-connection line, a second sub-connection line;

8. The display panel according to claim 2, further comprising a first sub-connection line;

the cross-sectional area of the first sub-connecting line is larger than that of the first sub-first data line.

9. The display panel according to claim 2, further comprising a first sub-connection line, a second sub-connection line, a first compensation resistor;

10. The display panel according to claim 2, further comprising a first sub-connection line, a second sub-connection line, a first compensation resistor;

11. A display panel driving method is characterized in that the display panel comprises a display area and a non-display area, the display area comprises a first display area, a second display area and a third display area, wherein the second display area is positioned between the first display area and the third display area, the edge of the second display area comprises a concave edge section, and the concave direction of the concave edge section faces to the second display area;

a first pixel column and a second pixel column, a number of pixels in the first pixel column being smaller than a number of pixels in the second pixel column, data lines of the first pixel column extending at the first display area and the third display area and being interrupted at the recessed edge section, the second pixel column including a common data line at the second display area, the first pixel column and the second pixel column sharing the common data line;

12. The display panel driving method according to claim 11, wherein the non-display region includes a first sub non-display region adjacent to the recessed edge section;

13. The display panel driving method according to claim 12, wherein the first switching unit is a first switching transistor, the second switching unit is a second switching transistor, and types of the first switching transistor and the second switching transistor are different;

14. The display panel driving method according to claim 13, wherein in the first data writing phase, an on signal is transmitted through the first control line, and an off signal is transmitted through the second control line;

15. The display panel driving method according to claim 13, wherein in the first data writing phase, an on signal is transmitted through the second control line, and an off signal is transmitted through the first control line;

16. The display panel driving method according to claim 13, wherein in the second data writing phase, an on signal is transmitted through the second control line, and an off signal is transmitted through the first control line;

and transmitting a data signal through the second sub-second data line and the common data line.

17. The display panel driving method according to claim 13, wherein in the third data writing phase, an on signal is transmitted through the first control line, and an off signal is transmitted through the second control line;

18. The display panel driving method according to claim 17, wherein in the third data writing phase, an on signal is transmitted through the second control line, and an off signal is transmitted through the first control line;

and transmitting a data signal through the second data line.

19. A display device characterized by comprising the display panel according to any one of claims 1 to 10.