CN109637352B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN109637352B CN109637352B CN201811627627.4A CN201811627627A CN109637352B CN 109637352 B CN109637352 B CN 109637352B CN 201811627627 A CN201811627627 A CN 201811627627A CN 109637352 B CN109637352 B CN 109637352B
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- display panel
- clock signal
- circuit
- output selection
- selection circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
The invention discloses a display panel and a display device, wherein the display panel comprises a multi-output selection circuit and a scanning drive circuit, the multi-output selection circuit is electrically connected with a data line, and the scanning drive circuit is electrically connected with a scanning line; the multi-output selection circuit comprises a first multi-output selection circuit, and the scanning drive circuit comprises a first scanning drive circuit; the clock signal lead comprises a first clock signal lead which is electrically connected with the clock signal input end of the first multi-output selection circuit, and the first scanning driving circuit is positioned between the first clock signal lead and the first multi-output selection circuit. By adopting the technical scheme, the overlapping of the clock signal lead and the scanning driving circuit can be reduced, the crosstalk between the clock signal and the scanning signal output by the scanning driving circuit is reduced, and the display effect of the display panel is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.
Background
At present, in the design process of a display panel, in order to reduce the number of output channels of a driver chip, a multi-output selection circuit (DEMUX circuit) is added in a driver circuit of the display panel, so as to achieve the purpose of reducing the output channels of the driver chip by times.
In the prior art, the DEMUX circuit is generally disposed on a frame at one side of the display panel, for example, on the side of the driver IC, but this results in a larger area of the frame. In order to avoid the problem that a certain frame of the display panel is large in area, the DEMUX circuits can be arranged at a plurality of frame positions of the display panel. Because the frame position in the display panel is still provided with the scanning drive circuit, so can cause the signal of scanning drive circuit output and the signal of DEMUX circuit output to crosstalk each other, influence the display effect.
Disclosure of Invention
In view of this, embodiments of the present invention provide a display panel and a display device to reduce crosstalk between a signal output by a Demux circuit and a signal output by a scan driving circuit, so as to improve a display effect.
In a first aspect, an embodiment of the present invention provides a display panel, including:
the display device comprises a display area and a non-display area surrounding the display area, wherein the display area comprises a plurality of scanning lines and a plurality of data lines, and the plurality of scanning lines and the plurality of data lines are insulated and crossed to define a plurality of sub-pixel units; the non-display area comprises a multi-output selection circuit and a scanning driving circuit, the multi-output selection circuit is electrically connected with the data line, and the scanning driving circuit is electrically connected with the scanning line; the multi-output selection circuit comprises a first multi-output selection circuit, and the scanning driving circuit comprises a first scanning driving circuit;
the first scanning driving circuit is positioned between the first clock signal lead and the first multi-output selection circuit.
In a second aspect, an embodiment of the present invention further provides a display device, including the display panel provided in the first aspect.
In the display panel and the display device provided by the embodiment of the invention, the multi-path output selection circuit in the display panel comprises a first multi-path output selection circuit, and the scanning driving circuit comprises a first scanning driving circuit; the clock signal lead comprises a first clock signal lead which is electrically connected with the clock signal input end of the first multi-output selection circuit, and the first scanning driving circuit is positioned between the first clock signal lead and the first multi-output selection circuit. By adopting the technical scheme, the first clock signal lead is arranged on one side of the first scanning driving circuit far away from the display area, so that the overlapping of the clock signal lead and the scanning driving circuit can be reduced, the crosstalk between the clock signal and the scanning signal output by the scanning driving circuit is reduced, and the display effect of the display panel is improved.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, a brief description is given below of the drawings used in describing the embodiments. It should be clear that the described figures are only views of some of the embodiments of the invention to be described, not all, and that for a person skilled in the art, other figures can be derived from these figures without inventive effort.
FIG. 1 is a schematic diagram of a display panel according to the prior art;
fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 3 is an enlarged schematic view of a region A of the display panel shown in FIG. 2;
FIG. 4 is a schematic structural diagram of another display panel provided in the embodiment of the present invention;
FIG. 5 is an enlarged schematic view of a region B of the display panel provided in FIG. 4;
FIG. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 7 is an enlarged schematic view of a region C of the display panel provided in FIG. 6;
FIG. 8 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 9 is an enlarged schematic view of a D region of the display panel provided in FIG. 8;
FIG. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a demultiplexer circuit according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be fully described by the detailed description with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, not all embodiments, and all other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without inventive efforts fall within the scope of the present invention.
Fig. 1 is a schematic structural diagram of a display panel in the prior art, and as shown in fig. 1, the display panel includes a scan line 11, a data line 12, and a plurality of sub-pixel units 13 defined by the scan line 11 and the data line 12 crossing each other in an insulating manner; the display panel further includes a demultiplexer circuit 14 electrically connected to the data lines 12 to supply data line signals to the data lines 12, and a scan driver circuit 15 electrically connected to the scan lines 11 to supply scan signals to the scan lines 11. As shown in fig. 1, the multi-output selection circuit 14 overlaps with the scan driving circuit 15, so that crosstalk exists between the scan signal and the data signal, which affects normal display of the display panel.
Based on the above technical problem, an embodiment of the present invention provides a display panel, including a display area and a non-display area surrounding the display area, where the display area includes a plurality of scan lines and a plurality of data lines, and the plurality of scan lines and the plurality of data lines are insulated and crossed to define a plurality of sub-pixel units; the non-display area comprises a multi-output selection circuit and a scanning driving circuit, the multi-output selection circuit is electrically connected with the data line, and the scanning driving circuit is electrically connected with the scanning line; the multi-output selection circuit comprises a first multi-output selection circuit, and the scanning drive circuit comprises a first scanning drive circuit; the first scanning driving circuit is positioned between the first clock signal lead and the first multi-output selection circuit. By adopting the technical scheme, the first clock signal lead is electrically connected with the signal input end of the first multi-path output selection circuit, and the first driving scanning signal is arranged between the first clock signal lead and the first multi-path output selection circuit, so that the crosstalk between the clock signal and the scanning signal output by the scanning driving circuit is reduced, and the display effect of the display panel is improved.
The above is the core idea of the present invention, and the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.
Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention, fig. 3 is an enlarged structural diagram of an area a in the display panel provided in fig. 2, as shown in fig. 2 and fig. 3, the display panel provided in an embodiment of the present invention may include a display area a and a non-display area b surrounding the display area a, the display area a includes a plurality of scan lines 21 and a plurality of data lines 22, the plurality of scan lines 21 and the plurality of data lines 22 are insulated and crossed to define a plurality of sub-pixel units 23, the non-display area b includes a multi-output selection circuit 24 and a scan driving circuit 25, the multi-output selection circuit 24 is electrically connected to the data lines 22, and the scan driving circuit 25 is electrically connected to the scan lines 11; the multi-output selection circuit 24 includes a first multi-output selection circuit 241, and the scan driving circuit 25 includes a first scan driving circuit 251;
the display panel further includes a clock signal lead 26, the clock signal lead 26 includes a first clock signal lead 261, the first clock signal lead 261 is electrically connected to a clock signal input terminal of the first multi-output selection circuit 241, and the first scan driving circuit 251 is located between the first clock signal lead 261 and the first multi-output selection circuit 241.
As shown in fig. 2 and 3, the multi-output selection circuit 24 includes a first multi-output selection circuit 241, the scan driving circuit 25 includes a first scan driving circuit 251, the clock signal lead 26 includes a first clock signal lead 261, the first clock signal lead 261 is electrically connected to a clock signal input terminal of the first multi-output selection circuit 241, and the first scan driving circuit 251 is located between the first clock signal lead 261 and the first multi-output selection circuit 241, such that the first clock signal lead 261 bypasses the first scan driving circuit 251 from a side of the first scan circuit 251 away from the display area a and is connected to the first multi-output selection circuit 241, which can reduce overlapping of the first clock signal lead 261 and the first scan driving circuit 251, reduce crosstalk between the clock signal and the scan signal output by the scan driving circuit, ensure good fidelity of the clock signal and the scan signal, the display effect of the display panel is improved.
Fig. 4 is a schematic structural diagram of another display panel provided in an embodiment of the present invention, and fig. 5 is an enlarged structural diagram of a region B in the display panel provided in fig. 4; as shown in fig. 4 and fig. 5, the demultiplexer circuit 24 according to the embodiment of the present invention may further include a second demultiplexer circuit 242, the clock signal lead 26 may further include a second clock signal lead 262, and the second clock signal lead 262 is electrically connected to the clock signal input terminal of the second demultiplexer circuit 242.
Illustratively, as shown in fig. 4 and 5, the second clock signal lead 262 is electrically connected to the clock signal input terminal of the second demultiplexer circuit 242, such that the first clock signal lead 261 and the second clock signal lead 262 are electrically connected to the demultiplexer circuit 24, respectively, and the first clock signal lead 261 and the second clock signal lead 262 are connected in parallel, thereby reducing the resistance of the clock signal lead 26 and reducing the loss of the clock signal on the clock signal lead 26. Furthermore, the first clock signal lead 261 is connected from the clock signal input terminal of the first demultiplexer electrode 241 to the demultiplexer 24, and the second clock signal lead 262 is connected from the clock signal input terminal of the second demultiplexer electrode 242 to the demultiplexer 24, so that both ends of the demultiplexer 24 are directly connected to the clock signal lead 26, thereby avoiding the delay of the clock signal caused by a long distance from the clock signal lead 26 at one end of the demultiplexer 24, ensuring that the difference between the lighting time of the pixel unit 23 corresponding to the first demultiplexer 241 and the lighting time of the pixel unit corresponding to the second demultiplexer 242 is almost the same, and ensuring the display effect of the display panel.
Optionally, the display panel according to the embodiment of the present invention may further include a first clock signal line 31 and a second clock signal line 32, where the first clock signal line 31 is used to connect to the first multi-output selection circuit 241, and the second clock signal line 32 is used to connect to the second multi-output selection circuit 242. Alternatively, the first clock signal line 31 and the second clock signal line 32 may be connected to each other, as shown in fig. 4 and 5, to ensure that the first clock signal lead 261 and the second clock signal lead 262 are connected in parallel, so as to reduce the resistance of the clock signal lead 26 and reduce the loss of the clock signal on the clock signal lead 26. Alternatively, the first clock signal line 31 and the second clock signal line 32 may also be disconnected. Specifically, fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and fig. 7 is an enlarged structural diagram of a region C in the display panel provided in fig. 6, as shown in fig. 6 and fig. 7, the first scan driving circuit 251 can input a scan signal to the pixel unit 23 from a position where the first signal line 31 and the second signal line 32 are disconnected, so as to reduce overlap between the multi-output selecting circuit 24 and the first scan driving circuit 251, reduce crosstalk between a clock signal and the scan signal output by the first scan driving circuit 251, and improve a display effect of the display panel.
Optionally, as shown in fig. 2 to fig. 7, the display panel according to the embodiment of the present invention may further include a clock signal input pad 33, the first clock signal lead 261 and/or the second clock signal lead 262 are electrically connected to the clock signal input pad 33, and the clock signal is transmitted to the first clock signal lead 261 and/or the second clock signal lead 262 through the clock signal input pad 33, so as to ensure that the demultiplexer circuit 24 is turned on.
For example, in the case where the first clock signal lead 261 and the second clock signal lead 262 both supply a clock signal to the demultiplexer circuit, as shown in fig. 4 to 7, the first clock signal lead 261 and the second clock signal lead 262 may both be electrically connected to the clock signal input pad 33, and one of the first clock signal lead 261 or the second clock signal lead 262 may be electrically connected to the clock signal input pad 33. Specifically, fig. 8 is a schematic structural diagram of another display panel according to an embodiment of the present invention, fig. 9 is a schematic structural diagram of an enlarged region D in the display panel provided in fig. 8, and as shown in fig. 8 and fig. 9, one of the first clock signal lead 261 and the second clock signal lead 262 is electrically connected to the clock signal input pad 33, and at the same time, the first clock signal lead 261 and the second clock signal lead 262 are electrically connected to each other, so that the number of the signal input pads 33 is reduced and the display panel is simple in design in the case that both the first clock signal lead 261 and the second clock signal lead 262 can provide clock signals to the demultiplexer circuit.
Alternatively, as shown in fig. 2 to 9 with continued reference, the display panel according to the embodiment of the invention may further include a driving IC 27 located in the non-display region b, and the signal input pad 33 is bonded to the driving IC 27.
Exemplarily, the signal input pad 33 is arranged to be bound with the driving IC 27, so that the integration level of the driving IC 27 can be improved, the area of the non-display region b occupied by the signal input pad 33 can be reduced, and the frame of the display panel can be reduced.
Optionally, fig. 10 is a schematic structural diagram of another display panel provided in the embodiment of the present invention, and as shown in fig. 10, the display panel provided in the embodiment of the present invention may further include a flexible circuit board 34, and the clock signal input pad 33 is bound to the flexible circuit board 34.
As shown in fig. 10, the clock signal input pad 33 is bonded to the flexible circuit board 34, so as to ensure that the clock signal can be normally transmitted to the demultiplexer circuit 24, and ensure that the demultiplexer circuit 24 is turned on. Simultaneously, by additionally arranging the flexible circuit board 34, the flexible circuit board 34 can be bent to one side of the non-light-emitting side of the display panel, the frame of the display panel can be reduced, and the screen occupation ratio of the display panel is improved.
Alternatively, as shown in fig. 2 to 10 with continued reference, the display panel according to the embodiment of the present invention includes a plurality of clock signal leads 26, a plurality of data signal buses 28; each of the multiple output selection circuits 24 includes a plurality of switch circuits 29, each of the switch circuits 29 includes a signal input end 291, a signal output end 292, and a control end 293, the signal input end 291 is electrically connected to the data signal bus 28, the signal output end 292 is electrically connected to the data line 22, and the control end 293 is electrically connected to the clock signal lead 26; in the same multi-output selection circuit 24, the signal input ends 291 of the plurality of switch circuits 29 are electrically connected to the same data signal bus 28, the signal output end 292 of each switch circuit 29 is electrically connected to a different data line 22, and the control end 293 of each switch circuit 29 is electrically connected to a different clock signal lead 26; in the different demultiplexer circuits 24, the signal input terminals 291 of the switch circuits 29 are electrically connected to the different data signal buses 28, respectively.
For example, the signal input ends 291 of the plurality of switch circuits 29 are electrically connected to the same data signal trace 28, the signal output end 292 of each switch circuit 29 is electrically connected to a different data line 22, the control end 293 of each switch circuit 29 is electrically connected to a different clock signal lead 26, and the switch circuits 29 are controlled to be turned on and off by the clock signal lead 26, so that the purpose of transmitting signals provided by the same data signal bus 28 to different data lines 22 is achieved, the number of output pins on the driving IC 27 can be reduced, and the integration level of the driving IC 27 is improved.
Alternatively, each clock signal lead 26 may be connected to the control terminals 293 of the switch circuits 29 corresponding to the same emission color sub-pixel units 23 in the plurality of demultiplexer circuits 24. For example, each clock signal lead 26 is connected to the control terminal 293 of the switch circuit 29 corresponding to the red sub-pixel unit 23 in the multiple output selection circuits 24, or connected to the control terminal 293 of the switch circuit 29 corresponding to the green sub-pixel unit 23 in the multiple output selection circuits 24, or connected to the control terminal 293 of the switch circuit 29 corresponding to the blue sub-pixel unit 23 in the multiple output selection circuits 24, so as to ensure that the sub-pixel units 23 with the same light-emitting color in the display panel can be simultaneously lighted, and improve the light-emitting efficiency of the display panel.
Alternatively, with continued reference to fig. 2, in the display panel provided in the embodiment of the present invention, each of the demultiplexer circuits 24 includes three switch circuits 29; the three sub-pixel units 23 form a pixel unit 30; the signal output terminals 292 of the three switch circuits 29 are connected to the three data lines 22 corresponding to the same pixel unit. For example, fig. 2 illustrates that the display panel includes three clock signal leads 26, each of the multiple output selection circuits 24 includes three switch circuits 29, three sub-pixel units 23 form a pixel unit, and signal output terminals of the three switch circuits 29 are connected to three data lines 22 corresponding to the same pixel unit. Therefore, one data signal bus 28 can drive one pixel unit to emit light, and the driving efficiency of the display panel is improved.
Fig. 11 is a schematic structural diagram of a multi-output selection circuit according to an embodiment of the present invention, and as shown in fig. 11, a display panel according to an embodiment of the present invention may include three switch circuits 29 for each multi-output selection circuit 24; the three sub-pixel units 23 form a pixel unit 30; two adjacent multiple output selection circuits 24 form a multiple output selection circuit group 31; two pixel units 30 arranged adjacently in the same row form a pixel unit group 32; the signal output ends 292 of the three switch circuits 29 in the first multi-output selection circuit 24 in the multi-output selection circuit group 31 are connected with the data lines 22 corresponding to the ith sub-pixel unit 23 in the pixel unit group 32; the signal output ends 292 of the three switch circuits 29 in the second multi-output selection circuit 24 in the multi-output selection circuit group 31 are connected with the data lines 22 corresponding to the jth sub-pixel unit 23 in the pixel unit group 32; wherein, i is 2n-1, j is 2n, and n is a positive integer.
Illustratively, in the process of driving liquid crystal to deflect for display, in order to improve the display effect, voltages with opposite polarities need to be input into two adjacent columns of sub-pixel units 23, in the embodiment of the present invention, two adjacent multiple output selection circuits 24 are arranged to form a multiple output selection circuit group 31; two pixel units 30 arranged adjacently in the same row form a pixel unit group 32; the signal output ends 292 of the three switch circuits 29 in the first multi-output selection circuit 24 in the multi-output selection circuit group 31 are connected with the data lines 22 corresponding to the ith sub-pixel unit 23 in the pixel unit group 32; the signal output ends 292 of the three switch circuits 29 in the second multi-output selection circuit 24 in the multi-output selection circuit group 31 are connected to the data lines 22 corresponding to the jth sub-pixel unit 23 in the pixel unit group 32, where i is 2n-1, j is 2n, and n is a positive integer. That is, the signal output ends 292 of the three switch circuits 29 in the first multi-output selection circuit 24 in the multi-output selection circuit group 31 are respectively connected with the data lines 22 corresponding to the odd number sub-pixel units 23 in the pixel unit group 32; the signal output ends 292 of the three switch circuits 29 in the second multiple output selection circuit 24 in the multiple output selection circuit group 31 are respectively connected with the data lines 22 corresponding to the even number of sub-pixel units 23 in the pixel unit group 32, and at the same display moment, the data signal bus 28 corresponding to the first multiple output selection circuit 24 in the multiple output selection circuit group can be set to input a forward voltage, and the data signal bus 28 corresponding to the second multiple output selection circuit 24 in the multiple output selection circuit group 31 can be set to input a reverse voltage, so that voltages with opposite polarities are input in the two adjacent columns of sub-pixel units 23, the liquid crystal is driven to deflect normally, and the display panel displays normally. Compared with a scheme of inputting voltages with opposite polarities into the two adjacent columns of sub-pixel units 23 by inverting the voltage signals provided by the same data signal bus 28, the technical scheme of the embodiment of the invention can reduce the power consumption of the display panel.
Alternatively, the switch circuit 29 may be a switch thin film transistor, and the switch thin film transistor may include a first source, a first drain, and a first gate, wherein the first source may serve as the signal input end 291 of the switch circuit, the first drain may serve as the signal output end 292 of the switch circuit, and the first gate may serve as the control end of the switch circuit 29. Optionally, the display panel provided in the embodiment of the present invention may further include a driving thin film transistor (not shown in the figure) located in the display area a, where the driving thin film transistor is used for driving the pixel unit 23 to emit light. The driving thin film transistor may include a second source electrode, a second drain electrode, and a second gate electrode, wherein the first source electrode may be disposed on the same layer as the second source electrode, the first drain electrode may be disposed on the same layer as the second drain electrode, and the first gate electrode may be disposed on the same layer as the second gate electrode, and the processes are completed in the same manufacturing process, so that the switching circuit 29 is ensured to be matched with the existing manufacturing process of the display panel, and the manufacturing process of the switching circuit 29 is ensured to be simple.
Optionally, the clock signal lead 26 provided in the embodiment of the present invention may be disposed on the same layer as the scan line 21; or may be disposed in the same layer as the data line 22; alternatively, the display panel provided in the embodiment of the present invention may further include a touch signal line (not shown in the figure), and the clock signal lead 26 may be disposed on the same layer as the touch signal line. No matter the clock signal lead 26 and the scanning line 21 are arranged on the same layer, or the data line 22 is arranged on the same layer, or the touch signal line is arranged on the same layer, the clock signal lead 26 and part of films in the existing display panel can be arranged on the same layer, and the clock signal lead can be matched with the preparation process of the existing display panel in the preparation process, so that the preparation process of the clock signal lead is simple.
Optionally, the outline of the display panel provided in the embodiment of the present invention may be non-rectangular, for example, the outline of the display panel may be circular, oval, or other display panels that require setting of the multiple output selection circuit at multiple boundary positions of the display panel, which is not limited in the embodiment of the present invention.
Optionally, the display panel according to the embodiment of the present invention may further include an electrostatic protection circuit, where the electrostatic protection circuit is located in the non-display area b and is used to perform electrostatic protection on the clock signal lead 26 and the first scan circuit 251 on a side of the first scan circuit 251 away from the display area a.
Optionally, the display panel provided in the embodiment of the present invention may be a liquid crystal display panel, and may also be an organic light emitting diode display panel, which is not limited in the embodiment of the present invention.
Fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 12, the display device 100 may include the display panel 101 according to any embodiment of the present invention. The display device 100 may be a mobile phone as shown in fig. 10, or may be a computer, a television, an intelligent wearable display device, and the like, which is not particularly limited in this embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (13)
1. A display panel, comprising:
the display device comprises a display area and a non-display area surrounding the display area, wherein the display area comprises a plurality of scanning lines and a plurality of data lines, and the plurality of scanning lines and the plurality of data lines are insulated and crossed to define a plurality of sub-pixel units; the non-display area comprises a multi-output selection circuit and a scanning driving circuit, the multi-output selection circuit is electrically connected with the data line, and the scanning driving circuit is electrically connected with the scanning line; the multi-output selection circuit comprises a first multi-output selection circuit, and the scanning driving circuit comprises a first scanning driving circuit;
the first scanning driving circuit is positioned between the first clock signal lead and the first multi-output selection circuit.
2. The display panel of claim 1, wherein the mux select circuit further comprises a second mux select circuit, the clock signal lead further comprises a second clock signal lead;
the second clock signal lead is electrically connected with a clock signal input end of the second multi-path output selection circuit.
3. The display panel according to claim 2, wherein the display panel further comprises a clock signal input pad;
the first clock signal lead and/or the second clock signal lead are electrically connected to the clock signal input pad.
4. The display panel according to claim 3, further comprising a driver IC in the non-display region;
the clock signal input pad is bound to the driver IC.
5. The display panel according to claim 3, wherein the display panel further comprises a flexible circuit board;
the clock signal input pad is bound with the flexible circuit board.
6. The display panel according to claim 1, comprising:
a plurality of clock signal leads, a plurality of data signal buses;
each of the multiple output selection circuits comprises a plurality of switch circuits, each of the switch circuits comprises a signal input end, a signal output end and a control end, the signal input end is electrically connected with the data signal bus, the signal output end is electrically connected with the data line, the control end is electrically connected with the clock signal lead, and the control end is a clock signal input end of the first multiple output selection circuit;
in the same multi-path output selection circuit, the signal input ends of the plurality of switch circuits are electrically connected with the same data signal bus, the signal output end of each switch circuit is electrically connected with different data lines, and the control end of each switch circuit is electrically connected with different clock signal leads; in different ones of the multiple output selection circuits, the signal input terminals of the switching circuit are electrically connected to different ones of the data signal buses, respectively.
7. The display panel according to claim 6, wherein each of the clock signal leads is connected to control terminals of the switch circuits corresponding to the sub-pixel units of the same emission color in the plurality of the demultiplexer circuits.
8. The display panel according to claim 6, comprising:
each of the multiple output selection circuits includes three of the switch circuits; the three sub-pixel units form a pixel unit; and the signal output ends of the three switch circuits are connected with three data lines corresponding to the same pixel unit.
9. The display panel according to claim 6, comprising:
each of the multiple output selection circuits includes three of the switch circuits; the three sub-pixel units form a pixel unit; two adjacent multipath output selection circuits form a multipath output selection circuit group; two pixel units which are arranged in the same row and adjacent to each other form a pixel unit group;
the signal output ends of three switch circuits in a first multi-path output selection circuit in the multi-path output selection circuit group are connected with the data line corresponding to the ith sub-pixel unit in the pixel unit group; the signal output ends of three switch circuits in a second multi-path output selection circuit in the multi-path output selection circuit group are connected with the data line corresponding to the jth sub-pixel unit in the pixel unit group; wherein, i is 2n-1, j is 2n, and n is a positive integer.
10. The display panel according to claim 6, wherein the switch circuit comprises a switch thin film transistor, the switch thin film transistor comprises a first source, a first drain and a first gate, the first source is a signal input terminal of the switch circuit, the first drain is a signal output terminal of the switch circuit, and the first gate is a control terminal of the switch circuit.
11. The display panel according to claim 1, wherein the display panel has a non-rectangular outline shape.
12. The display panel according to claim 1, wherein the display panel is a liquid crystal display panel or the display panel is an organic light emitting diode display panel.
13. A display device characterized by comprising the display panel according to any one of claims 1 to 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811627627.4A CN109637352B (en) | 2018-12-28 | 2018-12-28 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811627627.4A CN109637352B (en) | 2018-12-28 | 2018-12-28 | Display panel and display device |
Publications (2)
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| CN111445806B (en) * | 2020-04-16 | 2022-07-26 | 上海中航光电子有限公司 | Display panel and display device |
| WO2022000240A1 (en) * | 2020-06-30 | 2022-01-06 | 京东方科技集团股份有限公司 | Display substrate and display apparatus |
| CN114342368A (en) | 2020-08-07 | 2022-04-12 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN114203128B (en) * | 2021-12-17 | 2022-11-15 | 武汉京东方光电科技有限公司 | Display panel driving method and circuit and display device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104732908A (en) * | 2015-02-05 | 2015-06-24 | 友达光电股份有限公司 | Display panel |
| CN206134140U (en) * | 2016-11-01 | 2017-04-26 | 厦门天马微电子有限公司 | Display panel and display device |
| CN107039008A (en) * | 2016-02-03 | 2017-08-11 | 三星显示有限公司 | Display device |
| CN107689210A (en) * | 2016-08-05 | 2018-02-13 | 天马日本株式会社 | Display device |
| CN108648680A (en) * | 2018-06-25 | 2018-10-12 | 厦门天马微电子有限公司 | A kind of display panel, its driving method, driving device and display device |
| CN108806503A (en) * | 2018-06-29 | 2018-11-13 | 厦门天马微电子有限公司 | Display panel and display device |
| US10134328B2 (en) * | 2015-09-18 | 2018-11-20 | Samsung Display Co., Ltd. | Display device and driving method thereof |
-
2018
- 2018-12-28 CN CN201811627627.4A patent/CN109637352B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104732908A (en) * | 2015-02-05 | 2015-06-24 | 友达光电股份有限公司 | Display panel |
| US10134328B2 (en) * | 2015-09-18 | 2018-11-20 | Samsung Display Co., Ltd. | Display device and driving method thereof |
| CN107039008A (en) * | 2016-02-03 | 2017-08-11 | 三星显示有限公司 | Display device |
| CN107689210A (en) * | 2016-08-05 | 2018-02-13 | 天马日本株式会社 | Display device |
| CN206134140U (en) * | 2016-11-01 | 2017-04-26 | 厦门天马微电子有限公司 | Display panel and display device |
| CN108648680A (en) * | 2018-06-25 | 2018-10-12 | 厦门天马微电子有限公司 | A kind of display panel, its driving method, driving device and display device |
| CN108806503A (en) * | 2018-06-29 | 2018-11-13 | 厦门天马微电子有限公司 | Display panel and display device |
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