CN109901815B

CN109901815B - Parallel logic gate and multiplier based on resistive random access memory

Info

Publication number: CN109901815B
Application number: CN201910041671.5A
Authority: CN
Inventors: 崔小乐; 马潇; 张魁民
Original assignee: Peking University Shenzhen Graduate School
Current assignee: Peking University Shenzhen Graduate School
Priority date: 2019-01-16
Filing date: 2019-01-16
Publication date: 2023-03-24
Anticipated expiration: 2039-01-16
Also published as: CN109901815A

Abstract

The invention discloses a parallel logic gate and a multiplier based on a resistive random access memory, wherein the parallel logic gate comprises n input and logic units, n input or any combination of the logic units and a non-logic unit, the three logic units all use the resistive random access memory as an input/output device, and n is more than or equal to 2; the device is provided with a left selection end and a right selection end, and a voltage division resistor is connected to an inlet of the left selection end; the left selection end is used for inputting an excitation voltage, and the right selection end applies a voltage to match with a voltage signal of the signal input end and a voltage signal of the signal output end to control the state transformation of the resistive random access memory; the positive ends are commonly hung on the resistive random access memories on the same common line between the left selection end and the right selection end to realize AND logic, the positive ends are respectively hung on the resistive random access memories on the parallel lines between the left selection end and the right selection end to realize OR logic, and the negative ends are hung on the resistive random access memories on the lines between the left selection end and the right selection end to realize NOT logic; the parallel logic gate performs setting, inputting, operation and outputting according to a clock sequence to complete logic operation.

Description

Parallel logic gate and multiplier based on resistive random access memory

Technical Field

The invention relates to the field of logic circuits, in particular to a parallel logic gate and a high-performance multiplier circuit which are built by using a resistive random access memory.

Background

In 2008, hewlett-packard laboratory researchers published "the missing memrisor found" in Nature, announcing that TiO-based materials were found _x /TiO ₂ The thin film material has a memristive effect, and the resistive random access memory is prepared for the first time.

The resistive random access memory is a very simple three-layer thin film structure of 'metal-memristive material-metal', and belongs to a passive nonlinear device as shown in fig. 1, the resistance value of the resistive random access memory can be changed between a high-resistance state and a low-resistance state by applying different voltages to two ends of the resistive random access memory, and meanwhile, the resistance value state of the resistive random access memory is kept unchanged after the applied voltage disappears, and the resistive random access memory has a memory characteristic. An I-V curve of the resistive random access memory is shown in fig. 2, and the curve is divided into 4 regions: a high resistance state, a low resistance state, and two transition regions of resistance state change. Based on the memory characteristics of the resistive random access memory, the resistive random access memory can be used as a nonvolatile memory device.

In addition to being used as a memory device, the resistive random access memory also has an operation function, and a publication of Nature by j.borghetti of hewlett-packard laboratory in 2010 shows that the resistive random access memory can realize a logic operation function through an Implication (IMPLY) operation, which is complete in logic function, and can complete all logic operations without a traditional CMOS device. The resistive random access memory has the advantages of small volume and low power consumption, so the resistive random access memory is considered to be a next-generation device which replaces an MOS transistor and continues the development of Moore's law.

Through research on the existing resistive random access memory circuit, it can be found that the existing resistive random access memory-based logic implementation method mainly has the following problems to be solved:

1) The problem is most remarkable in logic circuits based on IMPLY operation, because the operation steps are too long, and the circuit functions are more complex and the operation time is longer;

2) Because the resistive random access memory represents different logic states through the resistance value, most circuits which represent the logic by using the resistance value have the condition of difficult cascade connection, the upper and lower circuits need to read information stored in the resistive random access memory by using small voltage and then send the information to the next circuit by the amplification of the control unit, and the circuits are difficult to cascade connection;

3) The logic function which can be realized by partial logic realization methods is not complete, and an additional CMOS logic gate is needed to realize the operation, so that the circuit cannot be manufactured in the resistive random access memory array, and the process difficulty and the circuit area are increased;

4) Some logic implementation methods cannot store output results, and the output results are cut off and disappear after being output in a voltage mode, and the logic implementation methods sacrifice the storage function of the resistive random access memory and cannot realize effective fusion of storage and calculation;

5) The peripheral control circuit is complex, for example, logic is contained, the circuit form is the same no matter what function the circuit needs to realize, and the circuit completes different logic operations by changing the voltage applied to the resistive random access memory, which is equivalent to increasing the complexity of the peripheral control circuit to replace the simplicity of the operation circuit. The simple logic implementation method of the control unit, such as MPLA, has large hardware overhead;

6) The attenuation problem of output voltage exists in most of the resistance random access memory circuits which output voltage, and the attenuation problem caused by resistance voltage division exists, so that the logic high and low states become indistinguishable after the cascade frequency of the circuits is increased, and the circuit function is influenced;

7) The logic expression mode is not consistent with the CMOS circuit, and the methods for representing the logic by the resistor and the logic by the pulse are different from the method for representing the logic by the traditional CMOS circuit, so that the two circuits are difficult to communicate, a transition circuit needs to be additionally designed, and the design and manufacturing cost is increased.

The resistive random access memory has the advantages of nonvolatility, low power consumption, small volume and the like, the digital circuit research based on the resistive random access memory guides the direction of the next generation digital circuit, but the problems exist in the logic circuit based on the resistive random access memory, so that the existing logic implementation method based on the resistive random access memory cannot implement a large-scale circuit.

The above background disclosure is only for the purpose of assisting understanding of the inventive concept and technical solutions of the present invention, and does not necessarily belong to the prior art of the present patent application, and should not be used for evaluating the novelty and inventive step of the present application in the case that there is no clear evidence that the above content is disclosed before the filing date of the present patent application.

Disclosure of Invention

The parallel logic gate with complete logic function and outputting voltage is provided based on the resistive random access memory, the operation steps of the circuit are reduced to the maximum extent, and meanwhile, the complexity of a peripheral control circuit of a logic operation unit is reduced; and the parallel logic gate is compatible with the traditional CMOS circuit and can conveniently communicate with the traditional CMOS circuit. On the other hand, the invention provides a high-performance multiplier based on the parallel logic gate.

A parallel logic gate based on a resistive random access memory is used for carrying out logic operation on an input voltage signal and outputting a logic operation result expressed by voltage, the parallel logic gate comprises any combination of three logic units of an n input and logic unit, an n input or logic unit and a non-logic unit, the three logic units adopt the resistive random access memory as an input/output device, and n is more than or equal to 2; the parallel logic gate is provided with a left selection end and a right selection end, and the inlet of the left selection end is connected with a divider resistor; the left selection end is used for inputting an excitation voltage, and the right selection end applies a voltage to match a voltage signal of the signal input end and a voltage signal of the signal output end to control state transformation of the resistive random access memory; the positive ends of the resistive random access memories are commonly hung on the same public line between the left selection end and the right selection end to realize logical union, the positive ends of the resistive random access memories are respectively hung on parallel lines between the left selection end and the right selection end to realize logical union, and the negative ends of the resistive random access memories are hung on lines between the left selection end and the right selection end to realize logical union; the parallel logic gate executes setting, inputting, operation and outputting according to the clock sequence to complete logic operation.

The parallel logic gate provided by the technical scheme of the invention can realize any logic function within the limit of input quantity by using the random combination of the logic unit or the logic unit and the non-logic unit realized based on the resistive random access memory. In addition, when the parallel logic gate based on the resistive random access memory performs logic operation, a voltage signal to be operated is directly input from the resistive random access memory serving as an input device, a conversion step is not needed, and the voltage signal is directly output from the resistive random access memory serving as an output device through a control clock, so that the logic operation is completed, and therefore, the operation steps and the time length are greatly reduced. For example, the and (or, not) logic is implemented by inputting a voltage signal to be operated to a resistive random access memory connected according to the and (or, not) logic, and then setting the output device to be in a low-resistance state for outputting and a result in a subsequent clock. In the existing resistive random access memory logic operation based on implication operation, all expressions need to be converted into implication operation to complete logic operation, the operation steps are too long, and the more complex the circuit function, the longer the operation time is. In addition, the peripheral control circuit of the parallel logic gate only needs to provide the voltages of the left selection end and the right selection end and carry out clock control according to the operation steps, thereby greatly reducing the complexity of the peripheral control circuit and the control method.

A multiplier based on a resistive random access memory comprises the parallel logic gate. The parallel logic gate is used for pipeline delay control, a high-performance multiplier with short delay can be realized, and certain optimization is realized in the aspects of circuit area and power consumption.

Drawings

Fig. 1 is a schematic structural diagram of a resistance change memory;

FIG. 2 is an I-V characteristic curve of a resistive random access memory;

FIG. 3-1 is a two-input AND gate based on a resistive random access memory according to an embodiment of the present invention;

fig. 3-2 is a multi-input and gate based on a resistive random access memory according to an embodiment of the present invention;

FIG. 4-1 is a two-input OR gate based on a resistive random access memory according to an embodiment of the present invention;

fig. 4-2 is a multi-input or gate based on a resistive random access memory according to an embodiment of the present invention;

fig. 5 is an not gate based on a resistive random access memory according to an embodiment of the present invention;

fig. 6 is an exclusive or gate based on a resistive random access memory according to an embodiment of the present invention;

FIG. 7 is a one-bit half adder based on a resistive random access memory according to an embodiment of the present invention;

FIG. 8 is a one-bit full adder based on a resistive random access memory according to an embodiment of the present invention;

fig. 9 is a circuit diagram of a4 × 4-bit binary multiplier circuit based on a resistive random access memory according to an embodiment of the present invention;

FIG. 10 is a pipeline delay chain diagram for the multiplier shown in FIG. 9;

FIG. 11 is an area optimized design of the multiplier shown in FIG. 9;

FIG. 12 is another area optimized design of the multiplier shown in FIG. 9;

FIG. 13 is a logic simulation waveform of the two-input AND gate shown in FIG. 3-1;

FIG. 14 is a logic simulation waveform for the two input OR gate shown in FIG. 4-1;

fig. 15 is a logic simulation waveform of the not gate shown in fig. 5.

Detailed Description

The invention is further described with reference to the following figures and detailed description of embodiments.

The embodiment of the invention provides a parallel logic gate based on a resistance change memory, which is used for performing logic operation on an input voltage signal and outputting a logic operation result expressed by voltage. The parallel logic gate comprises any combination of three logic units, namely an n-input logic unit, an n-input logic unit and a non-logic unit, wherein the three logic units adopt a resistive random access memory as an input/output device, and n is more than or equal to 2; the parallel logic gate is provided with a left selection end and a right selection end, and the inlet of the left selection end is connected with a divider resistor; the left selection end is used for inputting an excitation voltage, and the right selection end applies a voltage to match a voltage signal of the signal input end and a voltage signal of the signal output end to control the state transformation of the resistive random access memory; the positive ends of the resistive random access memories are commonly hung on the same public line between the left selection end and the right selection end to realize logical union, the positive ends of the resistive random access memories are respectively hung on parallel lines between the left selection end and the right selection end to realize logical union, and the negative ends of the resistive random access memories are hung on lines between the left selection end and the right selection end to realize logical union; the parallel logic gate executes setting, inputting, operation and outputting according to the clock sequence to complete logic operation.

That is, the parallel logic gate of the present invention may be a two-input (or multiple-input) and gate implemented by using a resistive random access memory, may be a two-input (or multiple-input) or gate implemented by using a resistive random access memory, may be a nor gate implemented by using a resistive random access memory, may be a logic gate in which any two of the and gate, the or gate, and the nor gate are combined, or may be a logic gate in which the and gate, the or gate, and the nor gate are combined. It should be understood that any logic function can be implemented with any combination of the three basic logic gates described above, without regard to voltage droop.

The n input and logic unit needs n resistive random access memories serving as input devices to input n voltage signals to be operated and one resistive random access memory serving as an output device to output n results of the phase comparison of the voltage signals to be operated; and in the n input and logic unit, the negative end of the resistive random access memory is used as a signal input/output end. It should be understood that in AND logic, the number n of input signals ≧ 2.

As shown in fig. 3-1, the two-input and gate implemented by using the resistive random access memory of the present invention needs 3 resistive random access memories M1 to M3 and a divider resistor in total, and has a common line, the positive terminals (one terminal indicated by a black bold line is a positive terminal, and the other terminal is a negative terminal) of the 3 resistive random access memories are all simultaneously connected to the common line, the two ends of the common line are respectively used as a left selection terminal SL and a right selection terminal SR, 2 resistive random access memories M1 and M2 near the left selection terminal side are used as input devices, the negative terminal of the input device is a signal input terminal (for inputting two voltage signals a and B to be operated), the remaining one resistive random access memory M3 near the right selection terminal is used as an Output terminal Output (for inputting the result of the phase of a and B); and a divider resistor R is connected between the left selection end SL and the positive end of the resistive random access memory M1 closest to the left selection end, and the resistance value of the divider resistor R meets the requirement of R _on ＜＜R＜＜R _off ，R _on Represents a resistance value R of the resistive random access memory in a low resistance state _off The resistance value of the resistive random access memory in a high resistance state is shown.

The operation voltages for implementing and logic operation of the two-input and gate are shown in table 1 below:

TABLE 1 operating voltages of two-input AND logic gates

Namely:

step 1, setting: all signal input terminals and signal output terminals are connected to Vp voltage, left selection terminal and right selection terminalThe selected ends are all grounded; wherein, V _p ≥max{V _close ,|V _open |}，V _open Threshold voltage, V, required for the resistive random access memory to be in a high-resistance state _close Threshold voltage required for setting the resistive random access memory to a low resistance state;

step 2, inputting: inputting a voltage signal to be operated from a signal input end, and if the input voltage signal is in a high level, keeping the input resistive random access memory in a high-resistance state; if the input voltage signal is low level, the input resistive random access memory needs to be kept in a low resistance state; meanwhile, the left selection end, the right selection end and the signal output end are all connected with Vp voltage;

and step 3, operation: all signal input ends are grounded, and all signal output ends are connected with-1/2V _set Left end selection 1/2V _set The right selection ends are all suspended; wherein, V _set Denotes a predetermined value greater than V _close Voltage of (d);

and 4, outputting: all signal input ends are grounded, and the left selected end is connected with 1/2V _set And the right selection ends are all suspended, and the operation result is output from the signal output end in a voltage mode.

For the and logic gate, the extension from two inputs to multiple inputs only needs to add more resistive random access memories as input devices on a common line, and the number of the output devices is still one, as shown in fig. 3-2, that is, the output devices are the multiple-input and gate, and the number of the inputs is n. However, the operation steps of the operation are the same as the two inputs, as in table 1, and remain unchanged.

In order to ensure that the and gate can stably output a correct and logic operation result, the and gate has a certain limitation on the number of inputs, and the factor for limiting the number of inputs is analyzed as follows:

when the multi-input AND gate finishes the third step of operation, it needs to be ensured that when all input resistive random access memories are in a high-resistance state, the voltage V at two ends of the resistive random access memory is output _Mout The output resistive random access memory can be set to be in a low resistance state, namely V is needed _Mout ≥V _close ，V _close The threshold voltage is required for the resistive random access memory to be in a low resistance state. While

Namely need to satisfy

Wherein R is _off1 ～R _offn The resistance values of the n input resistive random access memories in the high resistance state are shown, and in this embodiment, it is considered that the parameters of the resistive random access memories used are the same, that is, the resistance values in the high resistance state are all R _off ，V _set Is preset to be greater than V _close The voltage of (c). Due to R _on ＜＜R＜＜R _off In general, R and R _off 、R _on There is a difference of several orders of magnitude between them, so the number n of inputs to and gate can reach tens to hundreds.

Meanwhile, considering that the resistance value of the resistive random access memory in a high resistance state and a low resistance state fluctuates in a certain range,

where x represents the resistance fluctuation coefficient of the resistance change memory, the above equation (2) is changed to

As can be seen from the calculation of equation (3), when the resistance value of the resistance random access memory fluctuates, the and gate can still be maintained to stably output the correct and logic operation result within the input number limit range.

The two-input and gate shown in fig. 1 is subjected to logic simulation, the simulation result is shown in fig. 13, and (a) to (d) in fig. 13 show simulation waveforms when the inputs are 00, 01, 10, and 11, respectively, and it can be seen that the correct and logic operation can be realized.

Compared with the existing circuit for realizing AND operation through Implication (IMPLY) operation, the clock period required by operation is greatly shortened, because all expressions are required to be in an operation mode of q = p IMPLYq in the existing scheme for realizing AND operation through implication operation, and the clock period required by logic is very long along with the increase of the number of inputs.

The n input or logic units need n resistive random access memories serving as input devices to input n voltage signals to be calculated and n resistive random access memories serving as output devices, and the n resistive random access memories serving as the output devices lead out a signal output end together to output n voltage signal phases to be calculated or results; and in the n input or logic unit, the negative end of the resistive random access memory is used as a signal input/output end.

As shown in fig. 4-1, the two-input or gate implemented by using the resistive random access memory needs 4 resistive random access memories M1 to M4, two of which are input devices and the other two of which are output devices; and has two lines and two voltage dividing resistors. The left ends of the two lines are connected together to serve as a left selection end SL, the right ends of the two lines serve as a right selection end SR1 and a right selection end SR2 respectively, the input device is closer to the left selection end, and the output device is closer to the right selection end. The positive ends of two resistive random access memories M1 and M3 serving as input devices are respectively connected to two lines, and the negative ends of the two resistive random access memories are used as signal input ends and used for inputting two voltage signals A and B to be operated; the positive terminals of the two resistive random access memories M2 and M4 as Output devices are also connected to the two lines, respectively, and the negative terminals are connected together to be led out as a signal Output terminal Output to Output the result of the phase or of the signals a and B. And the two divider resistors are respectively connected between the positive terminals and the left selection terminals of the two input devices. For an or gate, when one line is added and a voltage dividing resistor, an input resistive random access memory and an output resistive random access memory are added on each line, the number of input ports is increased by 1. Therefore, an n-input or gate needs n input resistive random access memories and n output resistive random access memories, and has n voltage dividing resistors R1 to Rn and n right selection terminals SR1 to SRn, as shown in fig. 4-2. The operation steps of the or gate to perform the or logic function also require four steps, table 1. Like the AND gate, the OR gate has a limit to the number of inputs in order to stably output the correct OR result.

The two-input or gate shown in fig. 4-1 was logically simulated, and the simulation results are shown in fig. 14, and (a) to (d) in fig. 14 show the simulation waveforms at the

inputs

00, 01, 10, and 11, respectively, and it can be seen that the correct or logical operation can be realized.

The implementation of the non-logic gate is simple, and as shown in fig. 5, only two resistive random access memories and one divider resistor are needed, and the resistive random access memories as input devices are connected in reverse (that is, the negative terminal is connected to the common line, and the positive terminal is used as a signal input terminal) to implement the inversion of the input signal. The operation voltages and steps of the operation are still shown in table 1, and are not described herein again. The logical simulation of the not gate shown in fig. 5 showed the simulation result shown in fig. 15, and (a) and (b) in fig. 15 showed the simulation waveforms when the inputs are 0 and 1, respectively, and it can be seen that the correct non-logical operation can be realized.

The three basic logic gates of the and gate, the or gate and the not gate realized by using the resistive random access memory and the voltage dividing resistor belong to one kind of parallel logic gates, and the parallel logic gate to realize the combinational logic function is combined by adopting at least two of and logic units, or logic units and non-logic units in the three basic logic gates. Such as the exclusive or gate shown in fig. 6, as another exemplary parallel logic gate, the first and second rows of the input array (M1, M2, M4, M5) are respectively and logic, and the first and second rows are in combination or logic; the output arrays (M3, M6) are or logic; the resistive random access memory with the positive terminal as the signal input terminal is not logic. Thus, the circuit is realized

Similarly, the exemplary parallel logic gate shown in fig. 6 also needs four steps of setting, inputting, operating, and outputting for implementing the logic operation, which is the same as the and/or nor gate, and is not described herein again. It can be understood that when one row of the resistive random access memory is added in the input array, one or item is added, and the output resistive random access memory and the divider resistor are correspondingly increased; every time a resistive random access memory is added in one row, an AND factor is added; thus, it can be understood that the parallel logicThe editing gate may implement any desired logic function.

The parallel logic gate is utilized to carry out pipeline design and optimization, and a high-performance multiplier can be realized, and is used for realizing multiplication of m-bit binary number XmXm-1 \8230, X1X0 and n-bit binary number YnYn-1 \8230, Y1Y0, wherein m and n are more than or equal to 2. The array multiplier can complete multiplication operation by using simple shift addition operation, wherein two input AND gates, a half adder unit and a full adder unit are required to be used for cascade connection according to the shift addition principle, a switch is arranged on a path between two adjacent stages, and the on-off of the switch is controlled according to a clock in the operation process, so that when a previous stage enters an output clock, a next stage enters an input clock, and the delay control of the multiplier is realized. The two input AND gates, the half adder and the full adder all belong to the parallel logic gates.

The circuit of a one-bit half adder is shown in fig. 7, and comprises an input array and an output array which are formed by a resistive random access memory, divider resistors R1-R3, a left selection end SL and three right selection ends SR 1-SR 3, wherein two added factors A and B are input by the resistive random access memory of the input array, and the output comprises a result bit S and a carry bit C. For the input array: the input AND operation is realized by forming three rows and two columns of resistive random access memories (M1, M2, M4, M5, M7 and M8), wherein the resistive random access memories in the same row represent an AND relation; the resistance random access memories in different rows represent the OR relationship, and the OR operation of the AND results in each row is realized; the resistive random access memory with the negative end connected with the public line and the positive end as the input end realizes the inversion of the input, so that the logic represented by the input array of the half adder shown in FIG. 7 is

For the output array: the resistance random access memories M3 and M6 are in OR connection, so that the result is that the bit is greater or less>

Carry C = AB, i.e. the logic function implemented by the half adder is: s = a ≧ B, C = AB, the clock and operating voltage which implement the logic function,The operation steps are the same as those of the logic gates in the previous embodiments, and are not described herein again.

A circuit of a one-bit full adder is shown in FIG. 8, and comprises an input array and an output array which are composed of resistive random access memories, divider resistors R1-R7, a left selection end SL and seven right selection ends SR 1-SR 7, wherein the input array has three columns corresponding to three input signals A _i 、B _i 、C _i-1 The output signal including a result bit S _i And carry C _i The logic implemented by the full adder shown in fig. 8 is: s. the _i ＝A _i ⊕B _i ⊕C _i-1 ，C _i ＝A _i B _i +B _i C _i-1 +A _i C _i-1 . The clock, operating voltage and operating steps for implementing the logic function are the same as those of the logic gate in the previous embodiments, and are not described herein again.

And realizing the m x n bit binary multiplier by utilizing the two-input AND gates, the one-bit half adder and the one-bit full adder, wherein m x n two-input AND gates, n one-bit half adders and (m x n-m-n) one-bit full adders are required to be cascaded according to a shift addition principle. The structure and principle of the high-performance multiplier built by using the parallel logic gates are described below by taking m = n =4, i.e. two 4-bit binary number multiplications as an example.

As shown in fig. 9, which is a circuit diagram of a4 × 4-bit binary multiplier according to an embodiment of the present invention, it should be noted that devices (mainly switches, and buffers may be further provided to prevent attenuation of voltage signals) between two adjacent cascaded stages are not shown in the figure. The multiplier shown in fig. 9 implements two four-bit binary numbers X ₃ X ₂ X ₁ X ₀ And Y ₃ Y ₂ Y ₁ Y ₀ The multiplication of (b) requires 16 two-input and gates (denoted by numerals 1 to 16), 4 of the aforementioned one-bit half adders HA1 to HA4, and 8 of the aforementioned one-bit full adders FA1 to FA8 to be cascaded.

The multiplier shown in FIG. 9 completes multiplication logic by starting multiplication from the low order (i.e., "AND"), i.e., Y ₀ And X ₃ X ₂ X ₁ X ₀ And then Y ₁ And X ₃ X ₂ X ₁ X ₀ And, by analogy, 8230, 8230and the like. The result of the and is then shift added, similar to a column-vertical multiplication operation in arithmetic, to complete the multiplication. As shown in FIG. 9, AND gates 1-4 complete Y separately ₀ And X ₀ 、Y ₀ And X ₁ 、Y ₀ And X ₂ 、Y ₀ And X ₃ And gates 5-8 respectively complete Y ₁ And X ₀ 、Y ₁ And X ₁ 、Y ₁ And X ₂ 、Y ₁ And X ₃ And so on. For the result P of the two-factor least significant bit AND ₀ It is directly output as the lowest bit of the multiplication result. The outputs of AND

gates

2 and 5 are inputs to half-adder HA1, the resulting bits of half-adder HA1 being the second to last bit P of the multiplication result ₁ Output, carry into its next stage full adder FA1 (as input signal C in full adder) _i-1 ) (ii) a The outputs of the AND

gates

3 and 6 are used as the input of a full adder FA1 and are simultaneously input to the full adder FA1 together with a carry signal output by a half adder HA1 for operation; after the full adder FA1 completes the operation, its carry is input to the next stage on the left side, and the result bit is input to the next stage below, and the operation is continued. That is, for full and half adders, the output arrow to the left represents a carry bit and the output arrow to the bottom represents a result bit. The final multiplication result is an eight-bit binary number P ₇ P ₆ P ₅ P ₄ P ₃ P ₂ P ₁ P ₀ . For the clocking of the multiplier, the following is explained:

the delay is increased by 2 for each full adder or half adder on the operation path. A total of 20 steps of delay are required to complete the 4 x 4 bit multiplication. The specific operation is described as follows:

in the first clock cycle, performing initial setting operation on all the resistive random access memories in the circuit;

in the second clock cycle, AND

gates

1, 2, 5 are connected separately (X) ₀ ,Y ₀ )、(X ₁ ,Y ₀ )、(X ₀ ,Y ₁ ) Entering the input step;

third clock cycle, AND

gates

1, 2, 5 computeX ₀ Y ₀ 、X ₀ Y ₁ 、X ₁ Y ₀ The output result of (1);

fourth clock cycle, X ₀ Y ₁ 、X ₁ Y ₀ The calculation result of (2) is inputted to the input array of the half adder HA1, and the lowest bit of the multiplication outputs the result X ₀ Y ₀ Output through AND gate 1 (i.e. P) ₀ ) (ii) a At the same time, AND

gates

3 and 6 are respectively connected (X) ₂ ,Y ₀ )、(X ₁ ,Y ₁ ) Entering the input step;

in the fifth clock period, the half adder HA1 enters the operation step, and the AND

gates

3 and 6 enter the operation step;

in the sixth clock cycle, half adder HA1 outputs the result P1 of the second to last bit operation of the multiplication and the carry signal (the carry signal is the arrow on the left of HA1, all the left arrows of all adders are carry signals C, and the downward arrow is the sum result S), the carry signal and X ₂ Y ₀ 、X ₁ Y ₁ The operation results are connected to the input end of the full adder FA1 together. And simultaneously the AND

gates

4, 7 and 9 are respectively connected (X) ₃ ,Y ₀ )、(X ₂ ,Y ₁ ) And (X) ₀ ,Y ₂ ) Entering the input step;

in the seventh clock cycle, the full adder FA1 and the and

gates

4, 7, and 9 enter the operation step. Setting operation is carried out on the half adder HA3 and the full adder FA 2;

in the eighth clock cycle, the carry result of full adder FA1 and the operation result of AND

gates

4 and 7 are input into full adder FA2, and the sum of the local bits of full adder FA1 (i.e. S as mentioned above) _i ) Fed into the half adder HA 3. Half adder HA3 receives X simultaneously ₀ Y ₂ The operation result of (1). In analogy, each time a full adder or half adder is delayed by 2, the corresponding and logic gate needs to calculate the result of and logic in advance and output the result in the form of voltage at the "input step" of the full adder or half adder.

In the work flow of the multiplier circuit shown in fig. 9, the leftmost logic block (including and gate, half adder, and full machine) of each row is idle after the operation is completed, so that it is considered to adopt the pipeline operation to increase the throughput of the circuit.

The operation of shift addition exists in the multiplier circuit shown in fig. 9, and it is reflected on the circuit delay link that the carry output of the leftmost full adder/half adder of each row needs to be sent to the next stage 2 clock cycles later than the carry output of the current bit and the carry output, which results in that the leftmost full adder/half adder needs to occupy two more clocks to store the data of the previous operation after completing the operation. Fig. 10 shows a chain diagram of pipeline operation delay of the multiplier performing more than two times of multiplication operations, numbers in fig. 10 represent delay chains of a first multiplication operation, and numbers in parentheses represent delay chains of a second multiplication operation. In fig. 10, an interval of two clock cycles needs to be added between every two multiplication operations, and since the resistive random access memory has a function of storing data, the circuit can store a carry result in the array for one clock cycle, output the carry result after one clock cycle, and then set for the next multiplication operation. The circuit inputs a group of operation data every 6 clock cycles, the throughput delay of the circuit is 6 clock cycles, and after 4-step operation (setting, inputting, operation and outputting) is completed, all logic blocks except a half adder HA2 and a full adder FA5 need to wait for two clock cycles and then enter the next operation. The timings of the half adder HA2 and the full adder FA5 are set → input → operation → output → wait → output → set. Taking full adder FA5 as an example, full adder FA5 outputs the bit and the result to full adder FA7 at the t-th clock cycle, then waits for one clock, and at the t +2 th clock, full adder FA5 outputs the carry signal to full adder FA8 again, and at the t +3 th clock, full adder FA5 performs the setting operation, and then enters the next multiplication operation cycle. And the arithmetic unit of the input end needs to add a waiting step of two clock cycles after the previous round of operation is completed and then inputs the next group of operation data, so that the circuit can not carry out gapless operation, and the throughput delay of the circuit is 6 clock cycles. After the timing optimization operation shown in fig. 10 is performed on the multiplier shown in fig. 9, 20 clock cycles are required for the first operation result output of one 4 × 4 multiplication operation, and only 6 clock cycles are required for the subsequent multiplication operation result output. For an N x N bit multiplier, 6N-4 delays are needed to complete the first multiplication (N is more than or equal to 2), and similarly, the subsequent multiplication only needs to wait for 6 clock cycles to complete the output, namely the throughput delay of the simple array multiplier based on the resistive random access memory is fixed to 6 clock cycles.

The pipeline delay chain multiplier shown in FIG. 10 has a fast operation speed, and the speed advantage is more obvious than that shown in FIG. 9 as the number of multiplication factor bits is increased. According to FIG. 9,6N-4 delays complete the first multiplication (N ≧ 2), and the second multiplication begins, each time thereafter 6N-4. And the pipelined multiplication is carried out according to the graph 10, 6N-4 delays finish the first multiplication (N is more than or equal to 2), and the subsequent multiplication can finish the output only by waiting for 6 clock cycles. Meanwhile, as the pipelined operation can be adopted, for a multiplier with any number of bits, the throughput delay is only 6 clock cycles, and the small delay has overwhelming advantages compared with other multiplication circuits which are based on the resistive random access memory and can be used for the operation in the memory.

On the other hand, in some environments with strict circuit area limitation, the hardware overhead of the multiplication circuit can be reduced by reasonably arranging the operation timing, and the circuit optimization is carried out in such a way.

Referring to fig. 9, the first optimization is to fold the multiplier circuit shown in fig. 9 left and right, i.e., optimize on "columns" in the multiplier array, with the rows unchanged. As can be seen from the path delay of the multiplier structure of fig. 10, the right circuit of each row is idle after completing the operation, so that some circuits on the left side of the array can be omitted, the operation is retransmitted to the right-most adder for operation, and a4 × 4-bit multiplier structure optimized by column folding is shown in fig. 11, the circuit area and the used devices are reduced, and no half adder is used. In operation, in one multiplication, the AND gate 2 performs X operations at different clock cycles ₁ 、X ₃ And Y ₀ And operation of (first completed X) ₁ And Y ₀ And operation of (2), then X is performed ₃ And Y ₀ And operation of) and gate 4 performs X at different clock cycles respectively ₀ 、X ₂ And Y ₁ The and operation of (2) is based on the principle that the right logic block is no longer idle, thereby reducing the hardware overhead, and the operation speed is the same as that of the multiplier shown in fig. 9.

To implement m × n bit binary multiplication after optimization according to the multiplier optimization principle shown in fig. 11, (2n + 1) foregoing two-input and gates and (2 n-2) foregoing full adders are required. The operational clocking of the column folding optimized multiplier is explained by taking fig. 11 as an example:

the first clock is: setting the AND

gates

1, 2 and 4;

the second clock is as follows: AND gate 1 input operand (X) ₀ ,Y ₀ ) Voltage signal, AND gate 2 input operand (X) ₁ ,Y ₀ ) Voltage signal, AND gate 4 input operand (X) ₀ ,Y ₁ ) A voltage signal;

third clock: setting the AND

gates

3 and 5, and performing operation on the AND

gates

1, 2 and 4;

the fourth clock: the AND gate 1 outputs the operation result P of the lowest order bit of the multiplication operation ₀ Full adder FA1 receives inputs of AND gate 2 and AND gate 4 (as a half adder, carry signal input is 0), and AND gate 5 inputs operation operand (X) ₁ ,Y ₁ ) Voltage signal, and gate 3 input operand (X) ₂ ,Y ₀ ) A voltage signal;

the fifth clock: the full adder FA1 enters an operation step, the AND

gates

3 and 5 enter the operation step, the setting operation is carried out on the full adder FA2, and the setting operation is carried out on the AND

gates

2, 4 and 6;

the sixth clock: full adder FA1 outputs carry and the result P of the second to last bit operation of the multiplication ₁ Full adder FA2 receives the carry output of full adder FA1 and the output of AND gate 5. AND gate 4 input operand (X) ₂ ,Y ₁ ) The voltage signal of (2). AND gate 2 input operand (X) ₃ ,Y ₀ ) And gate 6 inputs the operation operand (X) ₀ ,Y ₂ ) The voltage signal of (a);

the seventh clock: the full adder FA2 enters the operation step, and the full adder FA1 and the full adder FA3 carry out setting operation at the same time; and

gates

4 and 2 enter the operation step; the AND gate 6 also enters the operation step, and sets the AND

gates

3 and 5;

the eighth clock: full adder FA2 outputs carry signal to full adder FA1 and outputs home sum signal to full adder FA3, full adder FA1 receives outputs of AND

gates

2 and 4 at the same time, full adder FA3 receives output of AND gate 6 (used as half adder, carry signal is grounded) at the same time, and gate 5 inputs operation signal (X) ₃ ,Y ₁ ) Voltage signal, and gate 7 input operand (X) ₁ ,Y ₂ ) A voltage signal;

ninth clock: the full adder FA1 and the full adder FA3 enter the operation step, the AND gate 5 and the AND gate 7 enter the operation step, and meanwhile the setting operation is carried out on the full adder FA 4;

the tenth clock: full adder FA1 outputs carry signal to full adder FA2, and outputs home sum signal to full adder FA4, full adder FA3 outputs carry signal to full adder FA4, and outputs the result P of the third bit operation of the multiplication operation ₂ . Full adder FA2 receives the output of and gate 5 (used as half adder, carry signal is connected to 0V) at the same time, full adder FA4 receives the input of and gate 7 at the same time;

eleventh clock: the full adder FA2 and the full adder FA4 enter the operation step, and meanwhile, the setting operation is carried out on the full adder FA 3;

the twelfth clock: full adder FA2 outputs a home sum to full adder FA3, and full adder FA4 outputs a carry signal to full adder FA3 and a home sum signal to full adder FA5. So far, the first row of two full adders completes all the operations of the round. By analogy, the output of 8-bit multiplication results can be completed, so that 4 x 4-bit multiplication can be completed only by 6 full adders and 9 AND gates. The number of the resistive random access memories required after the time sequence optimization is reduced from 284 to 177, and the number of the resistors is reduced from 84 to 51.

Based on the same principle, the second optimization method is to fold the circuit up and down, i.e. the number of rows of the array is reduced, and the number of columns is unchanged. For the multiplier shown in fig. 9, the operation of the third row full add/half add circuit is started from the 12 th clock cycle, and the rightmost half add operation of the first row is completed in the 6 th clock cycle, and the hardware is idle, so that the full add/half add circuit of the third row and the corresponding and gate circuit can be omitted, and the corresponding operation is sent to the idle circuit of the first row for completion, after optimization, the circuit shown in fig. 9 is optimized to the form shown in fig. 12, the adder only needs 2 rows, the rightmost one of each row is a half adder, and the others are full adders. Thus, only 6 full adders, 2 half adders and 12 two-input AND gates are needed to complete a4 x 4 multiplication operation, 284 resistive random access memories are needed to be reduced to 204 resistive random access memories, and 84 resistive random access memories are needed to be reduced to 60 resistive random access memories. The binary multiplier with m x n bits optimized according to the principle needs 3m of the two-input AND gates, 2m-2 full adders and 2 half adders.

In addition, the multiplier circuit shown in fig. 9 may also perform the row folding and column folding optimization simultaneously according to the two hardware optimization principles, but an additional resistive random access memory is required to be added to temporarily store the intermediate operation result, and the time sequence complexity is also increased. In summary, for an m × n bit multiplier of the present invention, the area of the circuit can be reduced by selecting row folding or column folding by reasonably arranging the timing of the circuit operation; the operation speed of the multiplier can be improved through pipeline delay control, and the throughput of the circuit is increased.

In the multiplier provided above, a switch and a buffer are arranged on a path between every two cascaded stages, and the switch is controlled by a peripheral circuit and is closed only when the upper stage finishes operation and outputs an operation result, so as to output the operation result to the lower stage. The arrangement of the buffer can prevent the attenuation of the voltage and ensure that the multiplier can finally stably output the result.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several equivalent substitutions or obvious modifications can be made without departing from the spirit of the invention, and all the properties or uses are considered to be within the scope of the invention.

Claims

1. A parallel logic gate based on a resistance change memory for performing a logic operation on an input voltage signal and outputting a logic operation result expressed in voltage, characterized in that: the random combination of the logical unit or the logical unit and the non-logical unit realized on the basis of the resistive random access memory can realize random logical functions within the limit of the input quantity without considering voltage attenuation;

the parallel logic gate comprises any combination of three logic units, namely an n-input logic unit, an n-input logic unit and a non-logic unit, wherein the three logic units adopt a resistive random access memory as an input/output device, and n is more than or equal to 2; the parallel logic gate is provided with a left selection end and a right selection end, and the inlet of the left selection end is connected with a divider resistor; the left selection end is used for inputting an excitation voltage, and the right selection end applies a voltage to match a voltage signal of the signal input end and a voltage signal of the signal output end to control state transformation of the resistive random access memory;

the positive ends of the resistive random access memories are commonly hung on the same public line between the left selection end and the right selection end to realize logical union, the positive ends of the resistive random access memories are respectively hung on parallel lines between the left selection end and the right selection end to realize logical union, and the negative ends of the resistive random access memories are hung on lines between the left selection end and the right selection end to realize logical union;

the parallel logic gate executes setting, inputting, operation and outputting according to the clock sequence to complete logic operation.

2. The resistive-switching-memory-based parallel logic gate according to claim 1, wherein: the n input and logic unit needs n resistive random access memories serving as input devices to input n voltage signals to be operated and one resistive random access memory serving as an output device to output n results of the phase comparison of the voltage signals to be operated; and in the n input and logic unit, the negative end of the resistive random access memory is used as a signal input/output end.

3. The resistive-switching-memory-based parallel logic gate of claim 2, wherein: the implementation mode of the n input and logic unit is as follows: providing a public line, and hanging the positive ends of the n +1 resistive random access memories on the public line in parallel, wherein two ends of the public line are respectively used as the left selection end and the right selection end; the n resistive random access memories close to the left selection end serve as input devices, the negative end of each input device serves as n signal input ends, the remaining resistive random access memory close to the right selection end serves as an output device, and the negative end of each output device serves as a signal output end.

4. The resistive-switching-memory-based parallel logic gate according to claim 1, wherein: the n input or logic units need n resistive random access memories serving as input devices to input n voltage signals to be calculated and n resistive random access memories serving as output devices, and the n resistive random access memories serving as the output devices lead out a signal output end together to output n voltage signal phases to be calculated or results; in the n-input or logic unit, the negative terminal of the resistive random access memory serves as a signal input/output terminal.

5. The resistive-switching-memory-based parallel logic gate according to claim 4, wherein: the implementation mode of the n input or logic unit is as follows: providing n lines, wherein one ends of the n lines are connected together to serve as the left selection end, and the other ends of the n lines serve as a right selection end respectively; the method comprises the following steps that n resistive random access memories are used as input devices, positive ends of the n resistive random access memories are respectively hung on one sides, close to left selection ends, of the n lines, and negative ends of the input devices are used as n signal input ends; and the other n resistive random access memories are used as output devices, positive terminals of the other n resistive random access memories are respectively hung on one side of the n lines close to the right selection end, and negative terminals of the output devices are connected together to be used as signal output terminals.

6. The resistive-switching-memory-based parallel logic gate according to claim 1, wherein: the resistive random access memory serving as an input device in the non-logic unit is reversely connected, and the positive end of the resistive random access memory serves as a signal input end; and the negative end of the resistive random access memory of the output device is used as a signal output end.

7. The resistive-switching-memory-based parallel logic gate according to claim 6, wherein: the implementation mode of the non-logic unit is as follows: providing a line, wherein two ends of the line are the left selection end and the right selection end respectively; a resistive random access memory is used as an input device, the negative end of the resistive random access memory is connected to one side, close to the left selection end, of the line in a hanging mode, and the positive end of the resistive random access memory is used as a signal input end; and the other resistive random access memory is used as an output device, the positive end of the other resistive random access memory is hung on one side of the line close to the right selection end, and the negative end of the other resistive random access memory is used as a signal output end.

8. The resistive-switching-memory-based parallel logic gate according to claim 1, wherein: the four steps of the parallel logic gate for completing the logic operation are respectively

Step 1, setting: all signal input ends and signal output ends are connected with Vp voltage, and the left selection end and the right selection end are grounded; wherein, V _p ≥max{V _close ,|V _open |}，V _open Threshold voltage, V, required for the resistive random access memory to be in a high-resistance state _close Threshold voltage required for setting the resistive random access memory to a low resistance state;

and 4, outputting: all signal input ends are grounded, and the left selected end is connected with 1/2V _set The right selection end is suspendedAnd outputting the operation result from the signal output end in a voltage mode.

9. The resistive-switching-memory-based parallel logic gate according to claim 1, wherein: the resistance value of the divider resistor is R, and R is satisfied _on ＜＜R＜＜R _off ，R _on Represents a resistance value R of the resistive random access memory in a low resistance state _off The resistance value of the resistive random access memory in a high resistance state is shown.

10. A multiplier based on a resistive random access memory is characterized in that: comprising a parallel logic gate as claimed in any one of claims 1 to 9.

11. The resistive-switching-memory-based multiplier of claim 10, wherein: is used for realizing multiplication of m-bit binary number XmXm-1 \8230, X1X0 and n-bit binary number YnYn-1 \8230, and Y1Y0, wherein m and n are more than or equal to 2; the implementation mode of the multiplier is as follows: two input AND gates and a one-bit adder are used for cascade connection according to a shift addition principle, a switch is arranged on a path between two adjacent stages, and the switch is controlled to be opened and closed according to a clock in an operation process, so that when a previous stage enters an output clock, a next stage enters an input clock, and delay control of a multiplier is realized.

12. The resistive-switching-memory-based multiplier of claim 11, wherein: the two-input AND gate is realized by adopting a two-input AND logic unit and a divider resistor and is provided with a left selection end and a right selection end, and the inlet of the left selection end is connected with the divider resistor; the left selection end is used for inputting an excitation voltage, and the right selection end applies a voltage to match an AND gate input signal and an AND gate output signal to control state transformation of the resistive random access memory; the two input and logic units adopt a resistive random access memory as an input/output device.

13. The resistive-switching-memory-based multiplier of claim 12, wherein: the two-input AND gate is realized by adopting 3 resistive random access memories, the positive ends of the 3 resistive random access memories are parallelly connected to a common line, and the two ends of the common line are respectively used as a left selection end and a right selection end; two resistive random access memories close to one side of the left selection end are used as input devices, and the negative ends of the two input devices are two signal input ends; the other resistive random access memory close to the right selection end is used as an output device, and the negative end of the resistive random access memory is used as a signal output end; and a voltage dividing resistor is connected between the left selection end and the positive end of the input device close to the left selection end.

14. The resistive-switching-memory-based multiplier of claim 11, wherein: the one-bit adder used includes a one-bit half adder and a one-bit full adder, or only a one-bit full adder;

the single-bit half adder is formed by logically combining three logic units, namely an n-input and logic unit, an n-input or logic unit and a non-logic unit which are formed by a resistive random access memory according to a half adder, and the single-bit full adder is formed by logically combining the three logic units according to a full adder.

15. The resistive-switching-memory-based multiplier of claim 14, wherein: the one-bit half adder and the one-bit full adder each have the following features:

a resistive random access memory is adopted as an input/output device; the device is provided with a left selection end and a right selection end, and a voltage division resistor is connected to an inlet of the left selection end; the left selection end is used for inputting an excitation voltage, and the right selection end applies a voltage to match a voltage signal of the signal input end and a voltage signal of the signal output end to control state transformation of the resistive random access memory.

16. The resistive-switching-memory-based multiplier of claim 14, wherein: the two-input AND gate, the one-bit half adder and the one-bit full adder execute setting, inputting, calculating and outputting according to a clock sequence to complete respective logic operation functions.

17. The resistive-switching-memory-based multiplier of claim 16, wherein: the two-input AND gate, the one-bit half adder and the one-bit full adder complete respective logic operation functions in four steps as follows

step 2, inputting: inputting a voltage signal to be operated from a signal input end, and if the input voltage signal is in a high level, keeping the input resistive random access memory in a high-resistance state; if the input voltage signal is low level, the input resistive random access memory needs to keep a low-resistance state; meanwhile, the left selection end, the right selection end and the signal output end are all connected with Vp voltage;

18. The resistive-switching-memory-based multiplier of claim 14, wherein: the array multiplier is formed by cascading m x n two-input AND gates, n one-bit half adders and (m x n-m-n) one-bit full adders according to a shift addition principle; the clock control is carried out through a peripheral circuit, the switch between two adjacent stages is closed at the output of the previous stage and the input of the next stage, and the pipeline delay control of the shift addition of the multiplier is carried out.

19. The resistive-switching-memory-based multiplier of claim 14, wherein: is an array multiplier formed by cascading (2n + 1) two-input AND gates and (2 n-2) one-bit full adders according to the principle of shift addition; the peripheral circuit is used for clock control, the switches between two adjacent stages are closed when the switches are output at the previous stage and input at the next stage, and part of the two-input AND gates are subjected to AND operation for multiple times at different clocks.

20. The resistive-switching-memory-based multiplier of claim 14, wherein: the array multiplier is formed by cascading 3m two-input AND gates, (2 m-2) one-bit full adders and 2 one-bit half adders according to the shift addition principle; the peripheral circuit is used for clock control, the switches between two adjacent stages are closed when the switches are output at the previous stage and input at the next stage, and part of the two-input AND gates are subjected to AND operation for multiple times at different clocks.