CN111061454B - Logic implementation method based on bipolar memristor - Google Patents

Logic implementation method based on bipolar memristor Download PDF

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CN111061454B
CN111061454B CN201911306380.0A CN201911306380A CN111061454B CN 111061454 B CN111061454 B CN 111061454B CN 201911306380 A CN201911306380 A CN 201911306380A CN 111061454 B CN111061454 B CN 111061454B
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杨玉超
袁锐
马铭远
徐丽莹
汪玉
黄如
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Peking University
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G—PHYSICS
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    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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Abstract

The invention discloses a logic implementation method based on a bipolar memristor, wherein one input is defined as an initial resistance state of the bipolar memristor, the other input is defined as voltage, the output is defined as a final resistance state of a device, 16 Boolean logic functions are completed by one device within one-step reading and two-step writing operations, and the logic implementation method comprises the step of completing the XOR logic which is difficult to implement by other logic operation modes only by one device by one-time reading and writing. The method does not need initialization, can directly carry out logic cascade, and is more efficient than the existing logic method. Meanwhile, the invention also provides a realization scheme of the one-bit full adder and the two-bit multiplier based on the method, compared with other methods, the method has the advantages of fewer used devices and fewer steps, thereby being more efficient. Therefore, the method can be used as a general logic method and has great development prospect.

Description

Logic implementation method based on bipolar memristor
Technical Field
The invention belongs to the technical field of novel calculation, and particularly relates to a logic implementation method based on a bipolar memristor.
Background
Integrated circuits have evolved at a high rate for half a century according to moore's law, but with the reduction in device size and the gradual approach to physical limits, moore's law has been difficult to maintain. Simply scaling CMOS devices down in size is difficult to continue to improve performance significantly, and new materials, devices, and architectures are needed to meet the needs of the data explosion era. Today's computers are based on the von neumann architecture, and the separation of storage and operation of the von neumann architecture severely limits the performance of the computers, which is the so-called von neumann bottleneck, and a new architecture integrating storage and operation is expected to break through the bottleneck.
In recent years, memristors have gained widespread attention and found potential applications in non-volatile memory and memory computing due to their rich dynamics and good performance. It is a strong candidate for non-volatile logic or memory computation due to its high speed, high scalability, non-volatility, and low power consumption. The conventional logic implementation method based on the memristor is mainly divided into two types, one type is that a voltage signal is used as two inputs, and a resistance value is used as an output, and the method has the main problems that the required operation steps are large, the logic cascade cannot be directly carried out, the output needs to be converted into the voltage signal through AD and then used as the input again, and the initialization is usually needed, so that the steps required for implementing the logic operation are greatly increased; the other type is that the input and the output are both expressed in resistance values, which is favorable for logic cascade connection, but the number of required devices is large because the input and the output are both expressed in resistance values. Therefore, there is no logic implementation method that can implement all logic operations in a small number of steps with a small number of devices and can directly cascade logic.
Disclosure of Invention
In order to overcome the defects of the existing logic operation method, the invention aims to provide an efficient logic implementation method based on a bipolar logic device, which can realize all 16 Boolean logic functions within one-step reading operation and two-step writing operation by using a single bipolar device and can directly carry out logic cascade. The invention also provides a high-efficiency implementation method of the 1-bit full adder and the 2-bit multiplier based on the method.
Bipolar memristors typically have two electrode ports: a top electrode and a bottom electrode. The resistance change process of the bipolar memristor is related to the voltage polarity, and the resistance change process is carried out on the top electrode T1A Vset voltage is applied to change the device from a high-resistance state to a low-resistance state; at the bottom electrode T2A Vreset voltage is applied to cause the device to transition from a low resistance state to a high resistance state. Defining the high voltage as logic '1' and the low voltage as logic '0'; the high resistance state of the resistance is defined as logic '0' and the low resistance state is defined as logic '1'.
The invention proposes a new logic input and output definition: one input is defined as the initial resistance state of the bipolar memristor, the other input is defined as the voltage, and the output is defined as the final resistance state of the device.
The invention provides a method for realizing 16 Boolean logic functions based on a single bipolar memristor, which comprises the following steps:
(1) will T2Terminal voltage as input p, device initial state as input q, end state resistance as output, T1The end is arranged at a high voltage Vset, and the IMP logic function is realized in one step;
(2) will T2Terminal voltage as input p, device initial state as input q, end state resistance as output, T1The end is set to 0 voltage, and the RNIMP logic function is realized in one step;
(3) taking the initial state of the device as the input p, T2Terminal voltage as input q, end state resistance as output, T1The end is arranged at a high voltage Vset, and the RIMP logic function is realized in one step;
(4) taking the initial state of the device as the input p, T2Terminal voltage as input q, end state resistance as output, T1The end is placed at 0 voltage, and the NIMP logic function is realized in one step;
(5) taking the initial state of the device as the input p, T1Terminal voltage as input q, end state resistance as output, T2The end is placed at 0 voltage, and the OR logic function is realized in one step;
(6) taking the initial state of the device as the input p, T1Terminal voltage as input q, end state resistance as output, T2The end is arranged at a high voltage Vreset, AND the AND logic function is realized in one step;
(7) taking the initial state of the device as input p, reading the initial resistance state, and if the initial resistance state is a high resistance state '0', another input voltage q is from T1End input, T2Putting the mixture at 0 voltage; if it is in the high impedance state "1", the other input voltage q is from T2End input, T1Putting the mixture at 0 voltage; taking the last-state resistor as output, and completing an XOR logic function by one-step reading and one-step writing operation;
(8) taking the initial state of the device as input p, reading the initial resistance state, and if the initial resistance state is a high resistance state '0', outputting the other oneThe input voltage q is from T1End input, T2Put at high voltage Vrset; if it is in the high impedance state "1", the other input voltage q is from T2End input, T1Placed at a high voltage Vset; the last-state resistor is used as output, and the XNOR logic function is completed by one-step reading and one-step writing operation;
(9) defining the final resistance as the output, T1Is set at a high voltage Vset, T2Putting the voltage at 0, and realizing the logic TRUE function in one step;
(10) defining the final resistance as the output, T2Put at a high voltage Vreset, T1Putting the voltage at 0, and realizing logic FALSE function in one step;
(11) taking the initial state of the device as an input P, reading the value of the initial state, then placing the initial state into an opposite resistance state, and completing a non-P logic function by writing in one step and reading in one step;
(12) taking the initial state of the device as an input q, reading the value of the initial state, then placing the initial state into an opposite resistance state, and writing in one step and reading in one step to complete a non-q logic function;
(13) will T2Put at a high voltage Vreset, T1Put at 0 voltage and then T1As input p, T2Putting the voltage at 0, and realizing p logic function by two-step writing operation;
(14) will T2Put at a high voltage Vreset, T1Put at 0 voltage and then T1As input q, T2Putting the voltage to 0, and realizing a q logic function by two-step writing operation;
(15) the device is operated according to the operation in the step (5) to realize an OR logic function, then the resistance state of the device is read out, the device is placed in an opposite resistance state, and the NOR logic function is completed by one-step reading and two-step writing;
(16) AND (4) realizing an AND logic function by the device according to the operation in the step (6), reading the resistance state of the device, putting the device in the opposite resistance state, AND completing the NAND logic function by one-step reading AND two-step writing.
The invention also provides a logic cascade mode:
the output of the previous logic operation is stored in the form of resistance value, and the logic cascade is naturally realized by taking the value as an initial resistance state input p, taking voltage as another input q and taking a final state resistor as an output.
The invention also provides a method for realizing the one-bit full adder based on the logic realization mode, which needs three devices in total, realizes six steps, defines the input as A (addend), B (added number) and Ci (carry from low bit), and the output as C0(carry to high bit), S (sum of local bits), and CoAnd S are respectively stored in the device 1 and the device 2, and the specific operation flow is as follows:
(1) the first step is to write data a in the devices 1, 2, 3;
(2) secondly, reading the resistance values of the devices 1 and 2;
(3) the third step is that the devices 1, 2 are operated according to the read resistance as selection signal
Figure GDA0003309648720000031
In operation, the device 3 performs AB operation;
(4) the fourth step is to read out the resistance value of the device 2;
(5) fifth step device 1 does
Figure GDA0003309648720000032
Operation, device 2 does
Figure GDA0003309648720000033
In operation, the resistance of the device 3 is read;
(6) sixth step device 1 does
Figure GDA0003309648720000034
And (5) operating.
The invention also provides a two-bit multiplier implementation method based on the logic implementation mode, which needs five devices in total and is implemented in six steps, and the input is defined as A1A0、B1B0Output P4P3P2P1In order to store the calculation results in the devices 1, 2, 3 and 4, the specific operation flow is as follows:
(1) the first step is writing A in the devices 1, 4, 50；
(2) Second step device 1 as0B0Operation, write B in device 30Device for measuring the length of a pipeItem 4 is denoted as A0B0Operating;
(3) third step device 1 does0B0B1Operation, write B in device 21 Device 5 is referred to as A0B1Operating;
(4) fourth step device 1 is made as0B0A1B1Operation, device 2 is A1B1Device 3 as A1B0Operating;
(5) fifthly, reading the resistance values of the devices 1, 2, 3 and 5;
(6) sixth step device 2 does
Figure GDA0003309648720000035
Device 3 does
Figure GDA0003309648720000036
And (5) operating.
The invention provides a novel logic implementation method based on a bipolar memristor, which can use one device to complete 16 Boolean logics in less than one-step reading and two-step writing operations, and can also be implemented by using one device for one-time reading operation and one-time writing operation for exclusive OR logics which are difficult to implement in other logic operation modes. The method does not need initialization, can directly carry out logic cascade, and is more efficient compared with the existing logic method. Meanwhile, the invention also provides a realization scheme of the one-bit full adder and the two-bit multiplier based on the method, compared with other methods, the method has the advantages of minimum used devices and steps, thereby being more efficient. Therefore, the method can be used as a general logic method and has great development prospect.
Drawings
Fig. 1 is a schematic structural diagram of a bipolar memristor used in a logic implementation method of the present invention.
FIG. 2 is a diagram of experimental results of basic logic operations of the logic implementation method based on the bipolar memristor of the present invention, wherein: (a) to realize the result of AND logic experiment, (b) to realize the result of OR logic experiment. (c) To realize the XOR logic experimental result chart.
FIG. 3 is a schematic structural diagram of a one-bit full adder constructed by the logic implementation method based on the bipolar memristor.
FIG. 4 is a timing diagram of a time pulse required by a one-bit full adder to calculate a typical input (1+1+1) according to the logic implementation method of the bipolar memristor.
FIG. 5 is a schematic structural diagram of a two-bit multiplier constructed by the logic implementation method based on the bipolar memristor.
FIG. 6 is a timing diagram of a two-bit multiplier implemented by the logic implementation method based on bipolar memristors to calculate the time pulse required by a typical input (11x 10).
Detailed Description
To more clearly illustrate the objects, technical solutions and advantages of the present invention, the present invention will be described in further detail by way of specific embodiments with reference to the accompanying drawings. The specific embodiments described herein are merely illustrative of the invention and are not intended to be limiting.
The invention provides a logic implementation mode based on a bipolar memristor, which can complete 16 Boolean logics in one-step reading and two-step writing operations by using a single device. For the XOR logic function which is difficult to realize efficiently by the existing logic implementation scheme, the method can also be completed by one-step reading and one-step writing operation of a single device, and the scheme does not need any initialization and can directly carry out logic cascade.
The invention defines the high voltage as logic '1' and the low voltage as logic '0'; the resistance high resistance state is logic '0' and the low resistance state is logic '1'. The invention provides a new input and output definition mode, wherein one input is defined as the initial resistance state of a device, the other input is defined as the voltage, and the output is defined as the final resistance state of the device.
Example one
FIG. 1 shows a bipolar memristor, T, used in the logic implementation method of the present invention1Is a top electrode, T2Is a bottom electrode with two resistance states that are stably transformed. When the AND logic function is realized, the initial state of the device is used as the input p, T1Terminal voltage as input q, end state resistance as output, T2Is terminated at a high voltageVreset, as long as one of p and q is "0", the output end-state resistance is "0". The experimental results are shown in FIG. 2 (a); when the OR logic function is realized, the initial state of the device is used as the input p, T1Terminal voltage as input q, end state resistance as output, T2The end is set at 0 voltage, as long as one of p and q is not 0, the output end state resistance is 1, and the experimental result is shown in fig. 2 (b); when the XOR logic is realized, the initial state of the device is taken as an input p, the initial resistance state is read, and if the initial resistance state is a high resistance state '0', the other input voltage q is changed from T1End input, T2Putting the mixture at 0 voltage; if the initial resistance state is a high resistance state "1", another input voltage q is driven from T2End input, T1When p and q are the same, the output end state resistance is "0", and when p and q are different, the output end state resistance is "1", and the experimental result is shown in fig. 2 (c).
Example two
The one-bit full adder is realized based on the logic realization method of the invention, and the realization scheme of the one-bit full adder only needs 3 devices and can be operated in six steps. The full adder structure is shown in fig. 3, wherein the top electrodes of 3 devices are respectively connected to SL (1), SL (2) and SL (3), and the bottom electrodes are respectively connected to BL (1), BL (2) and BL (3). For a one-bit full adder, the 3 input variables are the addend A, the summand B, and the carry C from the lower bits, respectivelyiThe 2 output variables are respectively the carry bit C to the home bit and S and the high bitoThe logical expression is as follows:
Figure GDA0003309648720000051
Figure GDA0003309648720000052
the operation method is that the first step is to write data A in the devices 1, 2 and 3; secondly, reading the resistance values of the devices 1 and 2; the third step is that the devices 1, 2 are operated according to the read resistance as selection signal
Figure GDA0003309648720000053
In operation, the device 3 performs AB operation; the fourth step is to read out the resistance value of the device 2; fifth step device 1 does
Figure GDA0003309648720000054
Operation, device 2 does
Figure GDA0003309648720000055
In operation, the resistance of the device 3 is read; sixth step device 1 does
Figure GDA0003309648720000056
In operation, the resistances of the devices 1, 2 are the calculated results C, respectivelyoThe specific process is shown in Table 1.
TABLE 1
Figure GDA0003309648720000057
Next, we take a representative input (1+1+1) as an example, and give a specific pulse operation sequence as shown in fig. 4.
EXAMPLE III
The two-bit multiplier is realized based on the logic realization method of the invention, and the realization scheme of the two-bit multiplier only needs five devices and six steps of operation. The two-bit multiplier structure is shown in fig. 5, in which the top electrodes of 5 devices are connected to SL (1), SL (2), SL (3), SL (4), and SL (5), respectively, and the bottom electrodes are connected to BL (1), BL (2), BL (3), BL (4), and BL (5), respectively. Defining the input of the two-bit multiplier as A1A0、B1B0Output is P4P3P2P1The results of the calculations are stored in the devices 1, 2, 3, 4. The two-bit multiplier logic expression is as follows:
P1＝A0B0 (3)
Figure GDA0003309648720000061
Figure GDA0003309648720000062
P4＝A1A0B1B0 (6)
the method of operation is the first step of writing A in the devices 1, 4, 50(ii) a Second step device 1 as0B0Operation, write B in device 30 Device 4 as A0B0Operating; third step device 1 does0B0B1Operation, write B in device 21 Device 5 is referred to as A0B1Operating; fourth step device 1 is made as0B0A1B1Operation, device 2 is A1B1Operation, device 3 is A1B0Operating; fifthly, reading the resistance values of the devices 1, 2, 3 and 5; sixth step device 2 does
Figure GDA0003309648720000063
Operation, device 3 does
Figure GDA0003309648720000064
And (5) operating. The specific procedure is shown in Table 2.
TABLE 2
Figure GDA0003309648720000065
Next, we take a representative input (11x10) as an example, and give a specific pulse operation sequence as shown in fig. 6.
The implementation method based on the bipolar memristor provides a new input and output definition, can use one device to complete the XOR logic function which is difficult to be efficiently realized by the existing logic implementation scheme in one-step reading and one-step writing operation, can complete 16 Boolean logic functions in less than one-step reading and two-step writing operation, and can directly carry out logic cascade without any initialization. In addition, the invention provides an efficient implementation scheme of the one-bit full adder and the two-bit multiplier based on the logic implementation method, promotes the development of a memory fusion technology based on the memristor, and has very wide application prospect.
The above embodiments are only intended to illustrate the technical solution of the present invention and not to limit the same, and a person skilled in the art can modify the technical solution of the present invention or substitute the same without departing from the spirit and scope of the present invention, and the scope of the present invention should be determined by the claims.

Claims (4)

1. A logic implementation method based on a bipolar memristor, the bipolar memristor having two electrode ports: top electrode T1And a bottom electrode T2At the top electrode T1A Vset voltage is applied to cause the device to transition from a high-resistance state to a low-resistance state; at the bottom electrode T2Applying a Vreset voltage to enable the device to be converted from a low-resistance state to a high-resistance state; the method is characterized in that the high voltage is defined as logic '1', and the low voltage is defined as logic '0'; defining the high resistance state of the resistance value as logic '0' and the low resistance state as logic '1'; the logic inputs and outputs are defined as follows: one input is defined as the initial resistance state of the bipolar memristor, the other input is defined as the voltage, and the output is defined as the final resistance state of the bipolar memristor; based on the definition, 16 Boolean logic functions are realized by using a single bipolar memristor in one-step reading operation and two-step writing operation, and the operation is as follows:
1) will T2Terminal voltage as input p, initial resistance state as input q, final resistance as output, T1The end is arranged at a high voltage Vset, and the IMP logic function is realized in one step;
2) will T2Terminal voltage as input p, initial resistance state as input q, final resistance as output, T1The end is set to 0 voltage, and the RNIMP logic function is realized in one step;
3) taking the initial resistance state of the device as input p, T2Terminal voltage as input q, end state resistance as output, T1The end is arranged at a high voltage Vset, and the RIMP logic function is realized in one step;
4) taking the initial resistance state of the device as input p, T2Terminal voltage as input q, end state resistance as output, T1End-onAt 0 voltage, the NIMP logic function is realized in one step;
5) taking the initial resistance state of the device as input p, T1Terminal voltage as input q, end state resistance as output, T2The end is placed at 0 voltage, and the OR logic function is realized in one step;
6) taking the initial resistance state of the device as input p, T1Terminal voltage as input q, end state resistance as output, T2The end is arranged at a high voltage Vreset, AND the AND logic function is realized in one step;
7) taking the initial resistance state of the device as an input p, reading the initial resistance state, and if the initial resistance state is a high resistance state 0, then another input voltage q is from T1End input, T2Putting the mixture at 0 voltage; if it is in the high impedance state "1", the other input voltage q is from T2End input, T1Putting the mixture at 0 voltage; taking the last-state resistor as output, and completing an XOR logic function by one-step reading and one-step writing operation;
8) taking the initial resistance state of the device as an input p, reading the initial resistance state, and if the initial resistance state is a high resistance state 0, then another input voltage q is from T1End input, T2Put at high voltage Vreset; if it is in the high impedance state "1", the other input voltage q is from T2End input, T1Placed at a high voltage Vset; the last-state resistor is used as output, and the XNOR logic function is completed by one-step reading and one-step writing operation;
9) defining the final resistance as the output, T1Is set at a high voltage Vset, T2Putting the voltage at 0, and realizing the logic TRUE function in one step;
10) defining the final resistance as the output, T2Put at a high voltage Vreset, T1Putting the voltage at 0, and realizing logic FALSE function in one step;
11) taking the initial resistance state of the device as an input P, reading the value of the initial resistance state, then placing the initial resistance state in an opposite resistance state, and completing a non-P logic function by one-step writing and one-step reading;
12) taking the initial resistance state of the device as an input q, reading the value of the initial resistance state, then placing the device in the opposite resistance state, and completing a non-q logic function by one-step writing and one-step reading;
13) will T2Put at a high voltage Vreset, T1Put at 0 voltage and then T1As input p, T2Putting the voltage at 0, and realizing p logic function by two-step writing operation;
14) will T2Put at a high voltage Vreset, T1Put at 0 voltage and then T1As input q, T2Putting the voltage to 0, and realizing a q logic function by two-step writing operation;
15) the device is operated according to the operation of 5) to realize an OR logic function, then the resistance state of the device is read out, the device is placed in an opposite resistance state, and the NOR logic function is completed by one-step reading and two-step writing;
16) AND (3) realizing the AND logic function by the device according to the operation of 6), reading the resistance state of the device, putting the device in the opposite resistance state, AND completing the NAND logic function by one-step reading AND two-step writing.
2. A logic cascade method is characterized in that according to the logic implementation method based on the bipolar memristor, the output of the previous step of logic operation is stored in the form of resistance, the value is used as an initial resistance state input p, the voltage is used as another input q, and the final state resistor is used as the output, so that the logic cascade is directly implemented.
3. An implementation method of a one-bit full adder, based on the logic implementation method of claim 1, by three bipolar memristors: device 1, device 2 and device 3, and six-step operation is realized, and three input variables are specifically defined as an addend A, an added number B and a carry C from a low bitiThe two output variables are respectively the carry bit C to the high bit and the carry bit SoCalculating the result CoAnd S are stored in devices 1 and 2, respectively, and the logic expressions are as follows:
Figure FDA0003428384170000021
Figure FDA0003428384170000022
the operation flow is as follows:
the first step is to write data a in the devices 1, 2, 3;
secondly, reading the resistance values of the devices 1 and 2;
the third step is that the devices 1, 2 are operated according to the read resistance as selection signal
Figure FDA0003428384170000023
In operation, the device 3 performs AB operation;
the fourth step is to read out the resistance value of the device 2;
fifth step device 1 does
Figure FDA0003428384170000024
Operation, device 2 does
Figure FDA0003428384170000025
In operation, the resistance of the device 3 is read;
sixth step device 1 does
Figure FDA0003428384170000026
And (5) operating.
4. An implementation method of a two-bit multiplier is based on the logic implementation method of claim 1, and the two-bit multiplier is implemented by five bipolar memristors: the device 1-5 is realized by six-step operation, and two-bit numbers of input are specifically defined as A1A0、B1B0Wherein A is1And B1Representing the upper two digits, A0And B0Low order, output P representing a two-digit number4P3P2P1The calculation results are stored in the devices 1, 2, 3 and 4, and the logic expressions are as follows:
P1＝A0B0 (3)
Figure FDA0003428384170000031
Figure FDA0003428384170000032
P4＝A1A0B1B0 (6)
the operation flow is as follows:
the first step is writing A in the devices 1, 4, 50；
Second step device 1 as0B0Operation, write B in device 30Device 4 as A0B0Operating;
third step device 1 does0B0B1Operation, write B in device 21Device 5 is referred to as A0B1Operating;
fourth step device 1 is made as0B0A1B1Operation, device 2 is A1B1Device 3 as A1B0Operating;
fifthly, reading the resistance values of the devices 1, 2, 3 and 5;
sixth step device 2 does
Figure FDA0003428384170000033
Device 3 does
Figure FDA0003428384170000034
And (5) operating.
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