CN109885934B - Multi-junction solar cell sub-junction analysis method and device and electronic equipment - Google Patents
Multi-junction solar cell sub-junction analysis method and device and electronic equipment Download PDFInfo
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Abstract
The invention provides a multi-junction solar cell sub-junction analysis method, a multi-junction solar cell sub-junction analysis device and electronic equipment, wherein the method comprises the following steps: building a multi-junction solar cell model; the multi-junction solar cell model includes at least one sub-junction; respectively carrying out simulation treatment on each sub-junction of the multi-junction solar cell model by using the preset minority carrier lifetime and the preset defect parameters to obtain a simulation result; and outputting the simulation result according to the preset simulation result output type and output mode. The invention establishes the multi-junction solar cell model by means of the semiconductor device simulation software, obtains the variation trend of the electrical property of each sub-junction in the model through simulation, avoids complex physical formula calculation, improves the accuracy of the electrical property simulation of the multi-junction solar cell model, does not need to make a real object through the simulation by establishing the model, obtains a large number of simulation results through adjusting the model parameters, can quickly obtain the optimal epitaxial structure of the multi-junction solar cell, and saves time and cost.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a method and a device for analyzing a sub-junction of a multi-junction solar cell and electronic equipment.
Background
As one of the leading-edge research fields of solar cell research, the development of multi-junction solar cells obtains the favor of higher photoelectric conversion efficiency, but because the solar cells are in a series structure, the overall current of the device is influenced by the minimum current of a single sub-junction, and the minority carrier lifetime in the sub-junction influences the current of the sub-junction, and not only does the multi-junction solar cells also cause defects in the cells due to the epitaxial manufacturing process level of the cells and lattice mismatch factors of semiconductor materials, so that the diffusion length of the minority carrier is reduced, the output power of the cells is reduced, the electrical performance is degraded, and the service life is influenced, so that the research on the internal defects of the solar cells has important significance on the development of the multi-junction solar cells.
In a multi-junction solar cell, current matching (current-matching) analysis is a critical ring for the multi-junction solar cell, and how to effectively and truly obtain the current value of each junction cell in the multi-junction solar cell is a great problem, so how to use a simulation method to organically combine a complete incident spectrum and a complete multi-junction cell structure together, and simulation analysis on a single sub-junction cell becomes a research difficulty.
Disclosure of Invention
In view of the above, the present invention aims to provide a method, a device and an electronic device for analyzing a sub-junction of a multi-junction solar cell, so as to improve the accuracy of electrical performance simulation of the multi-junction solar cell, quickly obtain an optimal epitaxial structure of the multi-junction solar cell, and save time and cost.
In a first aspect, an embodiment of the present invention provides a multi-junction solar cell sub-junction analysis method, including: building a multi-junction solar cell model; the multi-junction solar cell model includes at least one sub-junction; respectively carrying out simulation treatment on each sub-junction of the multi-junction solar cell model by using the preset minority carrier lifetime and the preset defect parameters to obtain a simulation result; and outputting the simulation result according to the preset simulation result output type and output mode.
With reference to the first aspect, the embodiment of the present invention provides a first possible implementation manner of the first aspect, wherein the building process of the multi-junction solar cell model includes: building a device structure of a multi-junction solar cell model according to preset layer thickness, layer width, doping concentration, material composition and grid information; the device structure comprises a first lead-out area, a sub-junction area and a second lead-out area which are sequentially connected; and setting parameters of the device structure according to a preset poisson equation, a current continuity equation, a drift diffusion equation, thermodynamic statistical distribution of carrier concentration, a mobility model, an SRH model and an inter-band tunneling model to obtain a multi-junction solar cell model.
With reference to the first possible implementation manner of the first aspect, the present embodiment provides a second possible implementation manner of the first aspect, wherein the first lead-out area includes a first anode and a first cathode; the sub-junction region comprises at least one of the sub-junctions; the second lead-out area includes a second anode and a second cathode.
With reference to the second possible implementation manner of the first aspect, an embodiment of the present invention provides a third possible implementation manner of the first aspect, where the method further includes: and removing the first lead-out area part and the second lead-out area part connected by the sub-junctions except the current sub-junction when each sub-junction is subjected to simulation processing.
With reference to the first possible implementation manner of the first aspect, the embodiment of the present invention provides a fourth possible implementation manner of the first aspect, wherein the first surface of the sub-junction area is provided with an optical coating, and a front-end transmittance of the optical coating is 95% and a rear-end transmittance of the optical coating is 100%.
With reference to the first aspect, an embodiment of the present invention provides a fifth possible implementation manner of the first aspect, wherein the preset defect parameters include at least one defect parameter, and each defect parameter includes a plurality of trap densities and a plurality of trap sections.
With reference to the fifth possible implementation manner of the first aspect, the embodiment of the present invention provides a sixth possible implementation manner of the first aspect, wherein performing a simulation process on each sub-junction of the multi-junction solar cell by using a preset defect parameter includes: fixing the trap density, and performing simulation treatment on the sub-junctions by using a plurality of capture sections; and fixing the trapping section, and performing simulation processing on the sub-junction by utilizing the densities of the plurality of traps.
With reference to the first aspect, an embodiment of the present invention provides a seventh possible implementation manner of the first aspect, wherein the simulation result output type includes at least one of energy band distribution, light intensity distribution, electron hole distribution, electric field potential distribution, light absorption rate distribution, open circuit voltage, short circuit current, maximum output power, and conversion efficiency; the output mode includes a picture mode and/or a text mode.
In a second aspect, an embodiment of the present invention further provides a multi-junction solar cell sub-junction analysis device, including: the model building module is used for building a multi-junction solar cell model, and the multi-junction solar cell model comprises at least one sub-junction; the simulation module is used for respectively carrying out simulation treatment on each sub-junction of the multi-junction solar cell model by utilizing the preset minority carrier lifetime and the preset defect parameters to obtain a simulation result; the output module is used for outputting the simulation result according to the preset simulation result output type and output mode.
In a third aspect, an embodiment of the present invention further provides an electronic device, including a memory, and a processor, where the memory stores a computer program that can be executed on the processor, where the processor executes the steps of the method described in the first aspect.
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides a method, a device and electronic equipment for analyzing a solar cell sub-junction with multiple junctions, wherein the method comprises the following steps: building a multi-junction solar cell model; the multi-junction solar cell model includes at least one sub-junction; respectively carrying out simulation treatment on each sub-junction of the multi-junction solar cell model by using the preset minority carrier lifetime and the preset defect parameters to obtain a simulation result; and outputting the simulation result according to the preset simulation result output type and output mode. According to the embodiment of the invention, the multi-junction solar cell model is built by means of the semiconductor device simulation software, the variation trend of the electrical property of each sub-junction of the multi-junction solar cell model is obtained through simulation, complex physical formula calculation is avoided, the accuracy of the electrical property simulation of the multi-junction solar cell model is improved, meanwhile, the simulation is carried out by building the model, a real object is not required to be manufactured, a large number of simulation results are obtained by adjusting model parameters, and therefore, the optimal epitaxial structure of the multi-junction solar cell can be obtained rapidly, and time and cost are saved.
Additional features and advantages of the invention will be set forth in the description which follows, or in part will be obvious from the description, or may be learned by practice of the invention.
In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for analyzing a sub-junction of a multi-junction solar cell according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a four-junction solar cell module according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a structure for processing a current sub-junction according to an embodiment of the present invention;
fig. 4 is a graph showing the variation of the third sub-junction current-voltage JV performance with minority carrier lifetime in a four-junction solar cell model according to an embodiment of the present invention;
FIG. 5 is a graph showing the variation of the third sub-junction current voltage JV performance with the capture cross section in a four-junction solar cell model according to an embodiment of the present invention;
FIG. 6 is a graph showing the variation of the third sub-junction current voltage JV performance with the trap density in a four-junction solar cell model according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a simulation fit curve of a complete four-junction solar cell model structure according to an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of a multi-junction solar cell sub-junction analysis device according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Icon:
1-a first lead-out area; a 2-sub junction region; 3-a second lead-out area; 11-a first anode; 12-a first cathode; 21-a first sub-junction; 22-a first tunnel junction; 23-a second sub-junction; 24-a second tunnel junction; 25-third sub-junction; 26-a third tunnel junction; 27-fourth sub-junction; 31-a second anode; 32-a second cathode.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
At present, less research is performed on the simulation of the multi-junction solar cell, and most of the prior art utilizes real objects to perform electrical performance analysis on the multi-junction solar cell, and the simulation is performed on a large number of real objects, so that the cost is high, time and labor are consumed.
For the convenience of understanding the present embodiment, a detailed description will be first made of a multi-junction solar cell sub-junction analysis method disclosed in the embodiment of the present invention.
Referring to a flow chart of a multi-junction solar cell sub-junction analysis method shown in fig. 1, the method specifically comprises the following steps:
step S102, building a multi-junction solar cell model; the multi-junction solar cell model includes at least one sub-junction;
the APSYS simulation software can be utilized to build a multi-junction solar cell model, when the multi-junction solar cell model is built, the device structure of the multi-junction solar cell is built, and then parameter setting is carried out on the built device structure, so that the multi-junction solar cell model is obtained. The semiconductor modeling software APSYS adopting the finite element analysis method is subjected to simulation design, comprises a comprehensive physical model, can realize modeling and analysis of each layer structure of the multi-junction solar cell, is built by building mesh lattice points, is subjected to numerical analysis, is friendly in interface, can set physical parameters such as material selection, doping concentration, thickness and the like according to actual conditions, can also be imported into actual optical characteristics and electrical characteristics, and can finally output data such as an energy band diagram, an incident light intensity distribution diagram, an electron-hole pair generation rate diagram, an electron concentration distribution diagram, a hole concentration distribution diagram, a current-voltage J-V characteristic curve and the like of the device.
Building a device structure of a multi-junction solar cell model according to preset layer thickness, layer width, doping concentration, material composition and grid information; the device structure comprises a first lead-out area, a sub-junction area and a second lead-out area which are sequentially connected.
Because the multijunction solar cell model comprises at least one sub-junction, the sub-junction and the sub-junction are connected by adopting a tunnel junction, and a first export area and a second export area are required to be arranged to ensure that photo-generated carriers generated in the simulation process can flow out of the first export area and the second export area, so that simulation measurement is facilitated, when a device structure is built, the thickness, the width, the material composition, the doping concentration and the like of each part are required to be reasonably arranged, grids are divided according to specific requirements of each part, grid information is obtained, and the accuracy of the device structure building can be effectively improved according to the grid information.
Further, the first lead-out area includes a first anode and a first cathode; the sub-junction region includes at least one sub-junction; the second lead-out area includes a second anode and a second cathode; when the model is built, the P doped region of the multi-junction solar cell model is respectively connected with the first cathode and the second cathode; the N doped region is respectively connected with the first anode and the second anode, so that photo-generated carriers of the multi-junction solar cell model can flow out from an electrode connected with the multi-junction solar cell model.
After the basic device structure is built, parameter settings are required for the current device structure.
And according to the energy band distribution, the light intensity distribution, the electron hole distribution, the electric field potential distribution and the light absorption rate distribution of the multi-junction solar cell model required by simulation, parameter setting is carried out on the device structure by utilizing a preset poisson equation, a current continuity equation, a drift diffusion equation, carrier concentration thermodynamic statistical distribution, a mobility model, an SRH model and an inter-band tunneling model, so as to obtain the multi-junction solar cell model.
The parameter setting of the device structure is performed by using a preset equation, a model and the like, and the parameter setting can be realized by using related knowledge of solar cells and APSYS simulation software in the field, which are not described herein.
In an actual working environment of a solar cell, an antireflection film is often required to be arranged on the surface of the solar cell to reduce reflection of incident light capable of generating photocurrent on the surface of the cell, and meanwhile, reflection of incident light which does not contribute to a photo-generated carrier is increased, so that the photoelectric conversion efficiency of the solar cell is improved; therefore, when the solar cell model is built, an optical coating is arranged on the first surface of the sub-junction area, the front-end transmittance of the optical coating is 95%, and the rear-end transmittance of the optical coating is 100%, so that the effect of the antireflection film is achieved, and meanwhile, the corresponding calculated amount is reduced.
Step S104, respectively carrying out simulation treatment on each sub-junction of the multi-junction solar cell model by utilizing the preset minority carrier lifetime and the preset defect parameters to obtain a simulation result;
when each sub-junction is subjected to simulation processing, the first lead-out area part and the second lead-out area part which are connected with the sub-junctions except the current sub-junction are firstly removed, so that the anode and the cathode are just arranged in the N doped area and the P doped area of the current sub-junction, and the photo-generated carriers of the current sub-junction are ensured to flow out from the electrode connected with the current sub-junction, and the photo-generated carriers of the rest sub-junctions are fixed.
In order to fit experimental measurement results of the multi-junction solar cell model before being irradiated, the trend of the current-voltage curve of the sub-junction to the minority carrier lifetime change is analyzed first, and then the trend of the current-voltage curve of the sub-junction to the defect parameter change is analyzed.
And obtaining simulation results such as open-circuit voltage, short-circuit current, maximum output power, conversion efficiency and the like of the current sub-junction under different minority carrier lifetimes by continuously changing minority carrier lifetimes.
In SRH recombination, deep level defects are related to minority carrier lifetime, and minority carrier lifetime and trap density and trapping cross section caused by the defects are related.
The predetermined defect parameters include at least one defect parameter, each defect parameter including a plurality of trap densities and a plurality of trap cross-sections.
When each sub-junction of the multi-junction solar cell is subjected to simulation processing by using preset defect parameters, fixing the trap density under the condition of considering a single trap, and performing simulation processing on the current sub-junction by using a plurality of trapping sections to obtain simulation results such as open-circuit voltage, short-circuit current, maximum output power, conversion efficiency and the like of the current sub-junction under different trapping sections; and fixing the trapping section, and performing simulation processing on the current sub-junction by utilizing a plurality of trap densities to obtain simulation results such as open-circuit voltage, short-circuit current, maximum output power, conversion efficiency and the like of the current sub-junction under different trap densities.
And S106, outputting the simulation result according to the preset simulation result output type and output mode.
The finally output simulation results comprise simulation results such as open-circuit voltage, short-circuit current, maximum output power, conversion efficiency and the like obtained by the simulation, and also comprise parameter data such as energy band distribution, light intensity distribution, electron hole distribution, electric field potential distribution, light absorption rate distribution and the like; the type of the data to be output finally can be determined according to the requirement; the final output mode of the simulation result can be a relatively visual picture mode, a more detailed text mode or two modes for output.
The embodiment of the invention provides a multi-junction solar cell sub-junction analysis method, which comprises the steps of building a multi-junction solar cell model; the multi-junction solar cell model includes at least one sub-junction; respectively carrying out simulation treatment on each sub-junction of the multi-junction solar cell model by using the preset minority carrier lifetime and the preset defect parameters to obtain a simulation result; and outputting the simulation result according to the preset simulation result output type and output mode. According to the embodiment of the invention, the multi-junction solar cell model is built by means of the semiconductor device simulation software, the variation trend of the electrical property of each sub-junction of the multi-junction solar cell model is obtained through simulation, complex physical formula calculation is avoided, the accuracy of the electrical property simulation of the multi-junction solar cell model is improved, meanwhile, the simulation is carried out by building the model, a real object is not required to be manufactured, a large number of simulation results are obtained by adjusting model parameters, and therefore, the optimal epitaxial structure of the multi-junction solar cell can be obtained rapidly, and time and cost are saved greatly.
Corresponding to the above embodiment of the invention, the embodiment of the invention will be described in detail by taking a four-junction solar cell model as an example, wherein:
when the four-junction solar cell model is built, as shown in fig. 2, the four-junction solar cell model comprises a first lead-out area 1, a sub-junction area 2 and a second lead-out area 3 which are sequentially connected, wherein the first lead-out area comprises a first anode 11 and a first cathode 12; the sub-junction region includes a first sub-junction 21, a first tunnel junction 22, a second sub-junction 23, a second tunnel junction 24, a third sub-junction 25, a third tunnel junction 26, and a fourth sub-junction 27; the second lead-out area comprises a second anode 31 and a second cathode 32.
The widths of the first lead-out area 1 and the second lead-out area 3 are 0.5cm, the width of the sub-junction area 2 is 5cm, and the structure of the four-junction solar cell model is that: gaInP/GaAs/In 0.3 Ga 0.7 As/In 0.58 Ga 0.42 As, the first sub-junction 21 is GaInP, the second sub-junction 23 is GaAs, and the third sub-junction 25 is In 0.3 Ga 0.7 As, fourth sub-junction 27 is In 0.58 Ga 0.42 As; each sub-junction comprises a window layer, an emitter layer, a base region and a back electric field which are sequentially connected, when the whole multi-junction solar cell model is simulated, the first cathode and the second cathode are connected together to be used as a back electrode of the solar cell model to cover the bottom surface of the whole solar cell model, but when the multi-junction solar cell model is simulatedWhen each sub-junction of the multi-junction solar cell model is simulated, the first cathode and the second cathode are respectively positioned at two sides of the current sub-junction.
When simulation is carried out, the optical parameters of the absorbing layers of the sub-junction materials only consider the refractive index n and the extinction coefficient k under different incident light wavelengths, the refractive index and the extinction coefficient of each sub-junction are preset, the refractive index n of the absorbing layer of the GaInP material of the first sub-junction 21 is set to be 1.94-4.67, and the extinction coefficient k is set to be 0-1.15; setting the refractive index n of the GaAs material absorbing layer of the second sub-junction 23 to be 3.53-4.50, and the extinction coefficient k to be 0-0.60; a third sub-junction 25In is provided 0.3 Ga 0.7 The refractive index n of the As material absorbing layer is 2.07-4.80, and the extinction coefficient k is 0-0.35; fourth sub-junction 27In is provided 0.58 Ga 0.42 The refractive index n of the As 10 material absorbing layer is 1.12-4.48, and the extinction coefficient k is 0-1.29.
When simulation is performed, incident light is incident from the top end of the four-junction solar cell model, and sequentially passes through the first sub-junction 21, the first tunnel junction 22, the second sub-junction 23, the second tunnel junction 24, the third sub-junction 25, the third tunnel junction 26 and the fourth sub-junction 27, simulation processing is sequentially performed on each sub-junction by using a preset minority carrier lifetime and a preset defect parameter, as shown in fig. 3, when simulation processing is performed on the current sub-junction, a first lead-out area part and a second lead-out area part which are connected by sub-junctions other than the current sub-junction are removed, and the first cathode and the second cathode are respectively positioned on two sides of the current sub-junction.
Taking the simulation of the third sub-junction 25 as an example, the process of performing the simulation of the sub-junction with the preset minority carrier lifetime and the preset defect parameters will be described in detail.
Minority carrier lifetime is preset to be 0.3ns, 0.5ns, 1.0ns, 10ns and 100ns, and a graph of the third sub-junction current voltage JV performance as shown in fig. 4 is obtained.
Taking a trap as an example, the trap density of the pre-fixed trap is 1×10 21 m -3 The trap has trapping sections of 1×10 -18 m 2 、1×10 -17 m 2 、1×10 -16 m 2 、5×10 -16 m 2 And 10X 10 -16 m 2 Obtaining a graph of the variation of the third sub-junction current voltage JV performance with the capture section as shown in FIG. 5; the trap was then fixed to a trapping cross section of 1×10 -17 m 2 The trap densities of the traps were set to 1×10, respectively 21 m -3 、5×10 21 m -3 、10×10 21 m -3 And 100X 10 21 m -3 A graph of the third sub-junction current voltage JV performance versus trap density is obtained as shown in fig. 6.
After each sub-junction is subjected to simulation treatment, the simulation results of the sub-junctions are fitted to obtain simulation fitting results of a complete four-junction solar cell model structure, as shown in FIG. 7, the trap density of the first sub-junction 21GaInP is 3×10 21 m -3 The capture section is fixed to be 1×10 -17 m 2 The method comprises the steps of carrying out a first treatment on the surface of the The second sub-junction 23GaAs has a trap density of 2.6X10 21 m -3 The capture section is fixed to be 1×10 -17 m 2 The method comprises the steps of carrying out a first treatment on the surface of the Third sub-junction 25In 0.3 Ga 0.7 As trap density of 2.6X10 21 m -3 The capture section is fixed to be 1×10 -17 m 2 The method comprises the steps of carrying out a first treatment on the surface of the Fourth sub-junction 27In 0.58 Ga 0.42 As trap density of 1×10 21 m -3 The capture section is fixed to be 1×10 -17 m 2 The method comprises the steps of carrying out a first treatment on the surface of the Since the simulation result in the present embodiment is a current density of 15.669mA/cm 2 Voltage 3.2744V; the current density measured by practical experiment is 0-3.2768 mA/cm 2 The voltage is 15.69-0V; the errors of the simulation result and the experimental result are 0.11% and 0.07%, respectively, and it is known that the multi-junction solar cell sub-junction analysis method provided by the embodiment of the invention can effectively improve the accuracy of the electrical performance simulation of the multi-junction solar cell model.
The embodiment of the invention can also obtain the multi-junction solar cell model under different parameter states by adjusting each parameter of the multi-junction solar cell model, so as to obtain a large number of simulation results, thereby being capable of rapidly obtaining the optimal epitaxial structure of the multi-junction solar cell and saving time and cost.
Corresponding to the above embodiment of the present invention, the embodiment of the present invention further provides a schematic structural diagram of a multi-junction solar cell sub-junction analysis device, as shown in fig. 8, where the device includes:
a model building module 80 for building a multi-junction solar cell model comprising at least one sub-junction;
the simulation module 81 is configured to perform simulation processing on each sub-junction of the multi-junction solar cell model by using a preset minority carrier lifetime and a preset defect parameter, so as to obtain a simulation result;
and the output module 82 is used for outputting the simulation result according to the preset simulation result output type and output mode.
The multi-junction solar cell sub-junction analysis device provided by the embodiment of the invention has the same technical characteristics as the multi-junction solar cell sub-junction analysis method provided by the embodiment, so that the same technical problems can be solved, and the same technical effects can be achieved.
The embodiment of the present invention further provides an electronic device, as shown in fig. 9, where the electronic device 9 includes a memory 91 and a processor 92, and the memory 91 stores a computer program that can be run on the processor 92, and when the processor executes the computer program, the processor implements the steps of the method provided by the embodiment of the present invention.
Referring to fig. 9, the electronic device further includes: a bus 93 and a communication interface 94, the processor 92, the communication interface 94 and the memory 91 being connected by the bus 93; the processor 92 is adapted to execute executable modules, such as computer programs, stored in the memory 91.
The memory 91 may include a high-speed random access memory (RAM, random Access Memory), and may further include a non-volatile memory (non-volatile memory), such as at least one magnetic disk memory. The communication connection between the system network element and at least one other network element is implemented via at least one communication interface 94 (which may be wired or wireless), which may use the internet, a wide area network, a local network, a metropolitan area network, etc.
Bus 93 may be an ISA bus, a PCI bus, an EISA bus, or the like. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, only one bi-directional arrow is shown in fig. 9, but not only one bus or one type of bus.
The memory 91 is configured to store a program, and the processor 92 executes the program after receiving an execution instruction, and the method performed by any of the foregoing embodiments of the present invention may be applied to the processor 92 or implemented by the processor 92.
The processor 92 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the methods described above may be performed by integrated logic circuitry in hardware in processor 92 or by instructions in software. The processor 92 may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), etc.; but may also be a digital signal processor (Digital Signal Processing, DSP for short), application specific integrated circuit (Application Specific Integrated Circuit, ASIC for short), off-the-shelf programmable gate array (Field-Programmable Gate Array, FPGA for short), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be embodied directly in the execution of a hardware decoding processor, or in the execution of a combination of hardware and software modules in a decoding processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in the memory 91 and the processor 92 reads the information in the memory 91 and in combination with its hardware performs the steps of the above method.
Embodiments of the present invention also provide a computer readable medium having non-volatile program code executable by a processor, the program code causing the processor to perform the method according to the above-described embodiments of the invention.
The computer readable medium having the non-volatile program code executable by the processor provided by the embodiment of the invention has the same technical characteristics as the embodiment of the invention provided by the embodiment, so that the same technical problems can be solved, and the same technical effects can be achieved.
The computer program product provided in the embodiments of the present invention includes a computer readable storage medium storing a non-volatile program code executable by a processor, where the program code includes instructions for executing the method described in the foregoing method embodiment, and specific implementation may refer to the method embodiment and will not be described herein.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Finally, it should be noted that: the above examples are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention, but it should be understood by those skilled in the art that the present invention is not limited thereto, and that the present invention is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. A multi-junction solar cell sub-junction analysis method, comprising:
building a multi-junction solar cell model; the multi-junction solar cell model includes at least one sub-junction;
respectively carrying out simulation treatment on each sub-junction of the multi-junction solar cell model by using a preset minority carrier lifetime and a preset defect parameter to obtain a simulation result;
outputting the simulation result according to a preset simulation result output type and output mode;
the construction process of the multi-junction solar cell model comprises the following steps:
building a device structure of the multi-junction solar cell model according to preset layer thickness, layer width, doping concentration, material composition and grid information; the device structure comprises a first lead-out area, a sub-junction area and a second lead-out area which are sequentially connected; the first lead-out region includes a first anode and a first cathode; the sub-junction region includes at least one of the sub-junctions; the second lead-out area includes a second anode and a second cathode; the P doped region of the multi-junction solar cell model is respectively connected with the first cathode and the second cathode, and the N doped region of the multi-junction solar cell model is respectively connected with the first anode and the second anode;
performing parameter setting on the device structure according to a preset poisson equation, a current continuity equation, a drift diffusion equation, thermodynamic statistical distribution of carrier concentration, a mobility model, an SRH model and an inter-band tunneling model to obtain the multi-junction solar cell model;
and performing simulation processing on each sub-junction of the multi-junction solar cell model by using the preset minority carrier lifetime to obtain a simulation result, wherein the simulation result comprises the following steps:
obtaining simulation results of open-circuit voltage, short-circuit current, maximum output power and conversion efficiency of the current sub-junction under different minority carrier lifetimes by continuously changing minority carrier lifetimes;
the preset defect parameters comprise at least one defect parameter, and each defect parameter comprises a plurality of trap densities and a plurality of trap sections; and performing simulation processing on each sub-junction of the multi-junction solar cell by using preset defect parameters, wherein the simulation processing comprises the following steps:
fixing the trap density, and performing simulation processing on the sub-junctions by using the plurality of trapping sections;
and fixing the trapping section, and performing simulation processing on the sub-junctions by utilizing the plurality of trap densities.
2. The method according to claim 1, wherein the method further comprises:
and removing the first lead-out area part and the second lead-out area part connected by the sub-junctions except the current sub-junction when each sub-junction is subjected to simulation processing.
3. The method of claim 1, wherein the first surface of the sub-junction region is provided with an optical coating having a front-end transmittance of 95% and a back-end transmittance of 100%.
4. The method of claim 1, wherein the simulation result output categories include at least one of energy band distribution, light intensity distribution, electron hole distribution, electric field potential distribution, light absorption rate distribution, open circuit voltage, short circuit current, maximum output power, and conversion efficiency;
the output mode comprises a picture mode and/or a text mode.
5. A multi-junction solar cell sub-junction analysis device, comprising:
the model building module is used for building a multi-junction solar cell model, and the multi-junction solar cell model comprises at least one sub-junction;
the simulation module is used for respectively carrying out simulation treatment on each sub-junction of the multi-junction solar cell model by utilizing the preset minority carrier lifetime and the preset defect parameters to obtain a simulation result;
the output module is used for outputting the simulation result according to the preset simulation result output type and output mode;
the model building module is specifically used for:
building a device structure of the multi-junction solar cell model according to preset layer thickness, layer width, doping concentration, material composition and grid information; the device structure comprises a first lead-out area, a sub-junction area and a second lead-out area which are sequentially connected; the first lead-out region includes a first anode and a first cathode; the sub-junction region includes at least one of the sub-junctions; the second lead-out area includes a second anode and a second cathode; the P doped region of the multi-junction solar cell model is respectively connected with the first cathode and the second cathode, and the N doped region of the multi-junction solar cell model is respectively connected with the first anode and the second anode;
performing parameter setting on the device structure according to a preset poisson equation, a current continuity equation, a drift diffusion equation, thermodynamic statistical distribution of carrier concentration, a mobility model, an SRH model and an inter-band tunneling model to obtain the multi-junction solar cell model;
the simulation module is specifically used for:
obtaining simulation results of open-circuit voltage, short-circuit current, maximum output power and conversion efficiency of the current sub-junction under different minority carrier lifetimes by continuously changing minority carrier lifetimes;
the preset defect parameters comprise at least one defect parameter, and each defect parameter comprises a plurality of trap densities and a plurality of trap sections; the simulation module is also used for:
fixing the trap density, and performing simulation processing on the sub-junctions by using the plurality of trapping sections;
and fixing the trapping section, and performing simulation processing on the sub-junctions by utilizing the plurality of trap densities.
6. An electronic device comprising a memory, a processor, the memory having stored therein a computer program executable on the processor, characterized in that the processor, when executing the computer program, implements the steps of the method of any of the preceding claims 1 to 4.
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