CN109857685B

CN109857685B - MPU and FPGA extended multi-serial port implementation method

Info

Publication number: CN109857685B
Application number: CN201811485584.0A
Authority: CN
Inventors: 金亮; 滕兆宏; 赵长荣; 顾强; 柳常清; 黄磊; 刘政; 刘义
Original assignee: Integrated Electronic Systems Lab Co Ltd
Current assignee: Integrated Electronic Systems Lab Co Ltd
Priority date: 2018-12-06
Filing date: 2018-12-06
Publication date: 2021-04-09
Anticipated expiration: 2038-12-06
Also published as: CN109857685A

Abstract

The invention relates to a method for realizing MPU and FPGA expansion multi-serial port, which uses a DMA controller in the MPU to transmit and control data in data transmission; on the FPGA side, when the serial port detects a start signal, the FPGA deframes and stores the received data through the parameters of a register in the serial port configuration module, and after storing a frame byte, the receiving FIFO adds a timestamp after the frame data; when data is sent, the related serial ports frame the data in the transmission FIFO according to the parameters of the registers in the corresponding serial port configuration modules, and then the data is sent out through the serial ports; and on the MPU side, the sending and receiving of serial port data are controlled, the MPU carries out addressing operation through related register addresses defined by each serial port expanded by the FPGA, and the MPU carries out polling operation on the related serial ports in a timing mode in an interrupt query mode. The invention has the advantages of high efficiency, accuracy, strong reusability, short development period and low cost; meanwhile, the product cost is reduced, and the easy maintenance of the product is enhanced.

Description

MPU and FPGA extended multi-serial port implementation method

Technical Field

The invention belongs to the technical field of Field Programmable Gate Arrays (FPGA), and particularly relates to a method for expanding multiple serial ports of an MPU (micro processing unit) and an FPGA (field programmable gate array) based on a Direct Memory Access (DMA) technology.

Background

With the continuous development of the electronic technology level, the cost performance of a high-performance integrated circuit is continuously improved, and the integrated circuit is like an FPGA (field programmable gate array); the embedded processor (herein, it is collectively referred to as MPU) products provided by companies such as Intel, AMD, Motorola, and ARM, which have relatively good versatility, relatively strong processing capability, and good expandability, accelerate the updating of electronic products.

In the field of multi-serial port communication, with the development of technologies of FPGA and MPU, the yield of common serial port expansion chips used in large quantities year by year before is reduced, the price is also improved year by year, and troubles are brought to the later maintenance and the cost of related designed products.

Due to the problems of high maintenance and high cost of the traditional multi-serial port expansion method, a large amount of MPU and FPGA expansion serial port communication schemes appear subsequently. However, with the further development of the integrated circuit, a large number of schemes are no longer suitable for the current processing chip, and the problems of poor real-time performance, slow MPU working efficiency and the like are increasingly highlighted.

Disclosure of Invention

In order to solve the technical problem, the invention provides a method for realizing MPU and FPGA expansion multi-serial port based on DMA technology. DMA technology is an abbreviation of Direct Memory Access, meaning "Direct Memory Access", which allows data to be directly read and written between an external device and a Memory without the need for CPU intervention. The invention uses the DMA controller in the MPU to transmit and control data in data transmission, each extended serial port is completely independent, each serial port is not affected in the full duplex receiving and transmitting environment, parameters such as baud rate, parity check and the like of each serial port can be set independently, the number of the serial ports required in actual work can be configured according to the actual situation, and the configured serial ports do not have the problem of interrupt priority. The technical scheme adopted by the invention is as follows:

a MPU and FPGA expand the implement method of the multi-serial port, FPGA and MPU adopt 8 routes of parallel data bus to carry on the data interaction, adopt 8 routes of address bus to realize the addressing operation; a clock counter is arranged on the FPGA side for adding a timestamp, each independent asynchronous serial port unit comprises a data receiving module, a data sending module, a serial port configuration module and a baud rate generator, the data receiving module comprises a receiving FIFO and a data receiving register, the data sending module comprises a sending FIFO and a data sending register, the serial port configuration module is provided with a register for storing data transmission and control parameters, and a DMA (direct memory access) controller in an MPU (micro processing unit) is used for transmitting and controlling data in the data transmission;

and when the FPGA normally works, the FPGA receiving end detects a starting signal. On the FPGA side, when the serial port detects a start signal, the FPGA deframes and stores the received data through the parameters of a register in the serial port configuration module, and after storing a frame byte, the receiving FIFO adds a timestamp after the frame data; when data is sent, the related serial ports frame the data in the transmission FIFO according to the parameters of the registers in the corresponding serial port configuration modules, and then the data is sent out through the serial ports;

and on the MPU side, the receiving and sending of serial port data are controlled, the FPGA which is arranged below the MPU is regarded as a plurality of FIFO units, the MPU carries out addressing operation through related register addresses defined by each path of serial port expanded by the FPGA, and the MPU carries out polling operation on related serial ports in a timing mode through an interrupt inquiry.

And when the MPU and the FPGA transmit and receive related data, the DMA technology is adopted, so that the system operation efficiency is higher.

The invention has the beneficial effects that:

1) the invention realizes the unified description of asynchronous serial port communication, overcomes the defects of poor processor efficiency, long development period and high cost of the traditional asynchronous serial port data processing method, and has the advantages of high efficiency, accuracy, strong reusability, short development period and low cost.

2) The invention realizes the real-time and high-efficiency operation of the FPGA extended serial port by using the DMA technology of the MPU, adding a timestamp in the communication process and the like, simultaneously reduces the product cost and enhances the easy maintenance of the product.

Drawings

FIG. 1 is a block diagram of the overall architecture of the system of the present invention;

FIG. 2 is a block diagram of a data transfer process based on DMA technology according to the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The FPGA in the implementation adopts Xilinx (Sailing) Spartan-6 series products XC6SLX9, and the products can be connected with a data line and an address line of an MPU processor through a parallel bus, so that the aims of expanding a serial port and meeting the diversified requirements of users are fulfilled.

Fig. 1 is a block diagram of the general architecture of the system of the present invention. The FPGA and the MPU adopt 8 paths of parallel data buses (DATE [0,7]) for data interaction and 8 paths of address buses (ADDR [0,7]) for addressing operation; read enable (RD: enable flag when MPU reads data), write enable (WR: enable flag when MPU writes data).

The read and write enable signals are a pair of signals known in the art, and they mainly represent the read and write data states of the MPU, thereby controlling the reading and writing of data. For example, if the MPU is to read data from a serial device, the MPU then selects the address of the relevant device, and a read enable signal (assumed to be active low) is required to read the data up, otherwise the data is unreadable. The write enable signals are similar. The present application does not introduce such bus data read/write timing control, and therefore, will not be described in detail.

On the FPGA side, each independent asynchronous serial port unit comprises a data receiving module, a data transmitting module, a serial port configuration module and a baud rate generator, wherein the data receiving module comprises a receiving FIFO (first in first out) and a data receiving register, the data transmitting module comprises a transmitting FIFO (first in first out data buffer area) and a data transmitting register, and a DMA (direct memory access) controller in the MPU is used for transmitting and controlling data in data transmission. The receiving FIFO is electrically connected with the data receiving register, the transmitting FIFO is electrically connected with the data transmitting register, the serial port configuration module is electrically connected with the baud rate generator, and the serial port configuration module and the baud rate generator are respectively electrically connected with the data receiving module and the data transmitting module. The FPGA and the serial port equipment are connected through TX and RX. TX and RX are standard serial ports of TTL level, and are used for transmitting data lines and receiving data lines.

The data sending module is mainly used for caching data sent by the MPU and framing the data and sending the data to the serial port equipment; and the data receiving module is mainly used for receiving data from the serial port equipment, deframing and buffering the data in the receiving FIFO.

In order to meet the accuracy of adding the timestamp on the FGPA side, a clock counter (the counting period is determined according to practical application) needs to be arranged in the FPGA, the clock counter is electrically connected with the MPU through a GPIO signal line, and the MPU can perform zero clearing time setting. This clock counter is used to add a timestamp. The specific operation is as follows: when the FPGA receives the FIFO and stores the FIFO into a frame of data, the FPGA takes the current counter value and converts the value into time according to the precision of the counter, and the time is stored into the receiving FIFO.

And on the MPU side, the data receiving and sending of the serial port equipment are controlled, the FPGA which is arranged below the MPU can be regarded as a plurality of FIFO units, and the MPU carries out addressing operation through related register addresses defined by each path of serial port expanded by the FPGA.

The MPU operates related serial port equipment at regular time in an interrupt query mode through the FPGA, and the specific query time can be determined according to the number of the extended serial ports and the used baud rate.

When the MPU transmits and receives related data, the MPU can be greatly liberated by adopting the DMA technology, so that the system operation efficiency is higher.

The FPGA simulates a plurality of independent serial ports, and works in an FIFO mode. The FPGA controls the data receiving and sending and the setting of the serial port baud rate, the parity check and the like according to the detailed address of the relevant register of the corresponding serial port; and the MPU processor uses a data line and an address line to perform data transceiving interaction with the FPGA in a DMA mode. Meanwhile, the parameters of the configuration register of the corresponding serial port are changed through the parallel bus to realize the configuration and control of the corresponding serial port;

in the normal working process, the unified acknowledgement address coding format is as follows:

the address bus structure is shown in table 1 below:

A7

A6

A5

A4

A3

A2

A1

A0

X2

X1

X0

D/K

Y4

Y3

Y2

Y1

TABLE 1

Note: A5-A7 is used for determining the serial port number; a4 is used to determine whether the address field is serial port configuration area or data receiving and transmitting area; A0-A3 is a specific functional region.

When the system normally works, the FPGA side and the MPU side uniformly confirm the coding format of the related serial port address and the related serial port control base address, and the corresponding base address of the FPGA extended 8-way serial port is as the following table 2:

serial number	Address range offset	Description of the invention
			1	0x00000000	Serial port 1 corresponding address
2	0x00000020	Serial port 2 corresponding address
			3	0x00000040	Serial port 3 corresponding address
4	0x00000060	Serial port 4 corresponding address
			5	0x00000080	Serial port 5 corresponding address
6	0x000000A0	Serial port 6 corresponding address
			7	0x000000C0	Serial port 7 corresponding address
8	0x000000E0	Serial port 8 corresponding address

TABLE 2

As can be seen from the above table, the serial port base address is selected mainly from A5-A7 in Table 1.

As shown in fig. 1, the FPGA side includes a data receiving module, a data sending module, and a serial port configuration module, each module has an address space corresponding thereto, and allocation of the address space is shown in table 1.

The data sending module further comprises: sending a flag bit detection register to detect whether the serial port is available (0x 00 is detected to be free, 0xaa indicates that the FPGA is busy); a transmission data length register for designating the lengths of the checksum of the data to be transmitted and all the frame data to the FPGA; and the first sum check register is used for storing the check sum of data sent by the MPU side to the FPGA. Specifically, taking serial port 2 as an example, see table 3 below:

TABLE 3

The data receiving module further comprises: a receive flag bit detection register for detecting whether the receive buffer has data (0xaa has new data, 0x00 has no new data); a received data length register for designating the lengths of the received data and the checksums of all frame data to the MPU side; a frame end register for indicating the end of the receiving to the FPGA by the MPU end, wherein the writing operation 0x5a indicates that the MPU finishes reading the data; and clearing the data register of the receiving buffer area for clearing the receiving FIFO. Specifically, taking serial port 2 as an example, see table 4 below:

TABLE 4

The serial port configuration module comprises: the baud rate setting register is used for setting the baud rate of the corresponding serial port; the data bit setting register is used for setting data bits of the corresponding serial port; the parity check bit setting register is used for setting the parity check bit of the corresponding serial port; the stop bit setting register is used for setting a stop check bit of the corresponding serial port; the second sum check register is used for the MPU end to read the sum check of the configuration information received by the FPGA and verify the correctness of the issued configuration; and downloading a configuration ending register, wherein the configuration ending register is used for sending a configuration ending command to the FPGA end by the MPU end, and the MPU continuously operates the address twice, firstly writes 00 and then writes 01. Specifically, taking serial port 2 as an example, see table 5 below:

TABLE 5

And the MPU side carries out addressing operation on the corresponding serial port related register in an interrupt query mode, thereby controlling the unified work of multiple serial ports. The interrupt inquiry can be realized by setting a clock timer to interrupt, polling each serial port at regular time, inquiring the receiving and sending flag bit (specifically, see table 3 and table 4) of the flag bit detection register in each serial port, determining that the serial port is operated in a certain time slice through the inquiry of the flag bit, and adjusting the polling time according to the number of the expanded serial ports, the used baud rate and the like.

In the data transfer process, the data transfer and control are performed by using the internal DMA controller of the MPU, and the MPU can be released to perform other operations. The operation of the MPU on the serial port is in an interrupt inquiry mode, namely the MPU polls whether each serial port transceiving mark is effective or not in an interrupt inquiry mode to trigger DMA data transmission. Before starting DMA data transmission, values of an MPU data transceiving cache first address, an FPGA transceiving FIFO first address and a transmission data volume are respectively given to corresponding control registers, and DMA operation is started. After the transmission of the relevant data is completed, the data bus and the address bus are handed to the MPU. As shown in fig. 2, a block diagram of a data transmission flow based on the DMA technology of the present invention includes the following specific steps:

step 1, a DMA controller in the MPU detects a register according to a marking bit of an FPGA side data receiving module and a marking bit of a data sending module and judges whether an effective DMA request is triggered;

step 2, judging whether the MPU responds, if so, turning to the next step, and if not, turning to the step 1;

step 3, the MPU sets the related parameters (the length of data to be sent and received by each path of serial port, the address of a receiving and sending memory and the like) of the DMA controller;

step 4, sending memory addresses (source address and target address);

step 5, sending data;

step 6, judging whether the transmission is finished, if so, switching to the next step, and if not, modifying the address of the memory and switching to the step 4;

and step 7, finishing the DMA transfer.

As shown in fig. 1, adding a time stamp to the receiving FIFO on the FPGA side requires a clock counter to be provided in the FPGA, and the counting interval is in ms (depending on the accuracy of the time stamp added). The clock counter is cleared to the time by the MPU, the MPU is cleared to the time and then stores the time, and the specific data frame receiving time can be calculated by counting the last timestamp of the frame data in the receiving FIFO and the time stored by the MPU.

The specific storage mode of the time stamp in the receiving FIFO of the FPGA is as follows: after a frame byte is stored, the receive FIFO fills 90, 90 as the start tag of the time stamp in the first two addresses of 2+ X (X number depends on the interval of MPU clear pair) consecutive after the frame data, and adds the time stamp from the X addresses of the third address.

For example, as shown in table 6 below, the counter designed in FPGA is 1ms apart, and the MPU is 1 minute for a time, the counter countable value should be no less than 60,000. The MPU times for the first time are shown in Table 6 (labeled time A, stored in address a of MPU), at which point the FPGA count is cleared. If a frame of data is received when the FPGA counter reaches 5000, then the time for this frame of play (labeled time B) is: b ═ a +5000ms, i.e., 0 min 5 sec at 10 months, 10 days, 10 months, 2018;

Time	year of year	Moon cake	Day(s)	Time of flight	Is divided into	Second of	Millisecond (ms)	FPGA count value
									MPU first time of time setting	2018	10	10	10	00	00	000	0
FPGA count value								5000
									MPU second time setting	2018	10	10	10	01	00	000	0

TABLE 6

The above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and the contents, which are not described in detail, are well known to those skilled in the art.

Claims

1. A MPU and FPGA expand the implement method of the multi-serial port, FPGA and MPU adopt 8 routes of parallel data bus to carry on the data interaction, adopt 8 routes of address bus to realize the addressing operation; the method is characterized in that a DMA controller in the MPU is used for data transmission and control in the data transmission, and the MPU polls whether each serial port transceiving mark is effective or not in an interrupt query mode to trigger the DMA data transmission;

on the FPGA side, when the serial port detects a start signal, the FPGA deframes and stores the received data through the parameters of a register in the serial port configuration module, and after storing a frame byte, the receiving FIFO adds a timestamp after the frame data; when data is sent, the related serial ports frame the data in the transmission FIFO according to the parameters of the registers in the corresponding serial port configuration modules, and then the data is sent out through the serial ports;

on the MPU side, the receiving and sending of serial port data are controlled, the FPGA which is arranged below is regarded as a plurality of FIFO units, the MPU carries out addressing operation through related register addresses defined by each path of serial port expanded by the FPGA, and the MPU carries out polling operation on related serial ports in a timing mode through interrupt inquiry;

the data sending module further comprises: a transmission flag bit detection register, a transmission data length register, and a first sum check register;

the data receiving module further comprises: a receiving mark bit detection register, a receiving data length register, a frame end register and a receiving buffer area data clearing register;

the serial port configuration module comprises: a baud rate setting register, a data bit setting register, a parity check bit setting register, a stop bit setting register, a second sum check register and a download configuration ending register;

the specific steps of using the DMA controller in the MPU to transmit and control data comprise:

step 3, the MPU sets the related parameters of the DMA controller;

step 4, sending a memory address;

step 5, sending data;

step 7, DMA transfer is finished;

the DMA controller related parameters in step 3 include: the length of data to be sent and received by each path of serial port is used for receiving and sending memory addresses;

the sending memory address in the step 4 comprises a source address and a target address;

the FPGA side and the MPU side confirm the address coding format and the related serial port control base address in a unified way;

the interrupt inquiry is realized by setting a clock timer to interrupt, polling each serial port at regular time, inquiring a serial port mark bit detection register so as to determine the operation of the serial port in a certain time slice, wherein the polling time can be adjusted according to the number of the expanded serial ports and the used baud rate;

the clock counter is electrically connected with the MPU through a GPIO signal line, and the MPU is reset and timed in an integral point way;

the specific operation of adding the time stamp by the clock counter is as follows: when the FPGA receives the FIFO and stores the FIFO into a frame of data, the FPGA takes the value of the clock counter at the moment, converts the value into time according to the precision of the clock counter and stores the time into the receiving FIFO;

the storage mode of the time stamp in the receiving FIFO is as follows: when a frame byte is stored, the receiving FIFO fills 90, 90 in the first two addresses of 2+ X consecutive addresses following the frame data as the start marker of the time stamp, adding the time stamp from X addresses of the third address.

2. The method for implementing the MPU and FPGA extended multi-serial port as recited in claim 1, wherein the FPGA uses Xilinx Spartan-6 series product XC6SLX 9.