CN109842410A - Frequency divider and transceiver including the frequency divider - Google Patents
Frequency divider and transceiver including the frequency divider Download PDFInfo
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- CN109842410A CN109842410A CN201811424661.1A CN201811424661A CN109842410A CN 109842410 A CN109842410 A CN 109842410A CN 201811424661 A CN201811424661 A CN 201811424661A CN 109842410 A CN109842410 A CN 109842410A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/68—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer
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Abstract
A kind of frequency divider may include: core circuit, including the first trigger loop and the second trigger loop, wherein, each of first trigger loop and the second trigger loop divide the frequency of the received clock signal of control terminal by trigger, wherein, core circuit is configured as: the second signal output frequency division signal of the first signal and the output of the second trigger loop based on the output of the first trigger loop, the first signal and the second signal frequency dividing ratio having the same and different phases, and pass through the input terminal feedback division signal of each of the first trigger loop and the second trigger loop；Duty-cycle correction circuit receives fractional frequency signal and exports the differential output signal generated by the duty ratio for correcting fractional frequency signal；And output circuit, the first output signal and the second output signal are exported, the first output signal is the signal amplified from differential output signal, and the second output signal is the orthogonal signalling of the first output signal.
Description
Cross reference to related applications
The 10-2017- submitted this application claims on November 28th, 2017 to Korean Intellectual Property Office (KIPO)
The 10-2018-0078249 Korean Patent that No. 0161007 South Korea patent application and on July 5th, 2018 submit to KIPO
The priority of application, it is open to be incorporated herein by reference in their entirety.
Technical field
Present inventive concept is related to a kind of frequency divider and the transceiver including the frequency divider, more particularly, to a kind of correction
The frequency divider of duty ratio, and the transceiver including the frequency divider.
Background technique
Frequency divider divides the frequency of input signal, and generates the output signal that frequency is lower than frequency input signal.
For example, frequency divider is to receive input signal, the circuit of output signal is divided and generated.Frequency divider can be used for clock generation
Circuit, for example, local oscillator, phaselocked loop (PLL), frequency synthesizer etc., and it is various integrated including clock forming circuit
Circuit.Frequency divider can be classified as frequency divided by the integer frequency divider of Integer N or by frequency divided by score for example N.5
Frequency divider.In integer frequency divider, it may be led being applied in radio frequency (RF) transceiver with the signal source exported greatly
It draws effect (pull effect).In fractional divider, when applying to it has the signal source exported greatly, it may not send out
It is raw to draw effect.However, fractional divider delays the periodic signal occurred in scaling-down process and frequency is spuious, this is a kind of non-
Expected frequency.
In addition, fractional divider usually exports 40% or 60% duty ratio, and may be not easily applied to need
The system of 50% duty ratio.
Summary of the invention
The exemplary embodiment conceived according to the present invention provides a kind of frequency divider comprising: core circuit, including first
Trigger loop and the second trigger loop, wherein each of the first trigger loop and the second trigger loop are to logical
The frequency for crossing the received clock signal of control terminal of trigger is divided, wherein core circuit is configured as: based on the first touching
Send out the first signal of device loop output and the second signal output frequency division signal of the second trigger loop output, the first signal and the
Binary signal frequency dividing ratio having the same and different phases, and by the first trigger loop and the second trigger loop
The input terminal feedback division signal of each；Duty-cycle correction circuit receives fractional frequency signal and exports through correction fractional frequency signal
Duty ratio and the differential output signal that generates；And output circuit, the first output signal of output and the second output signal, first
Output signal is the signal amplified from differential output signal, and the second output signal is the orthogonal signalling of the first output signal.
The exemplary embodiment conceived according to the present invention provides a kind of frequency divider comprising: core circuit receives clock
Signal simultaneously exports the fractional frequency signal that frequency dividing generation is carried out by the frequency to clock signal；And duty-cycle correction circuit, it receives
Fractional frequency signal and the differential output signal according to decision level output with new duty ratio, wherein duty-cycle correction circuit passes through
The edge slope of feedback and the differential output signal adjustment fractional frequency signal based on feedback is executed, to differential output signal to adjust original
Beginning duty ratio makes differential output signal have new duty ratio.
The exemplary embodiment conceived according to the present invention provides a kind of transceiver comprising: core circuit receives clock
Signal exports the fractional frequency signal generated and the frequency to clock signal divides, and including the first trigger loop
With the second trigger loop, each of the first trigger loop and the second trigger loop include multiple triggers；And it accounts for
Sky receives fractional frequency signal and exports the differential output signal generated by the duty ratio for correcting fractional frequency signal than correcting circuit.
Detailed description of the invention
The exemplary embodiment that present inventive concept is described in detail by referring to accompanying drawing, will be more clearly understood present inventive concept
Above and other feature, in the accompanying drawings:
Fig. 1 is the block diagram of the frequency divider for the exemplary embodiment conceived according to the present invention；
Fig. 2 is the waveform diagram of the signal of the frequency divider for the exemplary embodiment conceived according to the present invention；
Fig. 3 A and Fig. 3 B are the circuit diagrams of the frequency dividing core circuit for the exemplary embodiment conceived according to the present invention；
Fig. 4 be the signal for being inputted or being exported by frequency dividing core circuit for the exemplary embodiment conceived according to the present invention when
Sequence figure；
Fig. 5 is the circuit diagram of the duty-cycle correction circuit for the exemplary embodiment conceived according to the present invention；
Fig. 6 is the timing for the signal of the exemplary embodiment conceived according to the present invention generated by duty-cycle correction circuit
Figure；
Fig. 7 A is the circuit diagram of the output circuit for the exemplary embodiment conceived according to the present invention；
Fig. 7 B be the exemplary embodiment conceived according to the present invention output circuit in include logic circuit diagram；
Fig. 8 is the timing diagram for the signal of the exemplary embodiment conceived according to the present invention generated by output circuit；
Fig. 9 is the circuit diagram of the output circuit for the exemplary embodiment conceived according to the present invention；
Figure 10 is the circuit diagram of the driving voltage controlling circuit for the exemplary embodiment conceived according to the present invention；
When Figure 11 is the delay when operating driving voltage controlling circuit for the exemplary embodiment conceived according to the present invention
Between curve graph；And
Figure 12 is the block diagram of the transceiver for the exemplary embodiment conceived according to the present invention.
Specific embodiment
Hereinafter, it will be described in detail with reference to the accompanying drawings the exemplary embodiment of present inventive concept.
Fig. 1 is the block diagram of the frequency divider for the exemplary embodiment conceived according to the present invention.Fig. 2 conceives according to the present invention
The waveform diagram of the signal of the frequency divider of exemplary embodiment.
Referring to Fig.1, frequency divider (frequency divider) 1000 may include frequency dividing (divide) core circuit 100,
Duty-cycle correction circuit (duty correction circuit) 200 and output circuit 300.Frequency dividing core circuit 100 can connect
It receives clock signal clk and exports the fractional frequency signal S_DIV with frequency dividing.Duty-cycle correction circuit 200 receives fractional frequency signal S_
DIV, and export the differential output signal S_DP and S_DN of the duty ratio that each has correction.Output circuit 300 receives difference
Output signal S_DP and S_DN, and export orthogonal output signal S_I, S_IB, S_Q, S_QB.
Referring to Fig. 2, clock signal clk can be generated based on the signal exported from voltage controlled oscillator VCO.By the way that clock is believed
The frequency of number CLK calculates fractional frequency signal S_DIV divided by particular value, and duty ratio can be such as 40% or 60%.Difference
Output signal S_DP and S_DN may include the first differential output signal S_DP and the second differential output signal S_DN, and difference
Output signal S_DP and S_DN can be the signal of reverse phase relative to each other.Differential output signal S_DP and S_DN can pass through
The duty ratio of fractional frequency signal S_DIV is corrected using duty-cycle correction circuit 200.For example, duty-cycle correction circuit 200 can incite somebody to action
The fractional frequency signal S_DIV that duty ratio is 40% is corrected to the duty ratio with 50%.Orthogonal signalling may include the first output letter
Number S_I and S_IB and the second output signal S_Q and S_QB.First output signal S_I and S_IB all has in-phase component.Example
Such as, the first output signal S_I and S_IB has the phase with the phase portrait of the first differential output signal S_DP.Second output
Signal S_Q and S_QB all have quadrature component.Second output signal S_Q and S_QB all has and the first differential output signal S_
DP orthogonal phase.First output signal S_I and S_IB may include I signal S_I and IB signal S_IB, have between them
The gap (gap) of half period.In other words, I signal S_I and IB signal S_IB is the signal of reverse phase relative to each other.Second
Output signal S_Q and S_QB can also include Q signal S_Q and QB signal S_QB, with the gap of half period between them.
Referring again to Fig. 1, dividing core circuit 100 may include multiple triggers.Multiple triggers may include first
Trigger loop and the second trigger loop.Each trigger loop can receive clock signal clk.For example, the first trigger
Loop and the second trigger loop can export the frequency modulated signal of clock signal clk.By the first trigger loop and second
The frequency modulated signal of trigger loop output can have identical amplitude and different phases.In other words, frequency modulation(PFM) is believed
It number can be exported with phase shifted version.The fractional frequency signal S_DIV generated and the frequency to clock signal clk divides can be with
By being exported to the frequency modulated signal summation by the first trigger loop and the output of the second trigger loop.
The duty cycle correction of fractional frequency signal S_DIV can be with particular value by duty-cycle correction circuit 200.According to this hair
The exemplary embodiment of bright design, duty-cycle correction circuit 200 fractional frequency signal S_DIV can be applied to including resistor and
The primary circuit (for example, resistor-capacitor circuit (RC) filter) of capacitor.Have by the fractional frequency signal S_DIV of primary circuit
There is the primary response with the rise time, and primary response can be the decision level due to multiple phase inverters and have specific
The signal of duty ratio (for example, duty ratio is 50%).In this case, it can be including the resistor in primary circuit
Variable resistance is adjusted, the operational amplifier feedback differential output signal S_DP and S_ by the output voltage of operational amplifier
DN simultaneously receives differential output signal S_DP and S_DN.
Output circuit 300 can receive differential output signal S_DP and S_DN, and export the first orthogonal output letter
Number S_I and S_IB and the second output signal S_Q and S_QB.First output signal S_I and S_IB be and the second output signal S_
Q and S_QB orthogonal output signal.
The exemplary embodiment conceived according to the present invention, output circuit 300 receive differential output signal S_DP and S_DN,
And the first output signal S_I and S_IB is exported by using the buffer for only causing amplitude to change.Output circuit 300 receives difference
Output signal S_DP and S_DN, and the of 90 degree of phase delay is respectively provided with by using buffer and phase-delay network output
Two output signal S_Q and S_QB.
In this case, output circuit 300 can be based on the first output signal S_I and S_IB and the second output signal
S_Q and S_QB postpones phase.In other words, output circuit 300 can control second by executing feedback to output signal
The delay phase of output signal S_Q and S_QB.The exemplary embodiment conceived according to the present invention receives the first output signal S_I
It can be provided to the delay circuit in output circuit 300 with the operational amplifier of S_IB and the second output signal S_Q and S_QB
The delayed control signal that phase is postponed.In other words, output circuit 300 can by the first output signal S_1 and
S_IB and the second output signal S_Q and S_QB executes feedback to postpone phase.
As described in referring to Fig. 9 and Figure 10, the phase delay in output circuit 300 may be to the variation of temperature and voltage
It is sensitive.For this purpose, can by using include according to temperature change and the voltage control circuit of current source that changes provides to control
To the driving voltage for including buffer and delay circuit in output circuit 300.
Above-mentioned frequency divider 1000 in CMOS level can execute frequency dividing based on clock signal clk, and can export and have
Correct the orthogonal signalling of primary duty ratio.Therefore, frequency divider 1000 can provide output signal S_I, S_IB, S_Q and S_QB,
Each output signal has 50% duty ratio, and small frequency is spuious, and orthogonal.
Fig. 3 A and 3B are the circuit diagrams of the frequency dividing core circuit for the exemplary embodiment conceived according to the present invention.
Referring to Fig. 3 A, frequency dividing core circuit 100a may include the first trigger loop 110a, the second trigger loop
120a, multiple trigger 111a, 112a, 113a, 121a, 122a and 123a, NAND door 130 and phase inverter 140.
The exemplary embodiment conceived according to the present invention, the first trigger loop 110a and the second trigger loop 120a points
It Bao Kuo not multiple trigger 111a to 113a and 121a to 123a.For example, trigger can be d type flip flop.Trigger 111a is extremely
Each of 113a and 121a to 123a includes the control terminal for receiving clock signal clk, the D input of input logic value
End, and output logical value Q output end andEnd.It is referred to as data line in the line that input terminal and output are formed.
No matter inputted according to the truth table of trigger when controlling signal (for example, the CLK for being input to control terminal is 0)
To D input terminal logical value how, control signal all keep previous Q orIn addition, when control signal is 1 and to be input to D defeated
When the logical value for entering end is 0, Q exports logical value 0, andExport logical value 1.On the other hand, when control signal is 1 and is inputted
When logical value to D input terminal is 1, Q exports logical value 1, andExport logical value 0.The exemplary reality conceived according to the present invention
Apply example, the first trigger loop 110a and the second trigger loop 120a respectively include multiple trigger 111a to 113a and
121a to 123a, and each of multiple trigger 111a to 113a and 121a to 123a receive clock signal clk or from
The signal of clock signal clk reverse phase.For example, the first trigger loop 110a includes the trigger for receiving clock signal clk
112a, and trigger 111a and 113a from the signal of clock signal clk reverse phase are received respectively.Second trigger loop 120a
Signal including each trigger 121a and 123a for receiving clock signal clk and for receiving from clock signal clk reverse phase
Trigger 122a.In other words, frequency dividing core circuit 100a can receive clock signal clk by direct or reverse phase to execute
Frequency dividing, or by the way that shift clock signal CLK executes frequency dividing step by step at each trigger.
In this case, as shown in Figure 3A, clock signal clk can be by trigger 111a, 113a and 122a reverse phase is simultaneously
It receives.However, the another exemplary embodiment conceived according to the present invention, as shown in Fig. 3 B, clock signal clk and clock inversion
SignalFrequency dividing core circuit 100b can be applied to.
Referring to Fig. 3 B, clock signal clk and clock inversion signalIt can be provided by outside source.Clock inversion letter
NumberThere is the phase gap (phase gap) of half period with clock signal clk.In other words, clock inversion signalRelative to clock signal clk reverse phase.For example, can be provided from the outside source being located at outside frequency dividing core circuit 100b
Two bars input lines, and signal input line can be respectively by clock signal clk and clock inversion signalIt is supplied to point
Frequency core circuit 100b.In this case, different from Fig. 3 A, the control including multiple triggers in core circuit 100b
End receives control signal without reverse phase.For example, referring to Fig. 3 B, trigger 112b, 121b and 123b can receive clock signal
CLK, and trigger 111b, 113b and 122b can receive clock inversion signalHereinafter, in trigger loop 110a,
The embodiment of the operating aspect of 110b, 120a and 120b, Fig. 3 A and 3B is substantially identical, therefore, for ease of description, will
Trigger is described referring to the frequency dividing core circuit 100a of Fig. 3 A.
Referring again to Fig. 3 A, the first trigger loop 110a and the second trigger loop 120a respectively include identical quantity
Trigger.The exemplary embodiment conceived according to the present invention, in the first trigger loop 110a and the second trigger loop 120a
Each may include three triggers.Fractional frequency signal S_DIV passes through the first trigger loop that the end D is fed back and inputted
The trigger 113a of 110a can receive the signal from clock signal clk reverse phase by control terminal.Fractional frequency signal S_DIV passes through D
Hold the trigger 123a for the second trigger loop 120a for being fed back and being inputted that can receive clock signal clk by control terminal.
It is including multiple trigger 111a to 113a and 121a in the first trigger loop 110a and the second trigger loop 120a
Into 123a, receives the trigger of clock signal clk and receive can be with from the trigger of the signal of clock signal clk reverse phase
Alternating sequence is connected to the end D or the end Q.Signal in trigger loop (for example, 110a and 120a) output and input between pass
System will be described in detail in Fig. 4.
Fig. 4 be the signal for being inputted or being exported by frequency dividing core circuit for the exemplary embodiment conceived according to the present invention when
Sequence figure.For ease of description, Fig. 4 is described into for referring to used in Fig. 3 A identifier.
Referring to Fig. 4, clock signal clk is the voltage that logic low-voltage and logic high voltage are repeated in cycle T, and can
To be input to including multiple trigger 111a to 113a in the first trigger loop 110a and the second trigger loop 120a
With the control terminal of 121a to 123a.First trigger loop 110a and the second trigger loop 120a can terminate contracture by D
Frequency signal S_DIV, and QA signal and QB signal are exported respectively.In this case, as shown in figure 4, in QA signal and QB signal
Each period with 5T, therefore, QA signal and QB signal frequency dividing ratio having the same.
Trigger 113a can receive the signal from clock signal clk reverse phase by control terminal, and inputted and terminated by D
Receive fractional frequency signal S_DIV.According to the truth table of trigger 113a, QA1 signal can be exported by Q output end.In other words,
QA1 signal, period 5T, for example, 2T+3T as shown in Figure 4 can be generated in first trigger loop 110a.
Trigger 112a can by control terminal receive clock signal clk, and by D input terminal reception QA1 signal (come
From trigger 113a), to export QA2 signal by Q output.In other words, trigger 112a by control terminal receive from
The signal of clock signal clk reverse phase, and QA2 signal can be exported by receiving clock signal clk via control terminal.Change sentence
Talk about, QA2 signal can be generated in the first trigger loop 110a, the QA2 signal have 5T as the period and with QA1 signal
Phase have 0.5T phase gap.
During above-mentioned generation QA1 signal and QA2 signal, by will apply from the signal of clock signal clk reverse phase
The trigger 112a of trigger 113a can be connected in series to the control terminal and be applied to clock signal clk of trigger 113a
Control terminal, can be generated therebetween with half period phase gap signal.
Trigger 111a can receive the signal from clock signal clk reverse phase by control terminal, and inputted and terminated by D
QA2 signal (coming from trigger 112a) is received, to pass throughOutput end exports QA signal.In other words, the first trigger loop
QA signal can be generated in 110a, which as the period and has and the signal by the generation of reverse phase QA2 signal with 5T
Differ the phase difference of 0.5T.
Similar with the first trigger loop 110a, the second trigger loop 120a also can receive fractional frequency signal S_DIV, and
QB1 signal, QB2 signal and QB signal are generated according to trigger operation.
The exemplary embodiment conceived according to the present invention, the second trigger loop 120a are generated based on clock signal clk
QB1 signal is based on clock inversion signalQB2 signal is generated, and QB signal is generated based on clock signal clk.In other words
It says, the second trigger loop 120a and the first trigger loop 110a are the difference is that the first trigger loop 110a base
In clock inversion signalQA1 signal is generated, QA2 signal is generated based on clock signal clk, and raw according to clock inversion signal
At QA signal.First trigger loop 110a and the second trigger loop 120a has different methods, by these methods, when
Clock signal CLK is applied to multiple trigger 111a to 113a and 121a to 123a.
Therefore, the control terminal of multiple trigger 111a to 113a and 121a to 123a is input to depending on clock signal clk
Sequence and whether be inverted when clock signal clk is input to multiple trigger 111a to 113a and 121a to 123a,
QA1 signal and QB1 signal, QA2 signal and QB2 signal and QA signal and QB signal can have identical frequency dividing ratio and 2.5T
Phase gap.
Dividing core circuit 100a can be by using respectively by the first trigger loop 110a and the second trigger loop
The QA signal and QB signal that 120a is generated generate fractional frequency signal S_DIV by NAND gate 130 and phase inverter 140.Fractional frequency signal
S_DIV can be fed back to the first trigger loop 110a and the second trigger loop 120a.
Referring to Fig. 4, it is the 2.5 of the cycle T of clock signal clk that fractional frequency signal S_DIV, which can have the period of 2.5T,
Times.In addition, fractional frequency signal S_DIV can have 40% since the ratio of the logic high voltage in each period is 40%
Duty ratio.
Above-mentioned frequency dividing core circuit 100,100a and 100b can have a small amount of trigger, and each trigger includes a small amount of
Loop, so that it is spuious to reduce frequency.Compared with the frequency divider for including many loops, frequency is not divided accurately, therefore, mesh
Marking frequency can be with other frequency compounding.However, passing through packet in the frequency divider for the exemplary embodiment conceived according to the present invention
Frequency dividing core circuit is included, by using alternately reception clock signal clk and clock inversion signalMethod obtain have mesh
Mark the fractional frequency signal S_DIV of frequency.
Fig. 5 is the circuit diagram of the duty-cycle correction circuit for the exemplary embodiment conceived according to the present invention.Fig. 6 is basis
The timing diagram for the signal that the duty-cycle correction circuit of the exemplary embodiment of present inventive concept generates.
Referring to Fig. 5, duty-cycle correction circuit 200 may include operation amplifier circuit 210, transistor circuit 220, reverse phase
Device circuit 230 and differential conversion circuit 240.
The exemplary embodiment conceived according to the present invention, duty-cycle correction circuit 200 receive fractional frequency signal S_DIV, and will
The duty cycle correction of fractional frequency signal S_DIV is target duty ratio.For example, being accounted for when the duty ratio of fractional frequency signal S_DIV is 40%
Duty cycle correction can be the duty ratio after 50% and output calibration than correcting circuit 200 by sky.In addition, duty-cycle correction circuit
Homogeneous signal (unity signal) can be converted to duty ratio differential signal (duty differential by 200
signal)。
The exemplary embodiment conceived according to the present invention, operation amplifier circuit 210 can be fed back from duty cycle correction electricity
The the first differential output signal S_DP and the second differential output signal S_DN of the output end output on road 200, and receive and fed back
Signal.Operation amplifier circuit 210 may include: the first RC filter comprising resistor R1 and capacitor C1；And second
RC filter comprising resistor R2 between the input terminal of operational amplifier 211 and the output end of duty-cycle correction circuit and
Capacitor C2.
The exemplary embodiment conceived according to the present invention, operation amplifier circuit 210 can receive with first voltage and
First differential output signal S_DP of second voltage.In this case, the first differential output signal S_DP can have square wave
Form.The first RC filter provided at the inverting input terminal (-) of operational amplifier 211 can receive the first difference output
Signal S_DP and the inverting input terminal (-) that the average value of the first differential output signal S_DP is applied to operational amplifier 211.
Second differential output signal S_DN is also possible to the voltage with square.In this case, it is put in operation
The 2nd RC filter provided at the non-inverting input (+) of big device 211 can receive the second differential output signal S_DN and will
The average value of second differential output signal S_DN is applied to the non-inverting input (+) of operational amplifier 211.
The exemplary embodiment conceived according to the present invention, when anti-phase input and non-inverting input different from each other, operation is put
The control voltage Vctrl changed according to the time is applied to transistor circuit 220 by big device 211.In this case, due to empty short
The principle on road, the anti-phase input and non-inverting input of operational amplifier 211 tend to anti-phase input and non-inverting input with same
The level of a average value.
When anti-phase input and mutually the same non-inverting input, operational amplifier 211 can control control voltage Vctrl tool
There is uniform steady state value.For example, when the first differential output signal S_DP and the second differential output signal S_DN is anti-relative to each other
Xiang Shi, the average value for being applied to the input terminal of operational amplifier 211 can be mutually the same.When control voltage Vctrl is with constant
Be worth (for example, direct current (DC) 1.5V) when, stop by using operation amplifier circuit 210 duty-cycle correction circuit 200 it is anti-
Present loop procedure.Therefore, the equal control voltage Vctrl with steady state value is applied to transistor by operation amplifier circuit 210
Circuit 220, and the first differential output signal S_DP and the second differential output signal S_DN are exported in inverted form.
The exemplary embodiment conceived according to the present invention, transistor circuit 220 may include for receiving fractional frequency signal S_
The first transistor M1 of the DIV and second transistor M2 that can be modeled according to control voltage Vctrl by using variable resistance.
The first transistor M1 may be used as common-source amplifier.Divide for example, the first transistor M1 can be received by gate terminal
Frequency signal S_DIV by fractional frequency signal S_DIV reverse phase, and exports the fractional frequency signal S_DIV being inverted to node A.In Fig. 5,
Node A is connected to the drain electrode end of the first transistor M1.
The voltage for being applied to node A can be corrected with exponential function according to control voltage Vctrl, second transistor M2
The response of form.It in other words, can be according to raw based on the first differential output signal S_DP and the second differential output signal S_DN
At control voltage Vctrl adjust the edge slope of fractional frequency signal S_DIV.Edge slope is when voltage or electric current are when rising
Between or the slope that occurs when transforming to second value from the first value of fall time.For example, second transistor M2 can be according to control
Voltage Vctrl and the variable resistance changed, and the first transistor M1 of transistor circuit 220, second transistor M2 and post
Raw capacitor Cp can be connected in parallel to node A.Therefore, transistor circuit 220 can receive fractional frequency signal S_DIV and export tool
There is the voltage of the edge slope based on time constant, which is variable by will change according to control voltage Vctrl
What resistor was generated multiplied by the value of capacitor parasitics Cp, and adjustable control voltage Vctrl and edge slope, to adjust
Whole duty ratio.
Inverter circuit 230 can receive voltage from node A and by voltage output to node B.For example, inverter circuit
230 may include the multiple phase inverters being connected in series, and can adjust duty ratio based on the decision level of multiple phase inverters.
Referring to Fig. 6, fractional frequency signal S_DIV may include logic high voltage and logic low-voltage, each is with rectangular shape
Formula.Transistor circuit 220 can receive fractional frequency signal S_DIV, by the first transistor M1 by fractional frequency signal S_DIV reverse phase, and
And by second transistor M2 and capacitor parasitics Cp output frequency division signal S_DIV, with numerical index (numerical
Index) the response of form.It therefore, can be with output voltage, shown in the voltage pattern of node A as shown in Figure 6.Later, it is included in
Each phase inverter in inverter circuit 230 can export the voltage lower than decision level as logic low-voltage, and can be with
Output is higher than the voltage of decision level as logic high voltage.
For example, fractional frequency signal S_DIV is transformed to logic low-voltage from logic high voltage in time point ta.Transistor circuit
Fractional frequency signal S_DIV reverse phase can be adjusted the edge slope of fractional frequency signal S_DIV, and have through adjusting to node A output by 220
The fractional frequency signal S_DIV of whole edge slope.For example, after time point ta and before time point tb, by the node in Fig. 6
The signal of A instruction has adjusted edge slope.Time point tb is that the decision level of phase inverter is equal to the time of voltage level
Point.
Later, the square wave that duty ratio is fixed as 50% can be obtained according to decision level by inverter circuit 230.Example
Such as, when odd number phase inverter includes in inverter circuit 230, transistor circuit 220 can by node B export when
Between there is logic high voltage and after time point tb with the periodic square wave of logic low-voltage before point tb.
The time point tc of logic high voltage is transformed to from logic low-voltage in fractional frequency signal S_DIV, fall time may be non-
It is often short or be not present.In time point tc, by using the first of public source amplifier (for example, operational amplifier 211) operation
Transistor M1 cut-off, and when node A swinging earth, the voltage of node A may be declined in the form of step function without
Fall time.
Referring again to Fig. 5, differential conversion circuit 240 can will be input to differential conversion circuit 240 from inverter circuit 230
Individual signals be converted to differential signal and export the differential signal of conversion.Differential signal can be the first differential output signal S_
DP and the second differential output signal S_DN.Each of first differential output signal S_DP and the second differential output signal S_DN
It is with the signal with the phase of the reverse-phase 180 degree of another signal.The exemplary embodiment conceived according to the present invention, difference
Conversion circuit 240 can export the first differential output signal S_DP by using the even number of inverters of series connection, this first
Differential output signal S_DP is with phase identical with the phase of fractional frequency signal S_DIV and with 50% duty ratio.In addition, poor
Point conversion circuit 240 can export the second differential output signal S_DN by using public grid amplifier and phase inverter, this
Two differential output signal S_DN have the phase with the opposite in phase of the first differential output signal S_DP.
Fig. 7 A is the circuit diagram of the output circuit for the exemplary embodiment conceived according to the present invention.Fig. 7 B is according to the present invention
The view for the logic circuit for including in the output circuit of the exemplary embodiment of design.
Referring to Fig. 7 A, output circuit 300 may include input buffer 311, multiple output buffers, for example, first is defeated
Buffer 312 out, the second output buffer 313 and third output buffer 314, phase-delay network 320 and operational amplifier
Circuit 330.
The exemplary embodiment conceived according to the present invention, output circuit 300 can receive the by input buffer 311
One differential output signal S_DP and the second differential output signal S_DN.First output buffer 312 and the second output buffer
313 can amplify the signal amplified by input buffer 311 respectively, and export I signal S_I and IB signal S_IB.In other words,
Can by by the phase of the first differential output signal S_DP and the second differential output signal S_DN fix and by amplitude amplification come
Export I signal S_I and IB signal S_IB.
The exemplary embodiment conceived according to the present invention, phase-delay network 320 can be based on delayed control signal DLY
CTRL carrys out the phase of delay input signal.Third output buffer 314 amplifies the signal exported from phase-delay network 320, and
Export Q signal S_Q and QB signal S_QB.
The exemplary embodiment conceived according to the present invention, operation amplifier circuit 330 can be based on received multiple inputs
Signal S_QP, S_QN, S_IP and S_IN export delayed control signal DLY CTRL.In other words, operation amplifier circuit 330 can
To export delayed control signal DLY CTRL in response to input signal S_QP, S_QN, S_IP and S_IN.In this case, may be used
Biasing circuit to be added to the output end of operational amplifier 331, and biasing circuit can be according to 320 institute of phase-delay network
Voltage is redistributed in the input needed, and by the voltage input redistributed to phase-delay network 320.
By operation amplifier circuit 330 received multiple input signal S_QP, S_QN, S_IP and S_IN be by by
Multiple the output signal S_I, S_IB, S_Q and S_QB that output circuit 300 exports execute feedback and the signal of generation, will be referring to figure
7B describes its details.
Referring to Fig. 7 B, multiple NAND gates 332,333,334 and 335 can receive exported by output circuit 300 it is multiple defeated
Signal S_I, S_IB, S_Q, S_QB out, and generate input signal S_IP, S_IN, S_QP and the S_ of operation amplifier circuit 330
QN.Multiple NAND gates 332 to 335 may include that and can also be included in operation amplifier circuit in output circuit 300
In 330.In other words, multiple NAND gates 332 to 335 may include the second output for including in operation amplifier circuit 330
Buffer 313, between third output buffer 314 and RC filter.
Referring again to Fig. 7 A, the RC filter for being connected to the inverting input terminal (-) of operational amplifier 331 will be due to QP signal
Output caused by S_QP and QN signal S_QN is applied to the inverting input terminal (-) of operational amplifier 331.It is connected to operation amplifier
The RC filter of the non-inverting input (+) of device 331 will be exported due to caused by IP signal S_IP and IN signal S_IN and will be applied to
The non-inverting input (+) of operational amplifier 331.
When the average value of QP signal S_QP and QN signal S_QN and the average value of IP signal S_IP and IN signal S_IN are (logical
Cross each RC filter) when being equal to each other (in other words, when the anti-phase input and non-inverting input of operational amplifier 331 each other
When equal), operational amplifier 331 exports the voltage of delayed control signal DLY CTRL as constant value.When output circuit 300
When output signal is orthogonal signalling, operational amplifier 331 exports delayed control signal DLY CTRL as constant value.For example, working as
I signal S_I and Q signal S_Q are orthogonal, and when IB signal S_IB and QB signal S_QB is orthogonal, is input to operation and puts
The average value of the voltage of the inverting input terminal (-) and non-inverting input (+) of big device 331 is mutually the same.
When delayed control signal DLY CTRL is received as constant value, phase-delay network 320 no longer executes phase
Delay.In other words, it is operated by the delay that operation amplifier circuit 330 executes locked.
Fig. 8 is the timing diagram for the signal of the exemplary embodiment conceived according to the present invention generated by output circuit.In order to
Convenient for explanation, Fig. 8 will be described by using identifier used in Fig. 7 A and Fig. 7 B.
Referring to Fig. 8, I signal S_I and IB signal S_IB reverse phase, and Q signal S_Q and QB signal S_QB relative to each other
Reverse phase relative to each other.I signal S_I and Q signal S_Q can be orthogonal relative to each other, and IB signal S_IB and QB signal S_
QB can be orthogonal relative to each other.In other words, multiple output signal S_I, S_IB, S_Q and the S_ exported from output circuit 300
QB can be mutually orthogonal directions signal.
Be input to operation amplifier circuit 330 multiple signal S_IP, S_IN, S_QP and S_QN be by will from output electricity
Multiple the output signal S_I, S_IB, S_Q and S_QB that road 300 exports are applied to NAND gate 332 to 335 and the signal of acquisition.It is logical
Cross and do so, compared with I signal S_I, from output circuit 300 export Q signal S_Q postpone 90 degree, and with IB signal S_IB
It compares, QB signal S_QB postpones 90 degree.
For example, IP signal S_IP is generated by negative AND (NAND) operation to I signal S_I and Q signal S_Q, by right
The NAND operation of IB signal S_IB and QB signal S_QB generates IN signal S_IN, by Q signal S_Q and IB signal S_IB's
NAND operation generates QP signal S_QP, and generates QN signal S_ by the NAND operation to QB signal S_QB and I signal S_I
QN。
Fig. 9 is the circuit diagram of the output circuit for the exemplary embodiment conceived according to the present invention.
Referring to Fig. 9, output circuit 300 can also include driving voltage controlling circuit 340, and output circuit 300 is defeated
Outlet may be coupled to the input terminal of operation amplifier circuit 330.
The exemplary embodiment conceived according to the present invention, driving voltage controlling circuit 340 can be according to technique, voltage and temperature
(PVT) condition of spending is the first output buffer 312, in the second output buffer 313 and third output buffer 314 at least
One and the offer driving voltage of phase-delay network 320.The phase for the component for including in output circuit 300 can be according to PVT
Condition easily varies.
The another exemplary embodiment conceived according to the present invention, driving voltage controlling circuit 340 can be placed on output electricity
The outside on road 300, and in this case, driving voltage controlling circuit 340, which not only can control, is supplied to output circuit 300
Component driving voltage, but also can control be supplied to frequency dividing core circuit 100 trigger, duty-cycle correction circuit
200 operation amplifier circuit 210, the driving voltage of inverter circuit 230 and differential conversion circuit 240.
Figure 10 is the circuit diagram of the driving voltage controlling circuit 340 for the exemplary embodiment conceived according to the present invention.
Referring to Fig.1 0, driving voltage controlling circuit 340 may include current source 341, diode 342, voltage regulator 343
With reference resistor 344.
The exemplary embodiment conceived according to the present invention, current source 341 can be generated proportional to absolute temperature (PTAT)
Electric current.The generation of PTAT is electric for controlling the driving for being applied to output circuit 300 due to the temperature change in PVT condition
Pressure.Voltage regulator 343 may, for example, be low voltage difference (Low Dropout, LDO) adjuster.
The exemplary embodiment conceived according to the present invention, reference voltage VrefNodal parallel is connected to current source 341 and electricity
Press adjuster 343, and reference voltage VrefNode is also parallel-connected to the diode 342 and reference resistance being serially connected
Device 344.Therefore, reference voltage VrefIt can be expressed as follows by formula 1:
[formula 1]
Vref=IPTAT·Rref+2·(Vov+Vth)
Here, VovAnd VthRespectively indicate the overdrive voltage and threshold voltage of diode 342.
According to above-mentioned reference voltage Vref, voltage regulator 343 can will be supplied to phase according to the driving voltage of temperature change
Position delay circuit 320 and the first output buffer 312.It in other words, can be and according to temperature change offer different voltages
It is not that direct provide supply voltage (VDD) fluctuates to reduce the phase delay due to caused by temperature change.
When Figure 11 is the delay when operating driving voltage controlling circuit for the exemplary embodiment conceived according to the present invention
Between curve graph.
Referring to Fig.1 1, horizontal axis indicates the operational amplifier electricity in the output circuit 300 for controlling phase-delay network 320
Road 330 control signal DLY CTRL voltage, the longitudinal axis indicate by picosecond as unit of delay time.Electricity is controlled in driving voltage
In the case that road 340 is used for duty-cycle correction circuit 200, when driving voltage controlling circuit 340 is to duty-cycle correction circuit 200
When operation amplifier circuit 210 provides driving voltage, horizontal axis can indicate the control voltage exported by operational amplifier 211
Vctrl。
Referring to Fig.1 1, the solid line of curve graph is indicated when being provided by driving voltage controlling circuit 340 to output circuit 300
Delay time when driving voltage, and the dotted line of curve graph indicates to work as to output circuit 300 and provides supply voltage as driving
Delay time when voltage.
The exemplary embodiment conceived according to the present invention, when driving voltage controlling circuit 340 is mentioned to phase-delay network 320
When for driving voltage, according to -40,50 and 110 temperature change, reduced by the time change that phase-delay network 320 postpones,
It therefore can be with the reduction of identification error range.On the other hand, when driving voltage VDD is applied directly to phase-delay network 320,
Since temperature change leads to the surging of delay time, the deterioration of phase delay performance.
Figure 12 is the block diagram of the transceiver of the exemplary embodiment for describing to conceive according to the present invention.
Referring to Fig.1 2, transceiver 2000 may include local oscillator 410, signal source 420, frequency mixer (such as first is mixed
Frequency device 431 and the second frequency mixer 432), adder 440, power amplifier 450 and antenna 460.As shown in figure 12, local oscillations
Device 410 may include frequency divider 1000, filter 411 and buffer 412.
Local oscillator 410 can be based on generating clock signal clk from the received AC signal of signal source 420.Local vibration
The various characteristics that device 410 adjusts clock signal clk are swung, and clock signal clk is exported by frequency mixer 431 and 432.Frequency divider
1000 can realize one in the various embodiments as described in Fig. 1 to Figure 12.In other words, frequency divider 1000 receives
Clock signal clk simultaneously divides the frequency of clock signal clk in frequency dividing core circuit 100, correction duty cycle correction electricity
The duty ratio of clock signal clk in road 200, and it is defeated from output circuit 300 to the first frequency mixer 431 and the second frequency mixer 432
Orthogonal output signal S_I, S_IB, S_Q and S_QB out.
The exemplary embodiment conceived according to the present invention, the first frequency mixer 431 are defeated by the I signal IBB and first in base band
Signal S_1 and S_IB mixing, the second frequency mixer 432 mix Q signal QBB and the second output signal S_Q and S_QB in base band out
Frequently, and mixed frequency signal is output to adder 440 by the first frequency mixer 431 and the second frequency mixer 432.In this case, I
Component can be mutually orthogonal directions with Q.The I/Q signal summed in adder 440 is amplified in power amplifier 450, and
Enlarged IQ signal is exported by antenna 460, as the frequency in radio frequency (RF) frequency band.
The exemplary embodiment of present inventive concept provides a kind of frequency divider, and which reduce due to a small amount of trigger ring pass
The frequency risen is spuious, corrects duty ratio, and export orthogonal signalling, and provide the transceiver including frequency divider.
In addition, the frequency divider for the exemplary embodiment conceived according to the present invention and transceiver including the frequency divider can be
Reduce drawing effect while correcting duty ratio and output orthogonal signalling and frequency is spuious.
Although specifically illustrating and describing present inventive concept, this field referring to exemplary embodiment of the present invention
It, can be with ordinarily skilled artisan will understand that in the case where not departing from the range for the present inventive concept being defined by the following claims
It carry out various modifications.
Claims (20)
1. a kind of frequency divider, comprising:
Core circuit comprising the first trigger loop and the second trigger loop, wherein the first trigger loop and the second touching
Each of hair device loop will be divided by the frequency of the received clock signal of the control terminal of trigger, wherein the core
Electrocardio road is configured that
The second signal output frequency division letter of the first signal and the output of the second trigger loop based on the output of the first trigger loop
Number, the first signal and the second signal frequency dividing ratio having the same and different phases, and pass through the first trigger loop and the
The input terminal feedback division signal of each of two trigger loops；
Duty-cycle correction circuit, receives fractional frequency signal and output is defeated by correcting the difference that the duty ratio of fractional frequency signal generates
Signal out；And
Output circuit, exports the first output signal and the second output signal, the first output signal are put from differential output signal
Big signal, the second output signal are the orthogonal signalling of the first output signal.
2. frequency divider according to claim 1, wherein
First trigger loop and the second trigger loop include the trigger of identical quantity, and each control of trigger
End receives clock signal or the signal from clock signal reverse phase.
3. frequency divider according to claim 2, wherein
Each trigger in first trigger loop is connected in series, and receives first in the first trigger loop of clock signal
The the second trigger connection alternating with each other of trigger and reception from the first trigger loop of the signal of the clock signal reverse phase,
And
Each trigger in second trigger loop is connected in series, and receives first in the second trigger loop of clock signal
The the second trigger connection alternating with each other of trigger and reception from the second trigger loop of the signal of the clock signal reverse phase.
4. frequency divider according to claim 3, wherein
By to the first signal and the second signal execution AND exported respectively from the first trigger loop and the second trigger loop
Operation carrys out output frequency division signal.
5. frequency divider according to claim 1, wherein
The duty ratio of differential output signal, the first output signal and the second output signal is corrected as 50%.
6. frequency divider according to claim 1, wherein
Duty-cycle correction circuit further includes transistor circuit, wherein the input terminal of duty-cycle correction circuit is connected to transistor electricity
Road, and
Differential output signal is fed back to transistor circuit by duty-cycle correction circuit, and by based on differential output signal adjustment point
The edge slope of frequency signal adjusts the duty ratio of fractional frequency signal.
7. frequency divider according to claim 6, wherein
Duty-cycle correction circuit further includes the first operational amplifier, wherein
The output end of the duty-cycle correction circuit of output difference output signal is electrically connected to the input terminal of the first operational amplifier, and
And first the output end of operational amplifier be electrically connected to the input terminal for being entered the duty-cycle correction circuit of fractional frequency signal.
8. frequency divider according to claim 7, wherein
First operational amplifier receives differential output signal and generates the control signal of the edge slope of adjustment fractional frequency signal, and
Transistor circuit adjusts the edge slope of fractional frequency signal in response to the control signal.
9. frequency divider according to claim 8, wherein
Transistor circuit includes the first transistor and second transistor, wherein fractional frequency signal is applied to the grid of the first transistor
End, control signal are applied to the gate terminal of second transistor, and wherein, and transistor circuit is by using the first transistor and the
The edge slope of two-transistor adjustment fractional frequency signal.
10. frequency divider according to claim 9, further includes:
Resistor-capacitor circuit (RC) filter is connected to the output end and the first operational amplifier of duty-cycle correction circuit
Input terminal.
11. frequency divider according to claim 1, further includes:
Driving voltage controlling circuit, according to technique, voltage and temperature (PVT) condition control the driving electricity for being supplied to output circuit
The level of pressure.
12. frequency divider according to claim 11, wherein
Driving voltage controlling circuit further include: current source generates the electric current with temperature proportional；And voltage regulator,
Driving voltage is provided based on the electric current that current source generates.
13. frequency divider according to claim 1, wherein
Output circuit further includes output buffer and phase-delay network, wherein
First output signal is exported by output buffer, and the second output signal is exported by phase-delay network, phase delay
Phase of the circuit based on the first output signal and the second output signal delay difference output signal, so that the second output signal and the
One output signal is orthogonal.
14. frequency divider according to claim 13, wherein
Output circuit further includes operation amplifier circuit, and
Output circuit receives the first output signal and the second output signal in the input terminal of operation amplifier circuit, and puts from operation
The output end of big device circuit exports the signal of the phase delay operations of control phase-delay network to phase-delay network.
15. a kind of frequency divider, comprising:
Core circuit receives clock signal and exports the frequency dividing letter generated and the frequency to clock signal divides
Number；And
Duty-cycle correction circuit receives fractional frequency signal and according to decision level output there is the difference output of new duty ratio to believe
Number,
Wherein, duty-cycle correction circuit is adjusted by executing the differential output signal fed back and based on feedback to differential output signal
The edge slope of fractional frequency signal makes differential output signal have new duty ratio to adjust original duty cycle.
16. frequency divider according to claim 15, wherein
Duty-cycle correction circuit further includes the first operational amplifier,
Wherein, the output end of the duty-cycle correction circuit of output difference output signal is electrically connected to the input of the first operational amplifier
End, the output end of the first operational amplifier are electrically connected to the input terminal for being entered the duty-cycle correction circuit of fractional frequency signal.
17. frequency divider according to claim 16, wherein
First operational amplifier receives differential output signal and generates the control signal of the edge slope of adjustment fractional frequency signal, and
Duty-cycle correction circuit adjusts the edge slope of fractional frequency signal in response to the control signal.
18. a kind of transceiver, comprising:
Core circuit receives clock signal, exports the fractional frequency signal generated and the frequency to clock signal divides,
And including the first trigger loop and the second trigger loop, the first trigger loop and the second trigger loop each
Including multiple triggers；And
Duty-cycle correction circuit, receives fractional frequency signal and output is defeated by correcting the difference that the duty ratio of fractional frequency signal generates
Signal out.
19. transceiver according to claim 18, further includes:
Output circuit, exports the first output signal and the second output signal, the first output signal are put from differential output signal
Big signal, the second output signal are the signals postponed from the first output signal.
20. transceiver according to claim 19, further includes:
Driving voltage controlling circuit,
Wherein, output circuit includes output buffer and phase-delay network, wherein
First output signal is to amplify the signal that generates of differential output signal by output buffer, the second output signal be by
The signal of phase-delay network delay, and the driving voltage of output buffer and phase-delay network controls electricity by driving voltage
Road provides.
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| KR1020180078249A KR102523417B1 (en) | 2017-11-28 | 2018-07-05 | Frequency divider and transceiver including the same |
| KR10-2018-0078249 | 2018-07-05 |
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| CN111464153A (en) * | 2020-05-14 | 2020-07-28 | 京东方科技集团股份有限公司 | Pulse signal generation circuit, pulse signal generation method, clock generation module and display device |
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| CN110460328B (en) * | 2019-09-09 | 2024-06-25 | 广东华芯微特集成电路有限公司 | Arbitrary integer divider and phase-locked loop system |
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Also Published As
| Publication number | Publication date |
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| KR102523417B1 (en) | 2023-04-19 |
| KR20190062136A (en) | 2019-06-05 |
| CN109842410B (en) | 2024-06-04 |
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