CN109830566A - Low-temperature semiconductor bonding method for preparing efficient five-junction solar cell - Google Patents
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- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims abstract description 4
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02E10/00—Energy generation through renewable energy sources
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- Y02E10/544—Solar cells from Group III-V materials
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Abstract
The invention relates to a low-temperature semiconductor bonding method for preparing a high-efficiency five-junction solar cell, which comprises the steps of growing epitaxial layers with different band gaps and lattice matching on GaAs and InP substrates respectively, and then connecting two groups of epitaxial layers in series through the low-temperature semiconductor bonding method to form a 5-junction solar cell. In the bonding process, firstly, a chemical mechanical polishing process is adopted to carry out global planarization treatment on a bonded epitaxial layer, then ammonia water is used for cleaning a high-doped film on the bonding surface, low-energy plasma is used for carrying out activation treatment on the chemical bond on the bonding surface, and the bonding of the epitaxial layer is realized within 30-150 min. The invention has the beneficial effects that: the problem of limitation of lattice mismatch on growth of a high-quality epitaxial layer is solved, and the yield of the multi-junction battery is improved; and secondly, low-temperature bonding is adopted, the process time is short, the photoelectric property of the epitaxial layer cannot be influenced in the bonding process, the process complexity and the cost are reduced, and the commercial production is easy to realize.
Description
Technical field
The invention belongs to physical power source technical fields, more particularly, to a kind of low temperature for preparing efficient five connection solar cell half
Conductor bonding method.
Background technique
Currently, the photoelectric conversion effect of commercialization GaInP/Ga (In) As/Ge three-junction solar battery is 30% (AM0), approach
The limit of the expected efficiency of this kind of battery structure, then the space that is promoted very little.In the past 10 years, 4 knot iii-v sun electricity
Pond is because of the technical bottleneck of lattice mismatch epitaxial growth, and battery efficiency, yield rate are promoted lower than expection, and manufacturing cost is very
It is high.These multijunction cells are difficult to meet the needs of the following aerospace craft.Spectrographic laboratory, U.S. report is ground using bonding techniques
5 knot iii-v solar cells are produced, photoelectric conversion efficiency reaches 36% (AM0), is the current Duo Jie III-V race sun
The world record of cell photoelectric transfer efficiency represents the development trend of multijunction solar cell, but the U.S. one to a certain extent
Directly without disclosing its particular technique or process.
In multijunction solar cell technical field, previously there is document report to be expected to prepare using dilute nitrogen compound GaInAsN etc.
5 connection solar cell of high efficiency, but the crucial skills such as the research of nearly more than ten years has shown that, GaInAsN material component is incorporated to, adulterates control
Art bottleneck can not be broken through always, it is difficult to prepare high-efficiency battery device.Priority patent CN201510956796 proposes brilliant using InP
Piece realizes 5 connection solar cells as substrate, the III-V material of double-face epitaxial difference band gap.Firstly, this method still cannot
Avoid problem brought by lattice mismatch epitaxial growth.It needs first to grow certain thickness Ga in InP substratemIn1-mP group
Divide graded buffer layer, then grows the materials such as AlGaAs and AlGaInP and form the sub- battery of broad-band gap.Numerous studies have demonstrated that
Graded buffer layer can not completely inhibit the threading dislocation formed in lattice mismatch epitaxial process, due to above-mentioned high Al content material
Growth is easy to introduce the deep energy level defect of Al-O in itself, and the presence of threading dislocation defect further increases and deep energy level is inhibited to lack
Sunken difficulty is difficult to prepare the epitaxial layer of high quality；Second, InP substrate mechanical strength is poor, prolonged high growth temperature,
And the stress accumulated due to lattice mismatch will lead to InP chip warpage and even crack；Third, MOCVD epitaxy technical process
In, some reaction gas or generation product and the fixed bracket of substrate are easy to pollute substrate back and damage, at this
The back side of sample carries out continuing epitaxy technique, can produce a very large impact to growth material quality.
Summary of the invention
To solve the above problems, the present invention proposes a kind of cryogenic semiconductor bonding side for preparing efficient five connection solar cell
Method grows different band gap on GaAs and InP substrate respectively, and the III-V race semiconductor material of Lattice Matching, composition are electric
Pond and tunnel junctions interconnected, and grown the N-shaped bonded layer of high-dopant concentration in two groups of epi-layer surfaces.Then by low
Warm bonding semiconductor method, by two groups of epitaxial layer strings.
To solve the above problems, the technical solution of the present invention is as follows: a kind of low temperature for preparing efficient five connection solar cell is partly led
Body bonding method, it is characterised in that the following steps are included:
Step 1: respectively to grow the epitaxial layer of different band gap but Lattice Matching on GaAs and InP substrate, with GaAs and
InP is that the epi-layer surface of substrate grown highly doped n-type Group III-V film as bonded layer；
Step 2: two groups of epitaxial layer epitaxial layers are together in series by the method that cryogenic semiconductor is bonded；Cryogenic semiconductor
The method of bonding specifically includes bonded layer surface preparation, surface active, low-temperature bonding solidification, the bonded layer surface preparation
Including chemically mechanical polishing and chemical cleaning.
Further, referred to the epitaxial layer for growing band gap but Lattice Matching on GaAs substrate in GaAs substrate in step 1
On successively three knot battery structure of epitaxial growth broad-band gap, specifically include (the Al that band gap broadband is 2.0-2.2eVxGa1-x)yIn1-yThe sub- battery structure of P, the 4th tunnelling node structure, band gap are the Al of 1.6-1.8eVxGa1-xAs battery structure, third tunnelling
Junction structure, band gap are the sub- battery structure of GaAs and the second tunnelling node structure of 1.4eV.
Further, band gap is grown in step 1 in InP substrate but the epitaxial layer of Lattice Matching refers in InP substrate
Successively two knot battery structure of epitaxial growth narrow band gap specifically includes the Ga that band gap broadband is 0.65-0.8eV1-xInxAs electricity
Pool structure, the first tunnel junctions, band gap are the In of 1-1.2eV1-xGaxAsyP-y battery structure.
Further, GaAs and InP is that two groups of epi-layer surfaces of substrate grow one layer respectively respectively in the step 1
Thickness is about 0.2-2 μm, and doping concentration reaches 1019cm-3N-shaped GaAs and InP film as bonded layer.
Further, bonding layer surface is specifically included by the method preparation that cryogenic semiconductor is bonded in the middle part of the step 2
Pretreatment, surface active, low-temperature bonding solidification, the bonded layer surface preparation include chemically mechanical polishing and chemical cleaning.
Further, the chemically mechanical polishing, which refers to, carries out chemical machinery throwing using alkalescence polishing liquid para-linkage layer surface
Light, flow liquid rate 8-15ml/s polish revolving speed 30-50rmp/min, polishing time 30s-90s.
Further, the chemical cleaning, which refers to, carries out chemical cleaning to the epitaxial layer after chemically mechanical polishing, and use is dense
Degree is 10% ammonia spirit clean the surface, then rinses both sides with deionized water.
Further, the surface active refers to using Ar pneumoelectric from formation plasma etching to the extension after cleaning
Layer surface carries out chemical bond energy and is activated, air pressure 0.02-0.2mbar, etch period 0.2-2min.
Further, in step 3 high quality epitaxial layer tool will be prepared by the method that cryogenic semiconductor is bonded outside two groups
Body, which refers to, is put into bonder in epitaxial layer of the finger after bonded layer surface preparation, surface activation process, carries out cryogenic semiconductor
It is bonded curing process, naturally rings to room temperature.
Further, the cured technological parameter of the low-temperature bonding: 200-350 DEG C of temperature of bonding temperature applies 300-
The pressure of 2000Pa, bonding time 30min-150min
The present invention has the advantage that and good effect are as follows: (1) proposes that cryogenic semiconductor bonding techniques realize 5 knot sun electricity
Pond solves lattice mismatch to the restricted problem of high quality outer layer growth, it is ensured that give birth to respectively on GaAs and InP substrate
High performance sub- battery is grown, and the two will not influence each other, and be equivalent to and simplify preparation process, is conducive to promote more knot electricity
The yield rate in pond；
(2) propose low-temperature bonding technical solution, bonding temperature be no more than 350 DEG C, the process time at 1 hour or so,
It is matched with the temperature and time for commercially producing Wiring technology process.Therefore, bonding process will not influence the photoelectric properties of epitaxial layer.
And with the shorter bonding technology time instead of the epitaxy technique time longer in previous research, reduce process complexity and
Cost, it is easy to accomplish commercially produce.
Detailed description of the invention
Fig. 1 is the process flow diagram of cryogenic semiconductor bonding method.
Fig. 2 is the ultrasonic scanning figure of cryogenic semiconductor bonded interface.
Specific embodiment
It is illustrated with reference to the accompanying drawing to provided by the present invention.
Fig. 1 is the process flow diagram of cryogenic semiconductor bonding method.It is a kind of to prepare the low of efficient five connection solar cell
Warm bonding semiconductor method, comprising the following steps:
Step 1: respectively to grow the epitaxial layer of different band gap but Lattice Matching on GaAs and InP substrate；With GaAs and
InP is that the epi-layer surface of substrate grown highly doped n-type Group III-V film as bonded layer；
Step 2: high quality epitaxial layer will be prepared outside two groups by the method that cryogenic semiconductor is bonded.
In step 1 with grown on GaAs substrate the epitaxial layer of band gap but Lattice Matching refer to it is successively outer on gaas substrates
Prolong growth three knot battery structure of broad-band gap, specifically includes (the Al that band gap broadband is 2.0-2.2eVxGa1-x)yIn1-yThe sub- battery of P
Structure, the 4th tunnelling node structure, band gap are the Al of 1.6-1.8eVxGa1-xAs battery structure, third tunnelling node structure, band gap
For the sub- battery structure of GaAs of 1.4eV and the second tunnelling node structure.
The epitaxial layer for growing band gap but Lattice Matching in step 1 in InP substrate refers to that successively extension is raw in InP substrate
Long two knot battery structure of narrow band gap specifically includes the Ga that band gap broadband is 0.65-0.8eV1-xInxAs battery structure, the
One tunnel junctions, band gap are the In of 1-1.2eV1-xGaxAsyP-y battery structure.
It is about 0.2-2 μ that GaAs and InP grows a layer thickness for two groups of epi-layer surfaces of substrate respectively respectively in step 1
M, doping concentration reach 1019cm-3N-shaped GaAs and InP film as bonded layer.
By the way that the method preparation that cryogenic semiconductor is bonded specifically includes bonded layer surface preparation, surface is lived in the middle part of step 2
Change, low-temperature bonding solidification, bonded layer surface preparation includes chemically mechanical polishing and chemical cleaning.
Chemically mechanical polishing refers to be chemically-mechanicapolish polished using alkalescence polishing liquid para-linkage layer surface, flow liquid rate 8-
15ml/s polishes revolving speed 30-50rmp/min, polishing time 30s-90s.
Chemical cleaning, which refers to, carries out chemical cleaning to the epitaxial layer after chemically mechanical polishing, uses concentration for 10% ammonium hydroxide
Then solution clean the surface rinses both sides with deionized water.
Surface active refers to using Ar pneumoelectric from formation plasma etching to the epi-layer surface after cleaning
It learns bond energy to be activated, air pressure 0.02-0.2mbar, etch period 0.2-2min.
High quality epitaxial layer will be prepared outside two groups by the method that cryogenic semiconductor is bonded in step 2 to specifically refer to
Refer to that the epitaxial layer after bonded layer surface preparation, surface activation process is put into bonder, carries out cryogenic semiconductor bonding solidification
Processing, naturally rings to room temperature.
The cured technological parameter of low-temperature bonding: 200-350 DEG C of temperature of bonding temperature applies the pressure of 300-2000Pa, key
Close time 30min-150min.
Fig. 2 is the ultrasonic scanning figure of cryogenic semiconductor bonded interface, technique that two groups of epitaxial layers are recorded using the application and
The parameter of optimization is bonded, and bonded interface obtains good bonding effect without obvious cavity.
Embodiment 1
A kind of cryogenic semiconductor bonding method preparing efficient five connection solar cell, includes the following steps
1. the sub- battery structure that two groups of epitaxial layers have respectively constituted different band gap；
1.1 successively three knot battery structures of epitaxial growth broad-band gap on gaas substrates, specifically including band gap broadband is
2.0-2.2eV (AlxGa1-x)yIn1-yThe sub- battery structure of P, the 4th tunnelling node structure, band gap are the Al of 1.6-1.8eVxGa1-xAs
Sub- battery structure, third tunnelling node structure, band gap are the sub- battery structure of GaAs and the second tunnelling node structure of 1.4eV.?
Two tunnel junctions surface extension a layer thickness are about 0.2-2 μm, and doping concentration reaches 1018-1020cm-3N-shaped GaAs film, as
Bonded layer.The epitaxial film materials of above-mentioned growth are Lattice Matching.
The successively two knot battery structure of epitaxial growth narrow band gap in InP substrate, specifically including band gap broadband is 0.65-
The Ga of 0.8eV1-xInxAs battery structure, the first tunnel junctions, band gap are the In of 1-1.2eV1-xGaxAsyP-y battery structure,
Finally on its surface, extension a layer thickness is about 0.2-2 μm, and doping concentration reaches 1018-1020cm-3N-shaped InP film, as
Bonded layer.The epitaxial film materials and InP substrate of above-mentioned growth are also Lattice Matching.
1.2 in InP substrate successively two knot battery structure of epitaxial growth narrow band gap, specifically including band gap broadband is
The Ga of 0.65-0.8eV1-xInxAs battery structure, the first tunnel junctions, band gap are the In of 1-1.2eV1-xGaxAsyP-y battery
Structure, finally on its surface, extension a layer thickness is about 0.2-2 μm, and doping concentration reaches 1018-1020cm-3N-shaped InP film,
As bonded layer.The epitaxial film materials and InP substrate of above-mentioned growth are also Lattice Matching.
Two groups of epitaxial layers have respectively constituted the sub- battery structure of different band gap, and the lattice constant between two groups of materials is not
Match.Cryogenic semiconductor bonding method proposed by the present invention is exactly structure that the epitaxial structure of this two groups of lattice mismatches is directly together in series
At the basic structure of 5 connection solar cells.
2. being by the concrete scheme for preparing high quality epitaxial layer outside two groups by the method that cryogenic semiconductor is bonded:
2.1, the bonded layer on two groups of epitaxial structure surfaces is chemically-mechanicapolish polished, polishing process uses alkaline polishing
Liquid, flow liquid rate 8-15ml/s polish revolving speed 30-50rmp/min, polishing time 30s-90s.
2.2, chemical cleaning is carried out to the epitaxial layer after chemically mechanical polishing, table is cleaned using 10% ammonia spirit of concentration
Then both sides are rinsed with deionized water in face.
2.3, chemical bond energy is carried out to the bonding layer surface after cleaning and is activated, using Ar pneumoelectric from formation plasma
Etching bonding layer surface, air pressure 0.02-0.2mbar, etch period 0.2-2min.
2.4, pretreated two groups of epitaxial structures are put into bonder, cryogenic semiconductor is carried out and is bonded curing process.Very
Pneumatics reaches by force 10-2Pa-10-3After Pa, is heated up with the speed of 10 DEG C/min, reach 200-350 DEG C of bonding temperature, apply simultaneously
The pressure of 300-2000Pa, solidification bonding time are 30min-150min, then naturally ring to room temperature.
Epitaxial wafer is taken out, the device technologies such as subsequent substrate desquamation, photoetching, electrode preparation is carried out, ultimately forms 5 knots too
Positive electricity pond.
Embodiment 2
A kind of cryogenic semiconductor bonding method preparing efficient five connection solar cell, comprising the following steps:
1, using with a thickness of 350 μm, crystal orientation (100), doping concentration is about 1017-1018cm-3N-shaped GaAs chip conduct
Substrate, using gas phase epitaxy of metal organic compound technique (MOVPE) on it extension difference band gap width III-V material constitute three
Knot battery structure, specifically includes: band gap broadband is the (Al of 2.1eVxGa1-x)yIn1-yThe sub- battery structure of P, the 4th tunnelling junction
Structure, band gap are the Al of 1.7eVxGa1-xAs battery structure, third tunnelling node structure, band gap are the sub- battery knot of GaAs of 1.4eV
Structure and the second tunnelling node structure.The concrete content (x, y numerical value) of the components such as wherein Al, Ga, In can have material band gap to calculate
It arrives.Tunnel junctions are only mainly more than ten nanometer by thickness, and doping concentration reaches 1019cm-3The iii-vs such as GaInP, AlGaAs
Semiconductor material is constituted.It is about 1 μm in second tunnel junctions surface extension a layer thickness, doping concentration reaches 1019cm-3N-shaped
GaAs film, as bonded layer.
2, it is about 350 μm using thickness, crystal orientation (100), doping concentration is about 1017-1018cm-3P-type InP chip conduct
Substrate, using gas phase epitaxy of metal organic compound technique (MOVPE) on it extension difference band gap width III-V material constitute two
Knot battery structure, specifically includes: band gap broadband is the Ga of 0.7eV1-xInxAs battery structure, the first tunnel junctions, band gap are
1.05eV In1-xGaxAsyP-y battery structure.The concrete content (x, y numerical value) of the components such as wherein Ga, In, As, P can have
Material band gap is calculated.Finally on its surface, extension a layer thickness is about 1 μm, and doping concentration reaches 1019cm-3N-shaped InP
Film, as bonded layer.First tunnel junctions are only mainly more than ten nanometer by thickness, and doping concentration reaches 1019cm-3's
The III-V group semi-conductor materials such as InGaAs, GaAsSb are constituted.
3, the bonded layer on above-mentioned two groups of epitaxial structure surfaces is pre-processed.Chemical-mechanical polisher will be used first
Global planarizartion processing is carried out to the surface bond layer of two groups of epitaxial structures.The alkaline polishing for being about 10 using PH in polishing process
Liquid, flow liquid rate 12ml/s polish revolving speed 40rmp/min, polishing time 60s, while being applied by air pump rubbing head to sample
The pressure of about 30kg weight.Chemical cleaning is carried out to sample surfaces after polishing, surface is cleaned using 10% ammonia spirit of concentration, when
Between 10s, then with deionized water rinse both sides.Surface chemistry bond energy activation processing finally is carried out to the bonded layer after cleaning.It is living
Change device chamber to vacuumize, when pressure reaches 10-2Be passed through Ar gas after Pa, and apply about rf electric field, using ionization formed etc. from
Daughter etching bonding layer surface, air pressure is 0.1mbar, etch period 1min during this.
4, pretreated two groups of epitaxial structures are put into bonder, cryogenic semiconductor is carried out and is bonded curing process.Chamber
Vacuum pressure reaches 10-3After Pa, is heated up with the speed of 10 DEG C/min, constant temperature is kept after reaching 300 DEG C, while applying 300-
The pressure of 2000Pa, solidification bonding time are 60min, then naturally ring to room temperature.
Epitaxial wafer is taken out, the device technologies such as subsequent substrate desquamation, photoetching, electrode preparation is carried out, ultimately forms 5 knots too
Positive electricity pond.
Compared with prior art: the invention proposes specific bonding technology schemes, i.e., first using chemically mechanical polishing
The epitaxial layer of technique para-linkage carries out global planarizartion processing, is then cleaned with the highly doped film in ammonium hydroxide para-linkage surface,
Low energy plasma para-linkage surface chemistry key is activated again, completes above-mentioned bonding surface pretreating process process
Afterwards, using 200-350 DEG C of temperature, apply the pressure of 300-2000Pa, the key of epitaxial layer, electricity are realized in 30min-150min
Epitaxial structure in pond passes through Lattice Matching epitaxy technology and is grown, and then solves different band gap materials by bonding techniques
The problem of lattice mismatch, can prepare high quality epitaxial layer；Bonding surface activating pretreatment technology is used simultaneously, using only not surpassing
Spend 350 DEG C of bonding temperature, shorter bonding curing time, so that it may realize that the series connection between different sub- battery packs therefore will not
Have an adverse effect to pn-junction in epitaxial layer, also simplify technique, there is the technical prospect realized and commercially produced.
An example of the present invention is described in detail above, but the content is only preferable implementation of the invention
Example, should not be considered as limiting the scope of the invention.It is all according to all the changes and improvements made by the present patent application range
Deng should still be within the scope of the patent of the present invention.
Claims (7)
1. a kind of cryogenic semiconductor bonding method for preparing efficient five connection solar cell, it is characterised in that the following steps are included:
Step 1: respectively to grow the epitaxial layer of different band gap but Lattice Matching, two groups of epi-layer surfaces on GaAs and InP substrate
Highly doped n-type Group III-V film be grown as bonded layer；
Step 2: two groups of epitaxial layers are together in series by the method that cryogenic semiconductor is bonded；The method of cryogenic semiconductor bonding
Bonded layer surface preparation, surface active, low-temperature bonding solidification are specifically included, the bonded layer surface preparation includes chemical machine
Tool polishing and chemical cleaning.
2. a kind of cryogenic semiconductor bonding method for preparing efficient five connection solar cell according to claim 1, feature
Being in the step 1 that GaAs and InP grows a layer thickness for two groups of epi-layer surfaces of substrate respectively respectively is about 0.2-2 μ
M, doping concentration reach 1019cm-3N-shaped GaAs and InP film as bonded layer.
3. a kind of cryogenic semiconductor bonding method for preparing efficient five connection solar cell according to claim 1 or 2, special
Sign is that the chemically mechanical polishing is referred to and chemically-mechanicapolish polished using alkalescence polishing liquid para-linkage layer surface, flow liquid rate
8-15ml/s polishes revolving speed 30-50rmp/min, polishing time 30s-90s.
4. a kind of cryogenic semiconductor bonding method for preparing efficient five connection solar cell according to claim 3, feature
It is that the chemical cleaning refers to and chemical cleaning is carried out to the epitaxial layer after chemically mechanical polishing, uses concentration molten for 10% ammonium hydroxide
Then liquid clean the surface rinses both sides with deionized water.
5. a kind of cryogenic semiconductor bonding method for preparing efficient five connection solar cell according to claim 1,2 or 4,
Be characterized in that the surface active refer to using Ar pneumoelectric from formed plasma etching to the epi-layer surface after cleaning into
Row chemistry bond energy is activated, air pressure 0.02-0.2mbar, etch period 0.2-2min.
6. a kind of cryogenic semiconductor bonding method for preparing efficient five connection solar cell according to claim 1,2 or 4,
It is characterized in that low-temperature bonding solidifies to refer to and referring to that epitaxial layer after bonded layer surface preparation, surface activation process is put into bonding
Machine carries out cryogenic semiconductor and is bonded curing process, naturally rings to room temperature.
7. a kind of cryogenic semiconductor bonding method for preparing efficient five connection solar cell according to claim 8, feature
Be the cured technological parameter of the low-temperature bonding: 200-350 DEG C of temperature of bonding temperature applies the pressure of 300-2000Pa, key
Close time 30min-150min.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112687759A (en) * | 2020-12-25 | 2021-04-20 | 中国电子科技集团公司第十八研究所 | Low-temperature semiconductor direct bonding method based on surface modification and activation |
| CN112993135A (en) * | 2020-07-01 | 2021-06-18 | 重庆康佳光电技术研究院有限公司 | Display panel manufacturing method, display panel and display device |
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