CN109818614B - Time sequence control method, time sequence control chip and display device - Google Patents
Time sequence control method, time sequence control chip and display device Download PDFInfo
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- CN109818614B CN109818614B CN201811588005.5A CN201811588005A CN109818614B CN 109818614 B CN109818614 B CN 109818614B CN 201811588005 A CN201811588005 A CN 201811588005A CN 109818614 B CN109818614 B CN 109818614B
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Abstract
The application discloses a time sequence control method, a time sequence control chip and a display device, wherein the time sequence control method is used for the time sequence control chip, the time sequence control chip comprises a phase-locked loop, and the phase-locked loop comprises at least two charge pumps with different charge pump coefficients; the time sequence control method comprises the following steps: generating a first clock signal according to an initial clock signal or a feedback clock signal received by an input end of a phase-locked loop; determining a charge pump coefficient of the phase-locked loop according to the initial clock signal and the first clock signal; and selecting the corresponding charge pump to participate in phase locking according to the charge pump coefficient, and generating a second clock signal.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a timing control method, a timing control chip and a display device.
Background
The statements herein merely provide background information related to the present application and may not necessarily constitute prior art. A timing control chip (TCON IC) is an important component in a display device, and controls a driving timing of the display device to realize normal display of a screen. During the operation of the TCON IC, a corresponding target clock signal is generated according to an initial clock signal input from the outside to ensure the synchronization between the external clock and the internal clock, so as to capture and process the display data correctly.
Because the phase locking of the phase-locked loop needs a certain time, when the initial clock signal input from the outside changes greatly, the phase-locked state will be generated for a long time, which causes the abnormal display of the display device.
Disclosure of Invention
The present application is directed to a timing control method, which realizes fast and accurate phase locking to ensure normal display of a picture in a display device.
The time sequence control method is used for a time sequence control chip, the time sequence control chip comprises a phase-locked loop, and the phase-locked loop comprises at least two charge pumps with different charge pump coefficients; the time sequence control method comprises the following steps:
generating a first clock signal according to an initial clock signal or a feedback clock signal received by the input end of the phase-locked loop;
determining a charge pump coefficient of a phase-locked loop according to the initial clock signal and the first clock signal;
and selecting a corresponding charge pump to participate in phase locking according to the charge pump coefficient, and generating a second clock signal.
Optionally, after the step of selecting a corresponding charge pump according to the charge pump coefficient, controlling the charge pump to participate in phase locking, and generating a second clock signal, the timing control method further includes the steps of:
comparing the frequency of the second clock signal with a preset frequency range;
when the frequency of the second clock signal is within the preset frequency range, generating a target clock signal according to the second clock signal, and outputting the target clock signal;
and when the frequency of the second clock signal is out of the preset frequency range, feeding the second clock signal serving as a feedback clock signal back to the input end of the phase-locked loop, and returning to execute the step of generating the first clock signal according to the feedback clock signal received by the input end of the phase-locked loop.
Optionally, after the step of feeding back the second clock signal to the input terminal as a feedback clock signal when the frequency of the second clock signal is outside the preset frequency range, the timing control method further includes the steps of:
accumulating the feedback times of the second clock signal;
comparing the feedback times with preset times;
when the feedback times are greater than the preset times, generating a prompt signal; or the like, or, alternatively,
accumulating the lock losing time length from the time when the input end of the phase-locked loop receives the initial clock signal to the time when the second clock signal is fed back to the input end as the feedback clock signal;
comparing the lock losing duration with a preset duration;
and when the lock losing duration is greater than the preset duration, generating a prompt signal.
Optionally, the step of generating the first clock signal according to the feedback clock signal received by the input terminal of the phase-locked loop includes:
dividing the frequency of the feedback clock signal according to a target frequency division multiple N to generate a third clock signal;
generating a first clock signal according to the third clock signal;
wherein a frequency of the third clock signal is 1/N of a frequency of the feedback clock signal, and a frequency of the first clock signal is equivalent to a frequency of the third clock signal.
Optionally, the step of determining the charge pump coefficient of the phase-locked loop according to the initial clock signal and the first clock signal includes:
acquiring a frequency difference value of the first clock signal and the initial clock signal;
comparing the absolute value of the frequency difference value with a first frequency threshold value;
determining a first coefficient as the charge pump coefficient when the absolute value of the frequency difference is greater than the first frequency threshold;
when the absolute value of the frequency difference is smaller than or equal to the first frequency threshold, comparing the absolute value of the frequency difference with a second frequency threshold;
determining a second coefficient as the charge pump coefficient when the absolute value of the frequency difference is greater than the second frequency threshold;
determining a third coefficient as the charge pump coefficient when the absolute value of the frequency difference is less than or equal to the second frequency threshold;
wherein the first frequency threshold is greater than the second frequency threshold, the first coefficient is greater than the second coefficient, and the second coefficient is greater than the third coefficient.
In order to achieve the above object, the present application further provides a timing control chip, the timing control chip includes a phase-locked loop, the phase-locked loop includes a charge pump assembly, the charge pump assembly includes a selection circuit and at least two charge pumps, the charge pumps connect to the output terminal of the selection circuit, and each the charge pumps have different charge pump coefficients.
Optionally, the phase-locked loop includes a phase detector and a voltage-controlled oscillator, an input end of the phase detector is configured to receive the initial clock signal or the feedback clock signal, and an output end of the phase detector is connected to an input end of the selection circuit; the input end of the voltage-controlled oscillator is connected to the output end of the charge pump, and the output end of the voltage-controlled oscillator is set to output a target clock signal.
Optionally, the timing control chip includes a frequency divider, an input end of the frequency divider is connected to an output end of the voltage-controlled oscillator, and an output end of the frequency divider is connected to an input end of the phase detector.
Optionally, the selection circuit includes a judgment sub-circuit, a control sub-circuit, and a switch sub-circuit, an input end of the judgment sub-circuit is connected to an output end of the phase detector, and the judgment sub-circuit is configured to generate a control signal according to a frequency difference output by the phase detector; the input end of the control sub-circuit is connected with the output end of the judgment sub-circuit; the input end of the switch sub-circuit is connected with the output end of the control sub-circuit, the switch sub-circuit comprises at least two switches which are arranged in one-to-one correspondence with the charge pumps, and the switch sub-circuit controls the on or off of each switch according to the control signal.
In order to achieve the above object, the present application provides a display device, the display device includes display panel and sequential control chip, sequential control chip with the display panel electricity is connected, sequential control chip includes the phase-locked loop, the phase-locked loop includes charge pump assembly, charge pump assembly includes selection circuit and two at least charge pumps, charge pump connect in selection circuit's output, and each charge pump has different charge pump coefficients.
In the technical scheme of the application, the time sequence control method is used for a time sequence control chip, the time sequence control chip comprises a phase-locked loop, the phase-locked loop comprises at least two charge pumps with different charge pump coefficients, and the time sequence control method comprises the following steps: generating a first clock signal according to an initial clock signal or a feedback clock signal received by an input end of a phase-locked loop; determining a charge pump coefficient of the phase-locked loop according to the initial clock signal and the first clock signal; and selecting the corresponding charge pump to participate in phase locking according to the charge pump coefficient, and generating a second clock signal. In the application, the phase-locked loop comprises at least two charge pumps with different charge pump coefficients, so that different charge pumps can be selected to participate in phase locking according to the change of a first clock signal and an initial clock signal, so as to change the compensation amplitude of the phase-locked loop to the clock signal frequency in each cycle, thereby improving the speed and the precision of phase locking, improving the phase locking effect and ensuring the normal display of the display device.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a diagram illustrating an exemplary timing control chip;
FIG. 2 is a schematic diagram of the phase-locked loop of FIG. 1;
FIG. 3 is a schematic flow chart diagram illustrating a timing control method according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a timing control chip according to an embodiment of the present disclosure;
FIG. 5 is a schematic flow chart diagram illustrating another embodiment of a timing control method according to the present application;
fig. 6 is a schematic diagram of a frequency of a second clock signal in the timing control chip of fig. 1 and 4 varying with time.
The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that if directional indications (such as up, down, left, right, front, and back … …) are referred to in the embodiments of the present application, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present application, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the meaning of "and/or" appearing throughout is to include three juxtapositions, exemplified by "A and/or B" including either scheme A, or scheme B, or a scheme in which both A and B are satisfied. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
In one example, as shown in fig. 1, the TCON IC includes a phase locked loop 100 'and a data processing module 200'. Wherein the phase locked loop 100' is based on the initial clock signal CLKoGenerating a target clock signal CLKfAnd the target clock signal CLK is providedfOutput to the data processing module 200'. The data processing module 200' generates a target clock signal CLKfCapture initial display DATA under control ofoProcessed to generate target display DATA DATAfTo drive the display of the picture in the display panel of the display device. As shown in FIG. 2, the PLL 100' packetComprising a phase detector 110 ', a charge pump 120', a voltage controlled oscillator 130 'and a frequency divider 140' connected in sequence to form a loop, wherein an initial clock signal CLKoThe input of the self-phase detector 110 'enters the phase locked loop 100', and the target clock signal CLKfOutput from the phase locked loop 100 'via the output of the voltage controlled oscillator 130'. When the clock signal is circulating in the phase locked loop 100 ', the phase detector 110' acquires the initial clock signal CLK in the current stateoAnd a third clock signal, wherein the third clock signal is generated by the second clock signal generated by the voltage controlled oscillator 130 'in the previous cycle after being divided by the divider 140', and the phase detector calculates the third clock signal from the initial clock signal CLKoThe charge pump 120 ' generates a corresponding adjustment voltage Δ V according to the frequency difference Δ F, the adjustment voltage Δ V controls the voltage controlled oscillator 130 ' to output the second clock signal generated in the current cycle, where Δ V is M × Δ F, M is a charge pump coefficient of the charge pump 120 ', and the frequency CLK of the second clock signal after the current cycle is CLK2F2 ═ N × Δ V + F2 ', N is the vco coefficient, and F2' is the frequency of the second clock signal generated in the previous cycle. As can be seen from the above description, in the phase locked loop 100 ' of the present example, the frequency of the second clock signal generated by the voltage controlled oscillator 130 ' satisfies F2 ═ M × N × Δ F + F2 ', that is, when the charge pump coefficient M and the voltage controlled oscillator coefficient N are constant, the frequency difference M × N × Δ F that can be compensated each time is also fixed. If the initial clock signal CLKoWhen a large change occurs, the pll 100' will be in an unlocked state for a long time, which is likely to cause an abnormal display.
The application provides a time sequence control method, wherein the charge pump coefficient of a phase-locked loop is variable, so that the charge pump coefficient can be changed according to the change of an initial clock signal, and the speed and the accuracy of phase locking are improved.
In an embodiment of the present application, as shown in fig. 3 and 4, the timing control method is applied to a timing control chip, the timing control chip includes a phase-locked loop 100, the phase-locked loop 100 includes at least two charge pumps with different charge pump coefficients; the time sequence control method comprises the following steps:
step S100, generating a first clock signal according to an initial clock signal or a feedback clock signal received by an input end of a phase-locked loop;
the input terminal of the phase-locked loop is arranged to receive an initial clock signal CLK from an external inputoAfter phase-locked by phase-locked loop, the internally generated target clock signal CLK is generatedfAnd an externally inputted initial clock signal CLKoAnd synchronizing to provide timing reference for the data processing modules in the TCON IC to ensure correct processing of the display data. During the first cycle, an input terminal of the phase-locked loop receives an initial clock signal and generates a first clock signal according to the initial clock signal. Specifically, the initial clock signal may be directly used as the first clock signal, or the initial clock signal may be subjected to low-pass filtering or the like, and then the initial clock signal with the signal-to-noise ratio improved and the waveform optimized is used as the first clock signal. In the following cycle, the input end of the phase-locked loop receives an initial clock signal and a feedback clock signal, where the received initial clock signal provides a reference for determining a subsequent charge pump coefficient, that is, the charge pump coefficient is related to the initial clock signal, and the received feedback clock signal provides a reference for generating a first clock signal in the current cycle, that is, in each cycle (except for the first cycle) of the phase-locked loop, the first clock signal changes with the change of the feedback clock signal to adapt to the phase-locking requirement.
Step S200, determining a charge pump coefficient of the phase-locked loop according to the initial clock signal and the first clock signal;
according to the description of the example, the pll can compensate for the frequency difference at each time by M × N × Δ F, where M is the charge pump coefficient and N is the vco coefficient. In order to enable the frequency difference value compensated by the phase-locked loop each time to meet the requirements of efficiency and precision, the charge pump coefficient M of the phase-locked loop is determined according to the initial clock signal and the first clock signal. Specifically, the charge pump coefficient M may be determined by calculating a frequency difference or a phase difference between the initial clock signal and the first clock signal. Generally, when the frequency difference or phase difference between the initial clock signal and the first clock signal is large, i.e. the deviation from the phase-locked state is serious, a large charge pump coefficient M is determined to increase the frequency difference compensated in each cycle, thereby increasing the phase-locked speed; when the frequency difference or the phase difference between the initial clock signal and the first clock signal is small, that is, relatively close to the phase-locked state, a small charge pump coefficient M is determined to reduce the compensated frequency difference in each cycle, which is helpful to improve the accuracy of phase-locked operation and effectively avoid the over-compensation condition.
Step S300, according to the charge pump coefficient, selecting a corresponding charge pump to participate in phase locking, and generating a second clock signal.
After determining the charge pump coefficients, selecting a corresponding charge pump according to the charge pump coefficients, and connecting the charge pump in the phase-locked loop to participate in phase locking, thereby generating a second clock signal. The second clock signal can be generated by a voltage-controlled oscillator, and the clock signals inside and outside the phase-locked loop are synchronized through one or more times of compensation, so that the data processing module of the TCON IC can process display data according to a correct time sequence.
In this embodiment, the timing control method is applied to a timing control chip, the timing control chip includes a phase-locked loop 100, the phase-locked loop 100 includes at least two charge pumps with different charge pump coefficients, and the timing control method includes the following steps: generating a first clock signal according to an initial clock signal or a feedback clock signal received by an input terminal of the phase-locked loop 100; determining a charge pump coefficient of the phase-locked loop 100 according to the initial clock signal and the first clock signal; and selecting the corresponding charge pump to participate in phase locking according to the charge pump coefficient, and generating a second clock signal. The phase-locked loop 100 includes at least two charge pumps with different charge pump coefficients, so that different charge pumps can be selected to participate in phase locking according to the change of the first clock signal and the initial clock signal, so as to change the compensation amplitude of the phase-locked loop for the clock signal frequency in each cycle, thereby increasing the speed and precision of phase locking, improving the phase locking effect, and ensuring the normal display of the display device.
Optionally, as shown in fig. 5, in another embodiment of the present application, after step S300, the timing control method further includes the following steps:
step S400, comparing the frequency of the second clock signal with a preset frequency range;
step S510, when the frequency of the second clock signal is within a preset frequency range, generating a target clock signal according to the second clock signal, and outputting the target clock signal;
and step S520, when the frequency of the second clock signal is out of the preset frequency range, feeding the second clock signal serving as a feedback clock signal back to the input end of the phase-locked loop, and returning to the step of generating the first clock signal according to the feedback clock signal received by the input end of the phase-locked loop.
Specifically, in the TCON IC, a target clock signal CLK required for the data processing modulefThe frequency of (a) may not be a determined value but within a certain preset frequency range, in which case the data processing module can correctly capture the initial display data and process it to generate the target display data. In a specific example, the predetermined frequency range may be at the initial clock signal CLKoThe frequency range of about 20 kHz. In order to improve the processing efficiency of the phase-locked loop, after the second clock signal is generated, whether the clock signal needs to be continuously circulated in the phase-locked loop to compensate for the frequency difference is determined by comparing the frequency of the second clock signal with a preset frequency range. When the frequency of the second clock signal is within the preset frequency range, which indicates that the second clock signal generated by the phase-locked loop at the moment meets the requirement of data processing, a target clock signal CLK is generated according to the second clock signalfAnd outputs a target clock signal. Specifically, the second clock signal may be directly used as the target clock signal CLKfAlternatively, the second clock signal may be subjected to frequency multiplication, filtering, and the like, and then the processed second clock signal may be used as the target clock signal CLKfTo meet the requirements of display driving. When the frequency of the second clock signal is outside the preset frequency range, it indicates that the second clock signal is still in an out-of-lock state, the frequency of the second clock signal cannot meet the processing requirement of display data, and the second clock signal needs to continuously circulate in the phase-locked loop to compensate the frequency difference, so that the second clock signal is fed back to the input end of the phase-locked loop as a feedback clock signal, and the step of generating the first clock signal according to the feedback clock signal received by the input end of the phase-locked loop is returned to execute, that is, the first clock signal is generated according to the fed-back second clock signal, and the frequency difference is continuously compensated until the generated second clock signal meets the requirement of display driving.
Optionally, in another embodiment of the present application, in order to avoid abnormal operation of the display device caused by the phase-locked loop being in the lock-out state for a long time when the phase-locked loop cannot adjust synchronization of the internal and external clock signals through self negative feedback, the number of cycles or the lock-out time in the phase-locked process is monitored to determine the operation state of the phase-locked loop, so that relevant personnel can maintain the TCON IC in time, and the normal operation of the display device is ensured.
In a specific example, after the step of feeding back the second clock signal as the feedback clock signal to the input terminal when the frequency of the second clock signal is outside the preset frequency range, the timing control method further includes the steps of:
step S611, accumulating the feedback times of the second clock signal;
step S612, comparing the feedback times with preset times;
and step S613, generating a prompt signal when the feedback times are greater than the preset times.
In this example, it is determined whether a situation that synchronization of internal and external clock signals cannot be effectively adjusted through self negative feedback occurs by monitoring the number of cycles in the phase-locked loop, and when the number of feedback times is greater than a preset number of times, that is, when effective phase locking cannot be performed after multiple cycles, a prompt signal is generated to prompt related personnel.
In another specific example, after the step of feeding back the second clock signal as the feedback clock signal to the input terminal when the frequency of the second clock signal is outside the preset frequency range, the timing control method further includes the steps of:
step S621, accumulating the lock losing time length from the time when the input end of the phase-locked loop receives the initial clock signal to the time when the second clock signal is fed back to the input end as the feedback clock signal;
step S622, comparing the lock losing duration with a preset duration;
and step S623, generating a prompt signal when the lock losing duration is longer than the preset duration.
In the example, whether the situation that the synchronization of the internal and external clock signals cannot be effectively adjusted through self negative feedback occurs is determined by monitoring the lock losing time of the phase-locked loop, and when the lock losing time is longer than the preset time, namely, the phase cannot be effectively locked after a long time, a prompt signal is generated to prompt relevant personnel.
In the above embodiments of the present application, the generating the first clock signal according to the feedback clock signal received by the input terminal of the phase-locked loop includes:
step S110, dividing the frequency of the feedback clock signal according to the target frequency division multiple N to generate a third clock signal;
step S120, generating a first clock signal according to the third clock signal;
wherein the frequency of the third clock signal is 1/N of the frequency of the feedback clock signal, and the frequency of the first clock signal is equivalent to the frequency of the third clock signal.
Outside the TCON IC, data may be transmitted in a serial manner, while inside the TCON IC, data may be processed in a parallel manner, and thus, the operating frequency inside the TCON IC may be much higher than the input initial clock signal CLKoOf the target clock signal CLK, and correspondingly, the target clock signal CLK to be generated by the phase-locked loopfRelative to the initial clock signal CLKoOften after frequency doubling. According to an initial clock signal CLKoWhen determining the charge pump coefficient M with the first clock signal, it is necessary to compare the initial clock signal CLK with the first clock signaloCommensurate with the frequency or phase of the first clock signal. In bookIn the application, the high-frequency signal generated in the cycle is restored to the original clock signal CLK by dividing the frequency of the generated second clock signaloThe frequency of the low-frequency signal is equivalent to that of the feedback clock signal, that is, the feedback clock signal is divided according to the target frequency division multiple N to generate a third clock signal, and the third clock signal is directly used as the first clock signal, or the third clock signal is subjected to optimization processing such as filtering and the like, and the processed third clock signal is used as the first clock signal to be executed in subsequent steps, wherein the frequency of the third clock signal is 1/N of the frequency of the feedback clock signal, and the frequency of the first clock signal is equivalent to that of the third clock signal.
Optionally, in the above embodiment, step S200 includes:
step S210, acquiring a frequency difference value of a first clock signal and an initial clock signal;
step S220, comparing the absolute value of the frequency difference value with a first frequency threshold value;
step S231, when the absolute value of the frequency difference is greater than a first frequency threshold, determining that the first coefficient is a charge pump coefficient;
step S232, when the absolute value of the frequency difference is smaller than or equal to the first frequency threshold, comparing the absolute value of the frequency difference with a second frequency threshold;
step S241, when the absolute value of the frequency difference is greater than a second frequency threshold, determining that the second coefficient is a charge pump coefficient;
step S242, when the absolute value of the frequency difference is smaller than or equal to the second frequency threshold, determining the third coefficient as the charge pump coefficient;
the first frequency threshold is larger than the second frequency threshold, the first coefficient is larger than the second coefficient, and the second coefficient is larger than the third coefficient.
In this embodiment, the charge pump coefficient is determined by comparing the frequency difference of the first clock signal and the initial clock signal. When the absolute value of the frequency difference value of the first clock signal and the initial clock signal is larger, namely the difference of the first clock signal relative to the initial clock signal is larger, selecting a larger charge pump coefficient to improve the phase locking speed; on the contrary, a smaller charge pump coefficient is selected to improve the phase locking precision and avoid the over-compensation condition. Specifically, the frequency space is divided into three parts by taking a first frequency threshold and a second frequency threshold as boundaries, the largest first coefficient is selected for the case that the absolute value of the frequency difference is greater than the first frequency threshold, the second coefficient smaller than the first coefficient is selected for the case that the absolute value of the frequency difference is smaller than or equal to the first frequency threshold and greater than the second frequency threshold, and the smallest third coefficient is selected for the case that the absolute value of the frequency difference is smaller than or equal to the second frequency threshold. Of course, a phase-locked loop with two or more charge pumps may also be provided, the required charge pump coefficient is determined according to the frequency difference between the first clock signal and the initial clock signal, and the corresponding charge pump is selected to participate in phase locking, which is not described herein again.
The present application further provides a timing control chip, as shown in fig. 4, the timing control chip includes a phase-locked loop 100, the phase-locked loop 100 includes a charge pump assembly 120, the charge pump assembly 120 includes a selection circuit and at least two charge pumps, the charge pumps are connected to the output end of the selection circuit, and each of the charge pumps has a different charge pump coefficient.
It should be noted that the definition of each clock signal referred to hereinafter is the same as that of each clock signal in the timing control method embodiment. The input of the phase locked loop 100 is arranged to receive an externally input initial clock signal CLKoAfter phase-locked by phase-locked loop, the internally generated target clock signal CLK is generatedfAnd an externally inputted initial clock signal CLKoAnd synchronizing to provide timing reference for the data processing modules in the TCON IC to ensure correct processing of the display data. During the first cycle, the input of the phase locked loop 100 receives an initial clock signal, and the charge pump coefficients of the charge pump assembly 120 are determined during the first cycle based on the initial clock signal. During subsequent cycles, the input of the phase locked loop 100 receives an initial clock signal and a feedback clock signal, and the charge pump coefficients of the charge pump assembly 120 are determined based on the initial clock signal and the feedback clock signal. As described in the example, the PLL can compensate for the frequency difference at each timeAnd M is N is delta F, wherein M is a charge pump coefficient, and N is a voltage-controlled oscillator coefficient. In order to enable the frequency difference value compensated by the phase-locked loop each time to meet the requirements of efficiency and precision, when the frequency difference value or the phase difference value of the initial clock signal and the first clock signal is large, namely the deviation from the phase-locked state is serious, a large charge pump coefficient M is determined, and a corresponding charge pump is selected to participate in phase locking to improve the frequency difference value compensated in each cycle, so that the phase-locked speed is improved; when the frequency difference or the phase difference between the initial clock signal and the first clock signal is small, namely relatively close to a phase-locked state, a small charge pump coefficient M is determined, and a corresponding charge pump is selected to participate in phase locking so as to reduce the compensated frequency difference in each cycle.
Optionally, as shown in fig. 4, the phase-locked loop 100 includes a phase detector 110 and a voltage-controlled oscillator 130, an input end of the phase detector 110 is configured to receive an initial clock signal or a feedback clock signal, and an output end of the phase detector 110 is connected to an input end of the selection circuit; the input of the vco 130 is connected to the output of the charge pump, and the output of the vco 130 is configured to output the target clock signal.
Wherein an initial clock signal CLKoThe input of the self-phase detector 110 enters the phase locked loop 100 and the target clock signal CLKfOutput from the phase locked loop 100 via the output of the voltage controlled oscillator 130. When the clock signal is circulating in the phase locked loop 100, the phase detector 110 obtains the initial clock signal CLK in the current stateoAnd a first clock signal for obtaining the first clock signal and the initial clock signal CLK in the current stateoThe selection circuit determines a charge pump coefficient M according to the frequency difference Δ F, selects the corresponding charge pump to generate an adjustment voltage Δ V, and the adjustment voltage Δ V controls the voltage-controlled oscillator 130' to output a second clock signal generated in the current cycle, where Δ V is M Δ F and the frequency CLK of the second clock signal after the current cycle is CLK2F2 is N × Δ V + F2 ', N is the VCO coefficient, and F2' is the second clock generated in the previous cycleThe frequency of the signal.
Optionally, as shown in fig. 4, the timing control chip includes a frequency divider 140, an input of the frequency divider 140 is connected to the output of the voltage controlled oscillator 130, and an output of the frequency divider 140 is connected to the input of the phase detector 110.
The frequency divider 140 is arranged to divide the high-frequency second clock signal generated by the voltage-controlled oscillator 130 into a third clock signal having a frequency equivalent to that of the initial clock signal, generate the first clock signal according to the third clock signal, and compare the first clock signal with the initial clock signal to determine the charge pump coefficient of the charge pump assembly 120, thereby ensuring the speed and accuracy of phase locking.
In the above embodiment, as shown in fig. 4, the selection circuit includes a judgment sub-circuit 121, a control sub-circuit 122 and a switch sub-circuit 123, an input end of the judgment sub-circuit 121 is connected to an output end of the phase detector 110, and the judgment sub-circuit 121 is configured to generate a control signal according to a frequency difference value output by the phase detector 110; the input end of the control sub-circuit 122 is connected to the output end of the judgment sub-circuit 121; the input end of the switch sub-circuit 123 is connected to the output end of the control sub-circuit 122, the switch sub-circuit 123 includes at least two switches that are arranged in one-to-one correspondence with the charge pumps, and the switch sub-circuit 123 controls the on/off of each switch according to the control signal.
In the phase locked loop shown in fig. 4, the charge pump assembly 120 includes three paths, each path having a switch and a corresponding charge pump, i.e., charge pump 1 and switch K1 in the first path, charge pump 2 and switch K2 in the second path, and charge pump 3 and switch K3 in the third path. The judgment sub-circuit 121 generates a corresponding control signal according to an absolute value of a frequency difference between the first clock signal output from the phase detector 110 and the initial clock signal, and outputs the control signal to the control sub-circuit 121. The control sub-circuit 121 controls the switches K1, K2, and K3 to be turned on or off according to the control signal to select the charge pump 1, the charge pump 2, or the charge pump 3 having the unused charge pump coefficient, thereby achieving the synchronization of the internal and external clock signals. Assuming that M1> M2> M3 is satisfied among the charge pump coefficient M1 of the charge pump 1, the charge pump coefficient M2 of the charge pump 2 and the charge pump coefficient M3 of the charge pump 3, when the initial clock signal changes abruptly, which causes the absolute value of the frequency difference between the initial clock signal and the first clock signal to increase, the judgment sub-circuit 121 generates a control signal, the control sub-circuit 122 controls the switch K1 to be turned on according to the control signal, the switches K2 and K3 are turned off, and the charge pump 1 with the larger charge pump coefficient M1 is selected to participate in phase locking, so as to increase the compensated frequency difference in each cycle. As the absolute value of the frequency difference between the first clock signal and the initial clock signal is reduced, the charge pump 2 and the charge pump 3 are respectively selected to participate in phase locking, so that the phase locking precision is improved, and overcompensation is avoided. As shown in fig. 6, when the phase-locked loop of the example is used, the required phase-locking time is T'; when the phase-locked loop in the above embodiment is used for phase locking, the charge pump coefficient is adjustable, so that the required phase-locking time T is shorter when a larger charge pump coefficient is selected to increase the phase-locking speed.
The present application further provides a display device, where the display device includes a display panel and a timing control chip, the timing control chip is electrically connected to the display panel, and the specific structure of the timing control chip refers to the above embodiments. The display device may be a liquid crystal display device, a light emitting diode display device, a quantum dot display device, or the like.
The above description is only an alternative embodiment of the present application, and not intended to limit the scope of the present application, and all modifications and equivalents of the technical solutions that can be directly or indirectly applied to other related fields without departing from the spirit of the present application are intended to be included in the scope of the present application.
Claims (4)
1. A time sequence control method is used for a time sequence control chip and is characterized in that the time sequence control chip comprises a phase-locked loop, and the phase-locked loop comprises at least two charge pumps with different charge pump coefficients;
the time sequence control method comprises the following steps:
generating a first clock signal according to an initial clock signal or a feedback clock signal received by the input end of the phase-locked loop;
determining a charge pump coefficient of a phase-locked loop according to the initial clock signal and the first clock signal;
selecting a corresponding charge pump to participate in phase locking according to the charge pump coefficient, and generating a second clock signal;
comparing the frequency of the second clock signal with a preset frequency range;
when the frequency of the second clock signal is within the preset frequency range, generating a target clock signal according to the second clock signal, and outputting the target clock signal;
and when the frequency of the second clock signal is out of the preset frequency range, feeding the second clock signal serving as a feedback clock signal back to the input end of the phase-locked loop, and returning to execute the step of generating the first clock signal according to the feedback clock signal received by the input end of the phase-locked loop.
2. The timing control method according to claim 1, wherein after the step of feeding back the second clock signal as a feedback clock signal to the input terminal when the frequency of the second clock signal is outside the preset frequency range, the timing control method further comprises the steps of:
accumulating the feedback times of the second clock signal;
comparing the feedback times with preset times;
when the feedback times are greater than the preset times, generating a prompt signal; or the like, or, alternatively,
accumulating the lock losing time length from the time when the input end of the phase-locked loop receives the initial clock signal to the time when the second clock signal is fed back to the input end as the feedback clock signal;
comparing the lock losing duration with a preset duration;
and when the lock losing duration is greater than the preset duration, generating a prompt signal.
3. The timing control method of claim 1 or 2, wherein generating the first clock signal based on the feedback clock signal received at the input of the phase locked loop comprises:
dividing the frequency of the feedback clock signal according to a target frequency division multiple N to generate a third clock signal;
generating a first clock signal according to the third clock signal;
wherein a frequency of the third clock signal is 1/N of a frequency of the feedback clock signal, and a frequency of the first clock signal is equivalent to a frequency of the third clock signal.
4. The timing control method of claim 1 or 2, wherein the step of determining charge pump coefficients of a phase locked loop based on the initial clock signal and the first clock signal comprises:
acquiring a frequency difference value of the first clock signal and the initial clock signal;
comparing the absolute value of the frequency difference value with a first frequency threshold value;
determining a first coefficient as the charge pump coefficient when the absolute value of the frequency difference is greater than the first frequency threshold;
when the absolute value of the frequency difference is smaller than or equal to the first frequency threshold, comparing the absolute value of the frequency difference with a second frequency threshold;
determining a second coefficient as the charge pump coefficient when the absolute value of the frequency difference is greater than the second frequency threshold;
determining a third coefficient as the charge pump coefficient when the absolute value of the frequency difference is less than or equal to the second frequency threshold;
wherein the first frequency threshold is greater than the second frequency threshold, the first coefficient is greater than the second coefficient, and the second coefficient is greater than the third coefficient.
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| JP2000269807A (en) * | 1999-03-16 | 2000-09-29 | Huabang Electronic Co Ltd | Phase locked loop and signal synchronizing method |
| US6903585B2 (en) * | 2003-06-27 | 2005-06-07 | Analog Devices, Inc. | Pulse width modulated common mode feedback loop and method for differential charge pump |
| CN101159433B (en) * | 2006-10-08 | 2011-08-31 | 北京大学深圳研究生院 | Fast locked phase-locked loop circuit |
| CN104202048B (en) * | 2014-08-27 | 2017-05-17 | 中国科学技术大学 | Broadband totally-integrated phase-locked loop frequency synthesizer |
| CN106067813B (en) * | 2016-07-18 | 2019-06-04 | 西安紫光国芯半导体有限公司 | A kind of PLL of fast and stable locking |
| CN106972857B (en) * | 2017-04-28 | 2023-03-21 | 深圳市国微电子有限公司 | Multi-loop self-biased phase-locked loop circuit and clock generator |
| CN107154243B (en) * | 2017-06-20 | 2018-06-26 | 惠科股份有限公司 | Driving method, driving device and the display device of display panel |
| CN108988853B (en) * | 2018-07-04 | 2020-11-10 | 西安电子科技大学 | Digital auxiliary locking circuit |
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