CN109818614A - Sequential control method, timing controller and display device - Google Patents
Sequential control method, timing controller and display device Download PDFInfo
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- CN109818614A CN109818614A CN201811588005.5A CN201811588005A CN109818614A CN 109818614 A CN109818614 A CN 109818614A CN 201811588005 A CN201811588005 A CN 201811588005A CN 109818614 A CN109818614 A CN 109818614A
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Abstract
The application discloses a kind of sequential control method, timing controller and display device, wherein sequential control method is used for timing controller, and timing controller includes phaselocked loop, and phaselocked loop includes at least two charge pumps with different charge pump coefficients；Sequential control method generates the first clock signal the following steps are included: the initial clock signal or feedback clock signal received according to the input terminal of phaselocked loop；According to initial clock signal and the first clock signal, the charge pump coefficient of phaselocked loop is determined；According to charge pump coefficient, corresponding charge pump is selected to participate in locking phase, generates second clock signal.
Description
Technical field
This application involves field of display technology, in particular to a kind of sequential control method, timing controller and display dress
It sets.
Background technique
Here statement only provides background information related with the application, without inevitably constituting the prior art.Timing control
Coremaking piece (Timer control register Integrated circuit, TCON IC) is the important set in display device
Part controls the driver' s timing of display device, to realize the normal display of picture.In the operational process of TCON IC, need
Corresponding target clock signal is generated, to ensure external clock and internal clocking according to externally input initial clock signal
Synchronization, to correctly grab and handle display data, and above-mentioned target clock signal is produced by the phaselocked loop in TCON IC
Raw.
Since the locking phase of phaselocked loop needs certain time, when externally input initial clock signal varies widely,
The out-of-lock state that the long period will be generated causes the display of display device abnormal.
Summary of the invention
The main purpose of the application is to propose a kind of sequential control method, realizes fast and accurately locking phase, to ensure
The normal display of picture in display device.
The sequential control method that the application proposes is used for timing controller, and the timing controller includes phaselocked loop,
The phaselocked loop includes at least two charge pumps with different charge pump coefficients；The sequential control method includes following step
It is rapid:
The initial clock signal or feedback clock signal received according to the input terminal of the phaselocked loop generates the first clock
Signal；
According to the initial clock signal and first clock signal, the charge pump coefficient of phaselocked loop is determined；
According to the charge pump coefficient, corresponding charge pump is selected to participate in locking phase, generates second clock signal.
Optionally, corresponding charge pump is selected according to the charge pump coefficient described, and controls the charge pump and participates in
After the step of locking phase, generation second clock signal, the sequential control method is further comprising the steps of:
Compare the frequency and predeterminated frequency range of the second clock signal；
When the frequency of the second clock signal is within the predeterminated frequency range, believed according to the second clock
Number target clock signal is generated, and exports the target clock signal；
When other than the frequency of the second clock signal being in the predeterminated frequency range, by the second clock signal
The input terminal of the phaselocked loop is fed back to as feedback clock signal, and is returned to execution and received according to the input terminal of the phaselocked loop
The step of feedback clock signal arrived, the first clock signal of generation.
Optionally, when other than the frequency of the second clock signal is in the predeterminated frequency range, by described
After the step of two clock signals feed back to the input terminal as feedback clock signal, the sequential control method further include with
Lower step:
Add up the Times of Feedback of the second clock signal；
Compare the Times of Feedback and preset times；
When the Times of Feedback is greater than the preset times, standby signal is generated；Or,
Add up the phaselocked loop input terminal receive initial clock signal to currently using the second clock signal as
Feedback clock signal feeds back to the losing lock duration between the input terminal；
Compare the losing lock duration and preset duration；
When the losing lock duration is greater than the preset duration, standby signal is generated.
Optionally, the feedback clock signal received according to the input terminal of the phaselocked loop generates the first clock signal
Step includes:
Multiple N is divided according to target, the feedback clock signal is divided, generates third clock signal；
According to the third clock signal, the first clock signal is generated；
Wherein, the frequency of the third clock signal is the 1/N of the frequency of the feedback clock signal, first clock
The frequency of signal is suitable with the frequency of the third clock signal.
Optionally, described according to the initial clock signal and first clock signal, determine the charge pump of phaselocked loop
The step of coefficient includes:
Obtain the frequency difference of first clock signal and the initial clock signal；
Compare the absolute value and first frequency threshold value of the frequency difference；
When the absolute value of the frequency difference is greater than the first frequency threshold value, determine that the first coefficient is the charge pump
Coefficient；
When the absolute value of the frequency difference is less than or equal to the first frequency threshold value, the frequency difference is compared
Absolute value and second frequency threshold value；
When the absolute value of the frequency difference is greater than the second frequency threshold value, determine that the second coefficient is the charge pump
Coefficient；
When the absolute value of the frequency difference is less than or equal to the second frequency threshold value, determine that third coefficient is described
Charge pump coefficient；
Wherein, the first frequency threshold value is greater than the second frequency threshold value, and first coefficient is greater than second system
Number, second coefficient are greater than the third coefficient.
To achieve the above object, the application also proposes that a kind of timing controller, the timing controller include locking phase
Ring, the phaselocked loop include charge pump components, and the charge pump components include selection circuit and at least two charge pumps, described
Charge pump is connected to the output end of the selection circuit, and each charge pump has different charge pump coefficients.
Optionally, the phaselocked loop includes phase discriminator and voltage controlled oscillator, and the input terminal of the phase discriminator is set as connecing
The initial clock signal or the feedback clock signal are received, the output end of the phase discriminator is connected to the defeated of the selection circuit
Enter end；The input terminal of the voltage controlled oscillator is connected to the output end of the charge pump, and the output end of the voltage controlled oscillator is set
It is set to output target clock signal.
Optionally, the timing controller includes frequency divider, and the input terminal of the frequency divider is connected to the voltage-controlled vibration
The output end of device is swung, the output end of the frequency divider is connected to the input terminal of the phase discriminator.
Optionally, the selection circuit includes judging sub-circuit, controls sub-circuit and switch sub-circuit, judgement
The input terminal of circuit is connected to the output end of the phase discriminator, and the judgement sub-circuit is set as according to phase discriminator output
Frequency difference generates control signal；The input terminal of the control sub-circuit is connected to the output end of the judgement sub-circuit；It is described
The input terminal of switch sub-circuit is connected to the output end of the control sub-circuit, and the switch sub-circuit includes and the charge pump
At least two switches being arranged in a one-to-one correspondence, the switch sub-circuit according to the control signal control each switch conduction or
Shutdown.
To achieve the above object, the application proposes that a kind of display device, the display device include display panel with timely
Sequence controls chip, and the timing controller is electrically connected with the display panel, and the timing controller includes phaselocked loop, institute
Stating phaselocked loop includes charge pump components, and the charge pump components include selection circuit and at least two charge pumps, the charge
Pump is connected to the output end of the selection circuit, and each charge pump has different charge pump coefficients.
In technical scheme, sequential control method is used for timing controller, and timing controller includes phaselocked loop,
Phaselocked loop includes at least two charge pumps with different charge pump coefficients, and sequential control method is the following steps are included: according to lock
The initial clock signal or feedback clock signal that the input terminal of phase ring receives generate the first clock signal；According to initial clock
Signal and the first clock signal determine the charge pump coefficient of phaselocked loop；According to charge pump coefficient, corresponding charge pump is selected to participate in
Locking phase generates second clock signal.In this application, phaselocked loop includes at least two charges with different charge pump coefficients
Pump, therefore different charge pumps can be selected to participate in locking phase, to change according to the variation of the first clock signal and initial clock signal
Become the compensation magnitude in each circulation of phaselocked loop to clock signal frequency, to improve the speed and precision of locking phase, improves lock
Phase effect ensures the normal display of display device.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of application for those of ordinary skill in the art without creative efforts, can be with
The structure shown according to these attached drawings obtains other attached drawings.
Fig. 1 is the structural schematic diagram of timing controller in an example；
Fig. 2 is the structural schematic diagram of phaselocked loop in Fig. 1；
Fig. 3 is the flow diagram of one embodiment of the application sequential control method；
Fig. 4 is the structural schematic diagram of one embodiment of the application timing controller；
Fig. 5 is the flow diagram of another embodiment of the application sequential control method；
Fig. 6 is the schematic diagram that the frequency of second clock signal in the timing controller of Fig. 1 and Fig. 4 changes over time.
The embodiments will be further described with reference to the accompanying drawings for realization, functional characteristics and the advantage of the application purpose.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiment is only a part of the embodiment of the application, instead of all the embodiments.Base
Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts it is all its
His embodiment, shall fall in the protection scope of this application.
It is to be appreciated that if relating to directionality instruction (such as up, down, left, right, before and after ...) in the embodiment of the present application,
Then directionality instruction be only used for explain under a certain particular pose (as shown in the picture) between each component relative positional relationship,
Motion conditions etc., if the particular pose changes, directionality instruction is also correspondingly changed correspondingly.
In addition, being somebody's turn to do " first ", " second " etc. if relating to the description of " first ", " second " etc. in the embodiment of the present application
Description be used for description purposes only, be not understood to indicate or imply its relative importance or implicitly indicate indicated skill
The quantity of art feature." first " is defined as a result, the feature of " second " can explicitly or implicitly include at least one spy
Sign.In addition, the meaning of the "and/or" occurred in full text is, and including three schemes arranged side by side, by taking " A and/or B " as an example, including A
The scheme that scheme or B scheme or A and B meet simultaneously.In addition, the technical solution between each embodiment can be combined with each other,
It but must be based on can be realized by those of ordinary skill in the art, when conflicting or nothing occurs in the combination of technical solution
Method realize when will be understood that the combination of this technical solution is not present, also not this application claims protection scope within.
In an example, as shown in Figure 1, TCON IC includes phaselocked loop 100 ' and data processing module 200 '.Wherein, it locks
Phase ring 100 ' is according to initial clock signal CLKoGenerate target clock signal CLKf, and by target clock signal CLKfIt exports to number
According to processing module 200 '.Data processing module 200 ' is in target clock signal CLKfControl under grab initial display data
DATAo, target is generated after processing shows data DATAf, the display of picture in the display panel to drive display device.Such as Fig. 2
It is shown, phaselocked loop 100 ' include be sequentially connected and formed the phase discriminator 110 ' of loop, charge pump 120 ', voltage controlled oscillator 130 ' and
Frequency divider 140 ', wherein initial clock signal CLKoEnter phaselocked loop 100 ' from the input terminal of phase discriminator 110 ', and target clock
Signal CLKfOutput end through voltage controlled oscillator 130 ' is exported from phaselocked loop 100 '.When clock signal recycles in phaselocked loop 100 '
When, phase discriminator 110 ' obtains the initial clock signal CLK under current stateoWith third clock signal, wherein third clock signal
It is generated after being divided by the divided device 140 ' of second clock signal, and second clock signal here is in preceding one cycle by pressing
Control what oscillator 130 ' generated, phase discriminator calculates third clock signal and initial clock signal CLKoFrequency difference Δ F output
To charge pump 120 ', charge pump 120 ' generates one according to the frequency difference Δ F and adjusts voltage Δ V, adjusting voltage Δ V accordingly
Control voltage controlled oscillator 130 ' exports the second clock signal generated in this circulation, wherein Δ V=M* Δ F, M are charge pump
120 ' charge pump coefficient, the frequency CLK of second clock signal after this is recycled2Meet F2=N* Δ V+F2 ', N is voltage-controlled vibration
Device coefficient is swung, F2 ' is the frequency of second clock signal caused by preceding one cycle.According to foregoing description it is found that in this example
Phaselocked loop 100 ' in, the frequency of second clock signal caused by voltage controlled oscillator 130 ' meets F2=M*N* Δ F+F2 ',
That is when mono- timing of charge pump coefficient M and voltage controlled oscillator coefficient N, the frequency difference M*N* Δ F that can compensate for every time is also
Fixed.If initial clock signal CLKoBiggish variation has occurred, long-time is in out-of-lock state, held very much by phaselocked loop 100 '
Easily lead to the exception of display.
The application proposes a kind of sequential control method, and wherein the charge pump coefficient of phaselocked loop is variable, so as to according to initial
The variation of clock signal changes charge pump coefficient, improves the speed and accuracy of locking phase.
In the embodiment of the application, as shown in Figure 3 and Figure 4, which is used for timing controller, when
Sequence control chip includes phaselocked loop 100, and phaselocked loop 100 includes at least two charge pumps with different charge pump coefficients；Timing
Control method the following steps are included:
Step S100, the initial clock signal or feedback clock signal received according to the input terminal of phaselocked loop generates the
One clock signal；
The input terminal of phaselocked loop is set as receiving externally input initial clock signal CLKo, after phaselocked loop locking phase,
Make the internal target clock signal CLK generatedfWith externally input initial clock signal CLKoIt is synchronous, thus in TCON IC
Data processing module provides timing reference, to ensure the correct processing of display data.In first time cyclic process, phaselocked loop
Input terminal receives initial clock signal, and generates the first clock signal according to initial clock signal.Specifically, can be when will be initial
Clock signal can also carry out the processing such as low-pass filtering directly as the first clock signal to initial clock signal, then will improve
Signal-to-noise ratio optimizes initial clock signal after waveform as the first clock signal.In cyclic process later, phaselocked loop
Input terminal receive initial clock signal and feedback clock signal, wherein the initial clock signal received is that subsequent charge pumps
Determining for coefficient provides reference, that is, charge pump coefficient feedback clock signal related with initial clock signal, and receiving
Then the generation for the first clock signal in this circulation provides reference, that is, (removes for the first time in each circulation of phaselocked loop
Circulation) in, the first clock signal is all the variation with feedback clock signal and changes, to adapt to locking phase demand, specifically,
Can be directly using feedback clock signal as the first clock signal, or the processing according to phaselocked loop to feedback clock signal will
Treated the feedback clock signals such as frequency dividing, filtering are as the first clock signal.
Step S200, according to initial clock signal and the first clock signal, the charge pump coefficient of phaselocked loop is determined；
According to the description in example it is found that the frequency difference that phaselocked loop can compensate for every time is M*N* Δ F, wherein M is electricity
Lotus pumps coefficient, and N is voltage controlled oscillator coefficient.In order to which the frequency difference for compensating phaselocked loop every time meets the need of efficiency and precision
It asks, according to initial clock signal and the first clock signal, determines the charge pump coefficient M of phaselocked loop.Specifically, calculating can be passed through
The frequency difference or phase difference value of initial clock signal and the first clock signal determine charge pump coefficient M.In general, when initial
When the frequency difference or larger phase difference value of clock signal and the first clock signal, i.e., when deviation phase locked state is more serious,
A biggish charge pump coefficient M is determined to improve the frequency difference compensated in circulation every time, to improve locking phase speed；When initial
When the frequency difference or smaller phase difference value of clock signal and the first clock signal, that is, when being relatively close to phase locked state, determine
On the one hand one lesser charge pump coefficient M helps to improve the accurate of locking phase to reduce the frequency difference compensated in circulation every time
Degree, on the other hand also it is possible to prevente effectively from the generation of overcompensation situation.
Step S300, according to charge pump coefficient, corresponding charge pump is selected to participate in locking phase, generates second clock signal.
After determining charge pump coefficient, corresponding charge pump is selected according to charge pump coefficient, which is connected to lock
Xiang Huanzhong makes it participate in locking phase, to generate second clock signal.Second clock signal can be generated by voltage controlled oscillator, be led to
One or many compensation are crossed, the clock signal synchronization inside and outside phaselocked loop is made, to ensure that the data processing module of TCON IC can be by
Data are shown according to correct timing sequence process.
In the present embodiment, sequential control method is used for timing controller, and timing controller includes phaselocked loop 100,
Phaselocked loop 100 include at least two with different charge pump coefficients charge pumps, sequential control method the following steps are included: according to
The initial clock signal or feedback clock signal that the input terminal of phaselocked loop 100 receives generate the first clock signal；According to initial
Clock signal and the first clock signal determine the charge pump coefficient of phaselocked loop 100；According to charge pump coefficient, corresponding electricity is selected
Lotus pump participates in locking phase, generates second clock signal.Wherein, phaselocked loop 100 includes at least two with different charge pump coefficients
Charge pump, therefore different charge pumps can be selected to participate in locking phase according to the variation of the first clock signal and initial clock signal,
The compensation magnitude of clock signal frequency is changed to improve the speed and precision of locking phase in each circulation to change phaselocked loop
Kind locking phase effect, ensures the normal display of display device.
Optionally, as shown in figure 5, in another embodiment of the application, after step S300, sequential control method is also
The following steps are included:
Step S400, the frequency and predeterminated frequency range of second clock signal are compared；
Step S510, when the frequency of second clock signal is within predeterminated frequency range, according to second clock signal
Target clock signal is generated, and exports target clock signal；
Step S520, when other than the frequency of second clock signal is in predeterminated frequency range, second clock signal is made
When feeding back to the input terminal of phaselocked loop for feedback clock signal, and returning to the feedback that execution is received according to the input terminal of phaselocked loop
The step of clock signal, the first clock signal of generation.
Specifically, in TCON IC, target clock signal CLK needed for data processing modulefFrequency can not be one
A determining value, but within certain predeterminated frequency range, in this case, data processing module can be grabbed correctly
To initial display data and handled to generate target and show data.In a specific example, predeterminated frequency range be can be
Clock signal CLK at the beginningo20kHz of frequency or so range.In order to improve the treatment effeciency of phaselocked loop, second clock is being generated
After signal, by the frequency and predeterminated frequency range that compare second clock signal, it is determined whether also need to continue in phaselocked loop
Clock signal is recycled to compensate frequency difference.When the frequency of second clock signal is within predeterminated frequency range, show this
When phaselocked loop caused by second clock signal met the requirement of data processing, then target is generated according to second clock signal
Clock signal clkf, and export target clock signal.Specifically, can be by second clock signal directly as target clock signal
CLKf, after frequency multiplication, the processing such as filtering can also be carried out to second clock signal, general's treated second clock signal is as target
Clock signal clkf, to meet the needs of display driving.When other than the frequency of second clock signal being in predeterminated frequency range,
Show to be still within out-of-lock state at this time, the frequency of second clock signal be not able to satisfy display data processing requirement, need after
Continue and recycled in phaselocked loop, to compensate frequency difference, therefore feeds back to locking phase using second clock signal as feedback clock signal
The input terminal of ring, and the feedback clock signal for executing and receiving according to the input terminal of phaselocked loop is returned, generate the first clock signal
The step of, that is, the first clock signal is generated according to the second clock signal of feedback, continue to compensate frequency difference, until being produced
Raw second clock signal meets the needs of display driving.
Optionally, in the another embodiment of the application, in order to avoid can not be by itself negative-feedback to adjust in phaselocked loop
In the case where saving inside and outside clock signal synchronization, long-time is in out-of-lock state and leads to the operation exception of display device, to lock
Cycle-index or time of losing lock during phase are monitored, to determine the operating status of phaselocked loop, so that related personnel is timely
It safeguards TCON IC, ensures the normal operation of display device.
In a specific example, when other than the frequency of second clock signal is in predeterminated frequency range, when by second
After the step of clock signal feeds back to input terminal as feedback clock signal, sequential control method is further comprising the steps of:
Step S611, the Times of Feedback of accumulative second clock signal；
Step S612, Times of Feedback and preset times are compared；
Step S613, when Times of Feedback is greater than preset times, standby signal is generated.
In this example, pass through the cycle-index in monitoring phaselocked loop, it is determined whether occurring can not be anti-by bearing certainly
Feedback effectively adjusts the situation of inside and outside clock signal synchronization, when Times of Feedback is greater than preset times, i.e., repeatedly after circulation still without
When the effective locking phase of method, standby signal is generated to prompt related personnel.
In another specific example, when other than the frequency of second clock signal is in predeterminated frequency range, by second
After the step of clock signal feeds back to input terminal as feedback clock signal, sequential control method is further comprising the steps of:
Step S621, the input terminal of accumulative phaselocked loop receive initial clock signal to currently using second clock signal as
Feedback clock signal feeds back to the losing lock duration between input terminal；
Step S622, losing lock duration and preset duration are compared；
Step S623, when losing lock duration is greater than preset duration, standby signal is generated.
In this example, pass through the losing lock duration of monitoring phaselocked loop, it is determined whether occurring can not be by itself negative-feedback
The situation for effectively adjusting inside and outside clock signal synchronization, when losing lock duration is greater than preset duration, i.e., by the long period still without
When the effective locking phase of method, standby signal is generated to prompt related personnel.
In above-described embodiment of the application, according to the feedback clock signal that the input terminal of phaselocked loop receives, the is generated
The step of one clock signal includes:
Step S110, multiple N is divided according to target, feedback clock signal is divided, generate third clock signal；
Step S120, according to third clock signal, the first clock signal is generated；
Wherein, the frequency of third clock signal is the 1/N of the frequency of feedback clock signal, the frequency of the first clock signal with
The frequency of third clock signal is suitable.
Except TCON IC, data can be transmitted in a serial fashion, and within TCON IC, data can be with parallel side
Formula is processed, and therefore, the working frequency inside TCON IC is possible to the initial clock signal CLK much higher than inputoFrequency
Rate, correspondingly, the target clock signal CLK generated needed for phaselocked loopfOpposite initial clock signal CLKoOften by frequency multiplication
It is generated after reason.And according to initial clock signal CLKoWhen determining charge pump coefficient M with the first clock signal, for the ease of
It compares, it is necessary to make initial clock signal CLKoIt is suitable with the frequency of the first clock signal or phase.In this application, by right
The high-frequency signal generated in cyclic process is reduced to and initial clock signal CLK by the second clock signal frequency split of generationoFrequency
The comparable low frequency signal of rate divides multiple N according to target, divide to feedback clock signal, generates third clock signal, and will
Third clock signal, alternatively, the optimization processings such as being filtered to third clock signal, will be handled directly as the first clock signal
Third clock signal afterwards is as the first clock signal, with the execution to subsequent step, wherein the frequency of third clock signal is
The 1/N of the frequency of feedback clock signal, and the frequency of the first clock signal is suitable with the frequency of third clock signal.
Optionally, in the above-described embodiments, step S200 includes:
Step S210, the frequency difference of the first clock signal and initial clock signal is obtained；
Step S220, the absolute value of versus frequency difference and first frequency threshold value；
Step S231, when the absolute value of frequency difference is greater than first frequency threshold value, determine that the first coefficient is charge pump system
Number；
Step S232, when the absolute value of frequency difference be less than or equal to first frequency threshold value when, versus frequency difference it is exhausted
To value and second frequency threshold value；
Step S241, when the absolute value of frequency difference is greater than second frequency threshold value, determine that the second coefficient is charge pump system
Number；
Step S242, when the absolute value of frequency difference is less than or equal to second frequency threshold value, determine third coefficient for electricity
Lotus pumps coefficient；
Wherein, first frequency threshold value is greater than second frequency threshold value, and the first coefficient is greater than the second coefficient, and the second coefficient is greater than the
Three coefficients.
In the present embodiment, charge pump system is determined by comparing the frequency difference of the first clock signal and initial clock signal
Number.When the absolute value of the first clock signal and the frequency difference of initial clock signal is bigger, i.e., the first clock signal is relatively initial
When the difference of clock signal is bigger, bigger charge pump coefficient is selected, to improve locking phase speed；Conversely, selecting smaller charge
It pumps coefficient and avoids the generation of overcompensation situation to improve locking phase precision.Specifically, with first frequency threshold value and second frequency threshold
Value is boundary, and frequency space is divided into three parts, and the situation of first frequency threshold value, selection are greater than for the absolute value of frequency difference
Maximum first coefficient is less than or equal to first frequency threshold value for the absolute value of frequency difference and is greater than second frequency threshold value
Situation, select less than the first coefficient the second coefficient, for frequency difference absolute value be less than or equal to second frequency threshold value
Situation, select the smallest third coefficient.It is of course also possible to which the phaselocked loop with two or three above charge pumps, root is arranged
According to the frequency difference of the first clock signal and initial clock signal, required charge pump coefficient is determined, and select corresponding charge
Pump participates in locking phase, and details are not described herein.
The application also proposes a kind of timing controller, as shown in figure 4, timing controller includes phaselocked loop 100, locking phase
Ring 100 includes charge pump components 120, and charge pump components 120 include selection circuit and at least two charge pumps, charge pump connection
In the output end of selection circuit, and each charge pump has different charge pump coefficients.
It should be noted that each clock in the definition and sequential control method embodiment of each clock signal involved in hereinafter
The definition of signal is consistent.The input terminal of phaselocked loop 100 is set as receiving externally input initial clock signal CLKo, by locking phase
After ring locking phase, make the internal target clock signal CLK generatedfWith externally input initial clock signal CLKoIt is synchronous, to be
Data processing module in TCON IC provides timing reference, to ensure the correct processing of display data.In cyclic process for the first time
In, the input terminal of phaselocked loop 100 receives initial clock signal, and the charge pump coefficient of charge pump components 120 is in cyclic process for the first time
In be to be determined according to initial clock signal.In cyclic process later, the input terminal of phaselocked loop 100 receives initial clock letter
Number and feedback clock signal, the charge pump coefficient of charge pump components 120 be true according to initial clock signal and feedback clock signal
Fixed.According to the description in example it is found that the frequency difference that phaselocked loop can compensate for every time is M*N* Δ F, wherein M is charge
Coefficient is pumped, N is voltage controlled oscillator coefficient.The needs of meeting efficiency and precision for the frequency difference for compensating phaselocked loop every time,
When the frequency difference or larger phase difference value of initial clock signal and the first clock signal, i.e. deviation phase locked state is more tight
When weight, a biggish charge pump coefficient M is determined, and select the corresponding charge pump to participate in locking phase to improve and compensate in circulation every time
Frequency difference, to improve locking phase speed；When the frequency difference or phase difference value of initial clock signal and the first clock signal
It when smaller, that is, when being relatively close to phase locked state, determines a lesser charge pump coefficient M, and corresponding charge pump is selected to participate in lock
Mutually to reduce the frequency difference that compensates in circulation every time, the accuracy of locking phase is on the one hand helped to improve, it on the other hand can also be with
Effectively avoid the generation of overcompensation situation.
Optionally, as shown in figure 4, phaselocked loop 100 includes phase discriminator 110 and voltage controlled oscillator 130, phase discriminator 110
Input terminal is set as receiving initial clock signal or feedback clock signal, the output end of phase discriminator 110 are connected to selection circuit
Input terminal；The input terminal of voltage controlled oscillator 130 is connected to the output end of charge pump, and the output end of voltage controlled oscillator 130 is set as
Export target clock signal.
Wherein, initial clock signal CLKoEnter phaselocked loop 100 from the input terminal of phase discriminator 110, and target clock signal
CLKfOutput end through voltage controlled oscillator 130 is exported from phaselocked loop 100.When clock signal recycles in phaselocked loop 100, phase demodulation
Device 110 obtains the initial clock signal CLK under current stateoWith the first clock signal, the first clock signal and current shape are obtained
Initial clock signal CLK under stateoFrequency difference Δ F export to the selection circuit in charge pump components 120, selection circuit according to
Frequency difference Δ F determines charge pump coefficient M, selects corresponding charge pump to generate and adjust voltage Δ V, adjusting voltage Δ V
Control voltage controlled oscillator 130 ' exports the second clock signal generated in this circulation, wherein Δ V=M* Δ F, after this is recycled
The frequency CLK of second clock signal2Meet F2=N* Δ V+F2 ', N is voltage controlled oscillator coefficient, and F2 ' is produced by preceding one cycle
The frequency of raw second clock signal.
Optionally, as shown in figure 4, timing controller includes frequency divider 140, the input terminal of frequency divider 140 is connected to pressure
The output end of oscillator 130 is controlled, the output end of frequency divider 140 is connected to the input terminal of phase discriminator 110.
By being arranged frequency divider 140, the second clock signal frequency split of the high frequency that voltage controlled oscillator 130 is generated be with it is initial
The comparable third clock signal of the frequency of clock signal, according to third clock signal generate the first clock signal, and with it is initial when
Clock signal compares, and to determine the charge pump coefficient of charge pump components 120, ensures the speed and accuracy of locking phase.
In the above-described embodiments, as shown in figure 4, selection circuit includes judge sub-circuit 121, control sub-circuit 122 and
Sub-circuit 123 is switched, judges that the input terminal of sub-circuit 121 is connected to the output end of phase discriminator 110, judges that sub-circuit 121 is arranged
For the frequency difference exported according to phase discriminator 110, control signal is generated；The input terminal of control sub-circuit 122 is connected to judgement
The output end of circuit 121；The input terminal of switch sub-circuit 123 is connected to the output end of control sub-circuit 122, switchs sub-circuit
123 include at least two switches being arranged in a one-to-one correspondence with charge pump, and switch sub-circuit 123 controls each switch according to control signal
On or off.
In phaselocked loop as shown in Figure 4, charge pump components 120 include three accesses, are provided with a switch in each access
With corresponding charge pump, charge pump 1 and switch K1 in respectively the first access, charge pump 2 and switch K2 in alternate path,
And the charge pump 3 in third path and switch K3.Judge the first clock signal that sub-circuit 121 is exported according to phase discriminator 110
With the absolute value of the frequency difference of initial clock signal, corresponding control signal is generated, and exports and gives control sub-circuit 121.Control
System circuit 121 has with selection according to the on or off of control Signal-controlled switch K1, K2 and K3 and does not have to charge pump coefficient
Charge pump 1, charge pump 2 or charge pump 3, realize the synchronization of inside and outside clock signal.Assuming that the charge pump coefficient M1 of charge pump 1,
Meet M1 > M2 > M3 between the charge pump coefficient M2 of charge pump 2 and the charge pump coefficient M3 of charge pump 3, then works as initial clock signal
It mutates, when the absolute value of the frequency difference of initial clock signal and the first clock signal being caused to increase, judges sub-circuit 121
Control signal is generated, control sub-circuit 122 is closed according to control Signal-controlled switch K1 conducting, switch K2 and K3, and selection has
The charge pump 1 of larger charge pump coefficient M1 participates in locking phase, to improve the frequency difference compensated in circulation every time.When with first
The absolute value of frequency difference between clock signal and initial clock signal reduces, and charge pump 2, charge pump 3 is selected to participate in lock respectively
Phase avoids overcompensation to improve locking phase precision.As shown in fig. 6, when using the phaselocked loop locking phase in example, required locking phase
Time is T '；It is biggish in selection since charge pump coefficient is adjustable when using the phaselocked loop locking phase in above-described embodiment
In the case that charge pump coefficient improves locking phase speed, required locking phase time T is shorter.
The application also proposes that a kind of display device, display device include display panel and timing controller, timing control
Coremaking piece is electrically connected with display panel, and the specific structure of the timing controller is referring to above-described embodiment, due to this display device
Using whole technical solutions of above-mentioned all embodiments, therefore at least institute brought by the technical solution with above-described embodiment
There is beneficial effect, this is no longer going to repeat them.Wherein, display device can be liquid crystal display device, diode displaying dress
It sets or quantum dot display device etc..
The foregoing is merely the alternative embodiments of the application, are not intended to limit the scope of the patents of the application, all at this
Under the inventive concept of application, using equivalent structure transformation made by present specification and accompanying drawing content, or directly/use indirectly
In the scope of patent protection that other related technical areas are included in the application.
Claims (10)
1. a kind of sequential control method is used for timing controller, which is characterized in that the timing controller includes locking phase
Ring, the phaselocked loop include at least two charge pumps with different charge pump coefficients；
The sequential control method the following steps are included:
The initial clock signal or feedback clock signal received according to the input terminal of the phaselocked loop generates the first clock letter
Number；
According to the initial clock signal and first clock signal, the charge pump coefficient of phaselocked loop is determined；
According to the charge pump coefficient, corresponding charge pump is selected to participate in locking phase, generates second clock signal.
2. sequential control method as described in claim 1, which is characterized in that described according to the charge pump coefficient, selection
Corresponding charge pump, and after the step of controlling the charge pump participation locking phase, generating second clock signal, the timing control
Method is further comprising the steps of:
Compare the frequency and predeterminated frequency range of the second clock signal；
When the frequency of the second clock signal is within the predeterminated frequency range, produced according to the second clock signal
Raw target clock signal, and export the target clock signal；
When other than the frequency of the second clock signal being in the predeterminated frequency range, using the second clock signal as
Feedback clock signal feeds back to the input terminal of the phaselocked loop, and returns to what execution was received according to the input terminal of the phaselocked loop
The step of feedback clock signal, the first clock signal of generation.
3. sequential control method as claimed in claim 2, which is characterized in that be in the frequency when the second clock signal
When other than the predeterminated frequency range, the step of the input terminal is fed back to using the second clock signal as feedback clock signal
After rapid, the sequential control method is further comprising the steps of:
Add up the Times of Feedback of the second clock signal；
Compare the Times of Feedback and preset times；
When the Times of Feedback is greater than the preset times, standby signal is generated；Or,
The input terminal for adding up the phaselocked loop receives initial clock signal to currently using the second clock signal as feedback
Clock signal feeds back to the losing lock duration between the input terminal；
Compare the losing lock duration and preset duration；
When the losing lock duration is greater than the preset duration, standby signal is generated.
4. sequential control method as claimed any one in claims 1 to 3, which is characterized in that according to the defeated of the phaselocked loop
Entering the step of terminating the feedback clock signal received, generating the first clock signal includes:
Multiple N is divided according to target, the feedback clock signal is divided, generates third clock signal；
According to the third clock signal, the first clock signal is generated；
Wherein, the frequency of the third clock signal is the 1/N of the frequency of the feedback clock signal, first clock signal
Frequency it is suitable with the frequency of the third clock signal.
5. sequential control method as claimed any one in claims 1 to 3, which is characterized in that it is described according to it is described initial when
Clock signal and first clock signal, the step of determining the charge pump coefficient of phaselocked loop include:
Obtain the frequency difference of first clock signal and the initial clock signal；
Compare the absolute value and first frequency threshold value of the frequency difference；
When the absolute value of the frequency difference is greater than the first frequency threshold value, determine that the first coefficient is the charge pump system
Number；
When the absolute value of the frequency difference is less than or equal to the first frequency threshold value, the absolute of the frequency difference is compared
Value and second frequency threshold value；
When the absolute value of the frequency difference is greater than the second frequency threshold value, determine that the second coefficient is the charge pump system
Number；
When the absolute value of the frequency difference is less than or equal to the second frequency threshold value, determine that third coefficient is the charge
Pump coefficient；
Wherein, the first frequency threshold value is greater than the second frequency threshold value, and first coefficient is greater than second coefficient, institute
The second coefficient is stated greater than the third coefficient.
6. a kind of timing controller, which is characterized in that the timing controller includes phaselocked loop, and the phaselocked loop includes electricity
Lotus pump assembly, the charge pump components include:
Selection circuit；And
At least two charge pumps, the charge pump is connected to the output end of the selection circuit, and each charge pump has not
Same charge pump coefficient.
7. timing controller as claimed in claim 6, which is characterized in that the phaselocked loop includes:
Phase discriminator, the input terminal of the phase discriminator are set as receiving the initial clock signal or the feedback clock signal, institute
The output end for stating phase discriminator is connected to the input terminal of the selection circuit；And
Voltage controlled oscillator, the input terminal of the voltage controlled oscillator are connected to the output end of the charge pump, the voltage controlled oscillator
Output end be set as output target clock signal.
8. timing controller as claimed in claim 7, which is characterized in that the timing controller includes:
Frequency divider, the input terminal of the frequency divider are connected to the output end of the voltage controlled oscillator, the output end of the frequency divider
It is connected to the input terminal of the phase discriminator.
9. timing controller as claimed in claim 7 or 8, which is characterized in that the selection circuit includes:
Judge that sub-circuit, the input terminal of the judgement sub-circuit are connected to the output end of the phase discriminator, the judgement sub-circuit
It is set as the frequency difference exported according to the phase discriminator, generates control signal；
Sub-circuit is controlled, the input terminal of the control sub-circuit is connected to the output end of the judgement sub-circuit；And
Sub-circuit is switched, the input terminal of the switch sub-circuit is connected to the output end of the control sub-circuit, switch
Circuit includes at least two switches being arranged in a one-to-one correspondence with the charge pump, and the switch sub-circuit is according to the control signal
Control each switch conduction or shutdown.
10. a kind of display device, which is characterized in that the display device includes:
Display panel；And
Timing controller as described in any one of claim 6 to 9, the timing controller and display panel electricity
Connection.
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