CN109817570B - Metal connecting line structure of compound semiconductor and manufacturing method thereof - Google Patents
Metal connecting line structure of compound semiconductor and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a metal connecting line structure of a compound semiconductor and a manufacturing method thereof, wherein the method comprises the steps of forming a metal adhesion layer and an electroplating seed layer above a first metal layer, forming an electroplating metal layer through an electroplating process and forming a protective layer; in the process of etching the metal adhesion layer and the electroplating seed layer after the electroplating process, the etching degree of the metal adhesion layer is controlled in a mode of forming the side wing of the second dielectric layer on the exposed metal side wall, so that the edge of the metal adhesion layer in the obtained structure is positioned between the edge of the electroplating metal layer and the edge of the side wing, the situation that the metal adhesion layer extends into the lower part of the electroplating metal layer is avoided, the adhesion capacity of the metal and the protective layer is improved, cracks are prevented from being generated between the protective layer and the metal, the shape of the metal layer meets the requirement, and the reliability of a device is improved.
Description
Technical Field
The present invention relates to a compound semiconductor device and a manufacturing process thereof, and more particularly, to a metal interconnection structure of a compound semiconductor and a manufacturing method thereof.
Background
In the semiconductor production process, the preparation method of the metal layer is divided into two methods of evaporation and electroplating. The cost of the electroplating process is lower than that of the evaporation process, and the electroplating preparation method is introduced into the preparation of the metal connection structure of the compound semiconductor circuit. For example, referring to fig. 1, a conventional metal interconnection structure has a first metal layer M1 and a second metal structure M2 disposed above and below the first metal layer, wherein the second metal structure M2 can be formed by an electroplating process and is covered with a passivation layer. The conventional electroplated second metal structure M2 includes an adhesion layer, a seed layer and an electroplating layer stacked in this order, wherein the seed layer and the electroplating layer constitute a conductive layer. However, due to the requirement of the electroplating process, the thickness of the photoresist is relatively thick, and the cross-sectional shape of the second metal structure M2 formed by the subsequent process does not meet the process requirements, specifically, the adhesion layer for electroplating is formed under the electroplated layer (see the circle in fig. 1), and the appearance easily causes the adhesion with the protective layer on the upper layer to be reduced or broken, thereby causing reliability problems.
Disclosure of Invention
The present invention is directed to overcome the deficiencies of the prior art and to provide a metal interconnection structure of a compound semiconductor and a method for fabricating the same.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a method for manufacturing a metal connection line structure of a compound semiconductor comprises the following steps:
1) providing a wafer with a part of device manufacturing process completed, wherein a first metal layer is arranged on the wafer;
2) depositing a first dielectric layer on the structure;
3) coating an insulating layer, and etching the insulating layer to form an opening above the first metal layer;
4) depositing a metal adhesion layer and an electroplating seed layer in sequence;
5) coating a photoresist, and forming a display window corresponding to the opening through exposure and development, wherein the width of the display window is larger than that of the opening;
6) depositing a plating metal layer with the thickness higher than that of the opening in the display window through a plating process, and then stripping the photoresist;
7) etching the electroplating seed layer and the metal adhesion layer in sequence, and controlling the etching degree of the metal adhesion layer in a mode of forming a second dielectric layer side wing on the exposed metal side wall;
8) and depositing a protective layer.
Optionally, step 7) comprises the following substeps: depositing a second dielectric layer on the structure formed in the step 6); performing dry etching on the second dielectric layer to leave side wings attached to the side walls of the electroplated metal layer; etching to remove the exposed electroplating seed layer; and etching to remove the exposed metal adhesion layer.
Optionally, step 7) comprises the following substeps: etching to remove the exposed electroplating seed layer; depositing a second dielectric layer on the surface of the structure; performing dry etching on the second dielectric layer to leave side wings attached to the side walls of the electroplating metal layer and the electroplating seed layer; and etching to remove the exposed metal adhesion layer.
Optionally, the metal adhesion layer is TiW, and the thickness is 10-100 nm.
Optionally, the electroplating seed layer and the electroplating metal layer are both Au, wherein the thickness of the electroplating seed layer is 100-600 nm, and the thickness of the electroplating metal layer is 2-8 μm.
Optionally, the second dielectric layer and the protective layer are both SiN.
Optionally, the thickness of the second dielectric layer is 200-600 nm, and the thickness of the protective layer is 200-1000 nm.
Optionally, the opening angle is 45 ° to 90 °, and the display window angle is 70 ° to 90 °.
Optionally, in step 8), before depositing the protective layer, a step of forming a Ti layer on top of the electroplated metal layer is further included.
The metal connecting line structure of the compound semiconductor manufactured by the method comprises a wafer, a first metal layer, a first dielectric layer, an insulating layer, a metal adhesion layer, an electroplating seed layer, an electroplating metal layer, a second dielectric layer side wing and a protective layer; the first metal layer is arranged in a preset area on the wafer, the first dielectric layer covers the wafer and the surface of the first metal layer, the insulating layer is arranged on the first dielectric layer and is provided with an opening corresponding to the upper part of the first metal layer, the metal adhesion layer, the electroplating seed layer and the electroplating metal layer sequentially cover the surface of the opening and extend to the surface of the insulating layer covering two sides of the opening, the side wing of the second dielectric layer is at least adhered to the side wall of the electroplating metal layer, and the edge of the metal adhesion layer is positioned between the edge of the electroplating metal layer and the edge of the side wing of the second dielectric layer; the protective layer is arranged on the surface of the structure.
The invention has the beneficial effects that:
the etching edge of the metal adhesion layer is controlled to be positioned between the edge of the electroplated metal layer and the edge of the flank through the arrangement of the flank of the second dielectric layer before the metal adhesion layer is etched, the situation that the metal adhesion layer goes deep under the electroplated metal layer is avoided, the adhesion capability of the metal and the protective layer is improved, cracks are avoided between the protective layer and the metal, the shape of the metal layer meets the requirement, the reliability of a device is improved, the yield of a manufacturing process and the service life of a product are improved, the popularization of an electroplating process in the manufacture of the metal layer is facilitated, and the cost is reduced. In addition, by the preparation method, two or more metal layers can be prepared, the connection reliability of the metal layers is ensured, and the application range is wide.
Drawings
FIG. 1 is a prior art electron micrograph;
FIG. 2 is a process flow diagram of example 1;
FIG. 3 is a schematic structural view of embodiment 1;
FIG. 4 is a partial enlarged view of portion A of FIG. 3;
FIG. 5 is a partial process flow diagram of example 2, in which the process sequence repeated in example 1 is omitted;
FIG. 6 is a schematic structural view of embodiment 2;
fig. 7 is a partially enlarged view of a portion B in fig. 6.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. The drawings are only schematic and can be easily understood, and the specific proportion can be adjusted according to design requirements. The above and below are described as being formed first and formed last, respectively, with respect to the order in which the layers are formed.
Example 1
Referring to fig. 2, the manufacturing method of this embodiment includes the following steps:
1. providing a wafer 1 with a part of device manufacturing process completed, wherein the wafer 1 can be a III-V compound semiconductor wafer, and a first metal layer 2 is arranged on the wafer 1;
2. depositing a first dielectric layer 3 (such as SiN) by adopting a PECVD mode;
3. coating polyimide as an insulating layer 4 by a spin coating method, wherein the purpose is to manufacture a flattened interface, then coating a photoresist on the surface of the polyimide, and carrying out exposure and development, wherein the photoresist angle after development is between 45 and 90 degrees, so that the angle of the electroplated metal can meet the requirements; etching the polyimide by a dry etching method to form an opening 41 above the first metal layer 2, wherein the angle of the opening 41 inherits the angle of the photoresist; the angle here refers to θ in the figure;
4. preparing a metal adhesion layer 5 on the surface by using a physical vapor deposition method, wherein the metal adhesion layer 5 can be TiW, the thickness of the metal adhesion layer 5 is 10-100 nm, preparing a layer of gold as an electroplating seed layer 6 by using the physical vapor deposition method, and the thickness of the electroplating seed layer 6 can be 100-600 nm;
5. coating a photoresist 7, and forming a display window 71 corresponding to the opening 41 through exposure and development, wherein the width of the display window 71 is greater than that of the opening 41, the thickness of the photoresist is 2-10 mu m, and the angle of the display window 71 is 70-90 degrees, and the angle is beta in the figure;
6. depositing an electroplating metal layer 8 in the display window 71 through an electroplating process, wherein the electroplating metal layer 8 can be gold, and the thickness of the gold is higher than the opening 41 and lower than the display window 71 and can be 2-8 μm; stripping the photoresist 7 by chemical liquid medicines such as N-methyl pyrrolidone, isopropanol, acetone and the like to leave a primary required metal pattern;
7. depositing a second dielectric layer 9 by using a PECVD method and the like, wherein the second dielectric layer 9 is SiN and has the thickness of 200-600 nm;
8. dry etching of SiN is carried out on the surface of the wafer by RIE or ICP, and a layer of side wing 91 of SiN is left on the side wall of the electroplated metal layer 8 due to the dry etching;
9. removing the exposed plating seed layer 6 (the remaining plating seed layer 6a) by using a reverse plating method or a wet etching method, and etching away the exposed metal adhesion layer 5 (the remaining metal adhesion layer 5a) by using dry etching or wet etching; the metal adhesion layer is protected by a flank 91 so that TiW side etching is controlled below SiN;
10. defining a pattern of Ti to be evaporated on the top of the wafer by using a photo-resist, depositing Ti on the surface of the wafer by using a metal evaporation method, stripping the photo-resist by using chemical liquid medicines such as N-methyl pyrrolidone, isopropanol, acetone and the like, and leaving a Ti layer 10 on the top of an electroplated metal layer 8;
11. a SiN protective layer 11 is deposited on the surface of the wafer in a PECVD mode, and the thickness of the SiN protective layer is 200-1000 nm.
The obtained metal connection line structure of the compound semiconductor is shown in fig. 3, and comprises a wafer 1, a first metal layer 2, a first dielectric layer 3, an insulating layer 4, a metal adhesion layer 5a, a plating seed layer 6a, a plating metal layer 8, a second dielectric layer flank 91, a Ti layer 10 and a protective layer 11. The first metal layer 2 is arranged in a preset area on the wafer 1, the first dielectric layer 3 covers the wafer 1 and the surface of the first metal layer 2, the insulating layer 4 is arranged on the first dielectric layer 3 and is provided with an opening 41 corresponding to the upper part of the first metal layer 2, and the metal adhesion layer 5a, the electroplating seed layer 6a and the electroplating metal layer 8 sequentially cover the surface of the opening 41 and extend to the surface of the insulating layer 4 covering two sides of the opening 41. Referring to fig. 3 and 4, the wings 91 are attached to the sidewalls of the plated metal layer 8, and the edges of the metal adhesion layer 5a and the plating seed layer 6a are located between the edges of the plated metal layer 8 and the edges of the second dielectric layer wings 91. The Ti layer 10 is arranged on the top of the electroplated metal layer 8, the protective layer 11 covers the surface of the structure, and the protective layer 11 can be perforated according to requirements.
Example 2
Referring to fig. 5, the manufacturing method of this embodiment includes the following steps:
steps 1-6 reference example 1;
7. removing the exposed plating seed layer 6 (the remaining plating seed layer 6b) by using a reverse plating method or a wet etching method;
8. depositing a second dielectric layer 9 'on the surface of the wafer by using a PECVD method and the like, wherein the second dielectric layer 9' is SiN and has the thickness of 200-600 nm;
9. dry etching of SiN is performed on the surface of the wafer by RIE or ICP, and a layer of side wing 91' of SiN is left on the side wall of the metal (including the side wall of the electroplating metal layer 8 and the electroplating seed layer 6b) due to the dry etching;
10. removing the exposed metal adhesion layer 5 (the residual metal adhesion layer 5b) by dry etching, and protecting the TiW side etching by using a side wing 91' to control the etching below the SiN;
11. defining a pattern of Ti to be evaporated on the top of the wafer by using a photo-resist, depositing Ti on the surface of the wafer by using a metal evaporation method, stripping the photo-resist by using chemical liquid medicines such as N-methyl pyrrolidone, isopropanol, acetone and the like, and leaving a Ti layer 10 on the top of an electroplated metal layer 8;
12. a SiN protective layer 11' is deposited on the surface of the wafer in a PECVD mode, and the thickness of the SiN protective layer is 200-1000 nm.
The obtained metal connection line structure of the compound semiconductor is shown in fig. 6, and comprises a wafer 1, a first metal layer 2, a first dielectric layer 3, an insulating layer 4, a metal adhesion layer 5b, a plating seed layer 6b, a plating metal layer 8, a second dielectric layer wing 91 ', a Ti layer 10 and a protective layer 11'. The first metal layer 2 is arranged in a preset area on the wafer 1, the first dielectric layer 3 covers the wafer 1 and the surface of the first metal layer 2, the insulating layer 4 is arranged on the first dielectric layer 3 and is provided with an opening 41 corresponding to the upper part of the first metal layer 2, and the metal adhesion layer 5b, the electroplating seed layer 6b and the electroplating metal layer 8 sequentially cover the surface of the opening 41 and extend to the surface of the insulating layer 4 covering the two sides of the opening 41. Referring to fig. 6 and 7, the wings 91 'are attached to the sidewalls of the plated metal layer 8 and the plating seed layer 6b, and the edges of the metal attachment layer 5b are located between the edges of the plated metal layer 8 and the second dielectric layer wings 91'. The Ti layer 10 is arranged on the top of the electroplated metal layer 8, the protective layer 11 'covers the surface of the structure, and the protective layer 11' can be perforated according to requirements.
Example 3
According to practical requirements, after step 2 of example 1 or 2, steps 3 to 9 (or steps 3 to 10) of example 1 or steps 3 to 10 (or steps 3 to 11) of example 2 are repeated to form a multi-metal layer laminated structure, and then a protective layer is formed.
The above embodiments are merely provided to further illustrate the metal line structure of a compound semiconductor and the method for fabricating the same according to the present invention, but the present invention is not limited to the embodiments, and any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical spirit of the present invention fall within the scope of the present invention.
Claims (8)
1. A method for manufacturing a metal connection line structure of a compound semiconductor is characterized by comprising the following steps:
1) providing a wafer with a part of device manufacturing process completed, wherein a first metal layer is arranged on the wafer;
2) depositing a first dielectric layer on the structure;
3) coating an insulating layer, and etching the insulating layer to form an opening above the first metal layer;
4) sequentially depositing a metal adhesion layer and an electroplating seed layer, wherein the metal adhesion layer is TiW;
5) coating a photoresist, and forming a display window corresponding to the opening through exposure and development, wherein the width of the display window is larger than that of the opening;
6) depositing a plating metal layer with the thickness higher than that of the opening in the display window through a plating process, and then stripping the photoresist;
7) etching to remove the exposed electroplating seed layer, depositing a second dielectric layer on the surface of the formed structure, and performing dry etching on the second dielectric layer to leave side wings attached to the electroplating metal layer and the side walls of the electroplating seed layer; etching to remove the exposed metal adhesion layer, and controlling the side etching edge of the metal adhesion layer to be positioned between the edge of the electroplated metal layer and the edge of the side wing through the side wing; the second dielectric layer is SiN, and the thickness of the second dielectric layer is 200-600 nm;
8) and depositing a protective layer.
2. The method of manufacturing according to claim 1, wherein: the thickness of the metal adhesion layer is 10-100 nm.
3. The method of manufacturing according to claim 1, wherein: the electroplating seed layer and the electroplating metal layer are both Au, wherein the thickness of the electroplating seed layer is 100-600 nm, and the thickness of the electroplating metal layer is 2-8 μm.
4. The method of manufacturing according to claim 1, wherein: the protective layer is SiN.
5. The method of manufacturing according to claim 4, wherein: the thickness of the protective layer is 200-1000 nm.
6. The method of manufacturing according to claim 1, wherein: the angle of the opening is 45-90 degrees, and the angle of the display window is 70-90 degrees.
7. The manufacturing method according to claim 1 or 3, characterized in that: in step 8), before depositing the protective layer, a step of forming a Ti layer on top of the electroplated metal layer is further included.
8. A metal wiring structure of a compound semiconductor manufactured by the method of any one of claims 1 to 7, characterized in that: the chip comprises a chip, a first metal layer, a first dielectric layer, an insulating layer, a metal adhesion layer, a plating seed layer, a plating metal layer, a second dielectric layer flank and a protective layer; the first metal layer is arranged in a preset area on the wafer, the first dielectric layer covers the wafer and the surface of the first metal layer, the insulating layer is arranged on the first dielectric layer and is provided with an opening corresponding to the upper part of the first metal layer, the metal adhesion layer, the electroplating seed layer and the electroplating metal layer sequentially cover the surface of the opening and extend to the surface of the insulating layer covering two sides of the opening, the second dielectric layer side wing is adhered to the side walls of the electroplating metal layer and the electroplating seed layer, and the edge of the metal adhesion layer is positioned between the edge of the electroplating metal layer and the edge of the second dielectric layer side wing; the protective layer is arranged on the surface of the structure.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4810332A (en) * | 1988-07-21 | 1989-03-07 | Microelectronics And Computer Technology Corporation | Method of making an electrical multilayer copper interconnect |
| US20100190332A1 (en) * | 2008-09-15 | 2010-07-29 | Abdalla Aly Naem | Method of Forming a Copper Topped Interconnect Structure that has Thin and Thick Copper Traces |
| CN104241234A (en) * | 2013-06-11 | 2014-12-24 | 索尼公司 | Semiconductor device and manufacturing method thereof |
| US20150137374A1 (en) * | 2013-11-19 | 2015-05-21 | International Business Machines Corporation | Copper wire and dielectric with air gaps |
| CN107275380A (en) * | 2017-06-14 | 2017-10-20 | 厦门市三安集成电路有限公司 | A kind of metal level of compound semiconductor and preparation method thereof |
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| US9620580B2 (en) * | 2013-10-25 | 2017-04-11 | Mediatek Inc. | Semiconductor structure |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4810332A (en) * | 1988-07-21 | 1989-03-07 | Microelectronics And Computer Technology Corporation | Method of making an electrical multilayer copper interconnect |
| US20100190332A1 (en) * | 2008-09-15 | 2010-07-29 | Abdalla Aly Naem | Method of Forming a Copper Topped Interconnect Structure that has Thin and Thick Copper Traces |
| CN104241234A (en) * | 2013-06-11 | 2014-12-24 | 索尼公司 | Semiconductor device and manufacturing method thereof |
| US20150137374A1 (en) * | 2013-11-19 | 2015-05-21 | International Business Machines Corporation | Copper wire and dielectric with air gaps |
| CN107275380A (en) * | 2017-06-14 | 2017-10-20 | 厦门市三安集成电路有限公司 | A kind of metal level of compound semiconductor and preparation method thereof |
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