CN109791951B - 具有改进的阈值电压控制的沟槽垂直jfet - Google Patents
具有改进的阈值电压控制的沟槽垂直jfet Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 38
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 10
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 10
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 6
- 229910002601 GaN Inorganic materials 0.000 claims description 5
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Abstract
可以通过将沟槽蚀刻到第一掺杂类型的衬底的顶侧中以形成台面来产生一种沟槽JFET。衬底由背侧漏极层、中间漂移层和顶侧源极层构成。蚀刻穿过源极层并部分地进入漂移层。使用第二类型的掺杂在沟槽的侧部和底部形成栅极区。使用第一种类的掺杂经由成角度注入在垂直栅极段后面形成垂直沟道区,以提供改进的阈值电压控制。可选地,衬底可以包括在漂移层和源极层之间的轻掺杂沟道层,使得台面包括与注入的垂直沟道区形成较强的对比的轻掺杂沟道区。
Description
相关申请的交叉引用
本申请要求于2016年9月9日提交的题为“Trench Vertical JFET with ImprovedThreshold Voltage Control”的美国专利申请第15/260,548号的权益,该申请是于2015年3月10日提交的题为“Trench Vertical JFET with Improved Threshold VoltageControl”的美国专利申请第14/642,936号的部分继续申请,这两个申请的全部内容通过引用合并至本文中。
技术领域
本公开内容属于高电流高电压半导体器件领域。例如,公开了高电压常通和常断垂直结型场效应晶体管(VJFET)及其制造方法。
背景技术
由诸如碳化硅(SiC)和氮化镓(GaN)的材料制成的垂直结型场效应晶体管(JFET)在诸如功率因数校正(PFC)器件、DC-DC转换器、DC-AC逆变器和电机驱动器的电力电子电路中是有用的。垂直JFET器件可以包括活性单元区和终止区。
发明内容
可以通过将沟槽蚀刻到第一掺杂类型的衬底的顶侧来产生一种沟槽JFET。衬底由背侧漏极层、中间漂移层和顶侧源极层构成。在沟槽之间产生台面。蚀刻穿过源极层并且可以部分地延伸到漂移层中。使用第二类型的掺杂在沟槽的侧部和底部上形成栅极区。使用第一种类的掺杂经由成角度注入在垂直栅极段后面形成垂直沟道区,以提供改进的阈值电压控制。可选地,衬底可以包括在漂移层和源极层之间的轻掺杂沟道层,使得台面包括与注入的垂直沟道区形成较强的对比的轻掺杂沟道区。衬底可以由SiC、GaN和/或其他半导体材料制成。
提供本概要以便以简化的形式介绍选择的概念,这些概念将在下面的详细描述中进一步描述。本概要不旨在标识所要求保护的主题的关键特征或必要特征,也不旨在用于限制所要求保护的主题的范围。此外,所要求保护的主题不限于解决在本公开内容的任何部分中提到的任何或所有缺点的限制。
附图说明
当结合附图阅读时,将进一步理解概要以及以下详细描述。出于说明本发明的目的,在附图中示出了本发明的示例性实施方式;然而,本发明不限于所公开的特定方法、组合和装置。
图1示出了具有成角度注入的栅极的现有技术沟槽JFET的垂直截面图。
图2示出了具有成角度注入的沟道区的沟槽JFET的实施方式的垂直截面图。
图3和图4示出了在制造期间图2的沟槽JFET实施方式的垂直截面图。
图5是针对现有技术和当前提出的技术来比较随变化的台面宽度的阈值电压变化的图表。
图6是沿图4的截面B-B'的示例掺杂浓度分布的曲线图。
图7是具有短的垂直沟道区的替选沟槽JFET的垂直截面图。
图8是具有在台面的基部处包覆栅极区的沟道区的替选沟槽JFET的垂直截面图。
图9是具有在台面的基部和沟槽的底部处包覆栅极区的沟道区的另一替选沟槽JFET的垂直截面图。
具体实施方式
通过参考结合形成本公开内容的一部分的附图和示例所进行的以下详细描述,可以更容易地理解本发明。应理解,本发明不限于在本文中描述和/或示出的特定装置、方法、应用、条件或参数,并且在本文中使用的术语出于仅通过示例描述特定实施方式的目的,并且并不旨在限制要求保护的发明。此外,如在包括所附权利要求的说明书中所使用的,单数形式“一(a)”、“一个(an)”和“该(the)”包括复数,并且对特定数值的引用至少包括该特定值,除非上下文另有明确指示。在本文中使用的术语“多个”意指超过一个。当表示一系列值时,另一实施方式包括从一个特定值和/或到另一特定值。类似地,当通过使用先行词“约”将值表示为近似值时,应当理解,该特定值形成另一实施方式。所有范围都是包括性的且可组合的。
应当理解,为了清楚起见在本文中在不同实施方式的上下文中描述的本发明的某些特征也可以组合在单个实施方式中提供。相反,为了简洁起见在单个实施方式的上下文中描述的本发明的各种特征也可以分别提供或以任何子组合提供。此外,对范围中所陈述的值的引用包括该范围内的每个值。
可以通过将沟槽蚀刻到第一掺杂类型的衬底的顶侧来产生沟槽JFET。衬底由背侧漏极层、中间漂移层和顶侧源极层构成。在沟槽之间产生台面。蚀刻穿过源极层并可以部分地延伸到漂移层中。使用第二类型的掺杂在沟槽的侧部和底部上形成栅极区。使用第一种类的掺杂经由成角度注入在垂直栅极段后面形成垂直沟道区,以提供改进的阈值电压控制。可选地,衬底可以包括在漂移层和源极层之间的轻掺杂沟道层,使得台面包括与注入的垂直沟道区形成较强的对比的轻掺杂沟道区。衬底可以由SiC、GaN和/或其他半导体材料制成。
图1是示例性现有技术沟槽JFET的垂直截面图。这种器件通常包括多个外延层结构以承受期望的阻断电压,所述外延层结构包括衬底150和掺杂有第一种类的掺杂(n或p)的漂移层140。漂移层的顶部是沟道层130,其通常与漂移层相比而较重地掺杂有第一种类的掺杂。最顶层101是第一种类的掺杂的重掺杂源极区。沟槽被蚀刻穿过源极101并进入沟道层130中,但并未穿过沟道层130。这些沟槽的底部和侧壁分别使用垂直注入和成角度注入103来注入,以形成栅极区102。栅极掺杂类型与源极区、沟道区、漂移区和衬底区的掺杂类型相反。实际上,触点(未示出)包括形成到源极区101的源极触点、形成到衬底区150的底部的漏极触点,并且栅极触点被形成到栅极区102。
通过需要施加在栅极和源极之间的电压差来设置这种JFET的阈值电压,以耗尽位于栅极区102之间的沟道区。因此,它关键取决于沟道层130的掺杂和蚀刻沟槽的宽度,其又确定了栅极区102之间的间隔。实际上,这些因素导致驻留在相邻栅极区102之间的电荷的大的变化,其是掺杂水平以及区102之间的空间的乘积。这又导致器件阈值电压的大的变化。这部分地是由于随外延层生长的可能的有限控制水平而导致掺杂水平会波动很大的事实。+/-10%至20%的变化是常见的。栅极区102之间的空间也由于沟槽之间的台面的光刻和蚀刻轮廓变化而波动。在不使用复杂仪器的情况下,这种波动可以是几个0.1um。
图2是具有成角度注入的垂直沟道区的示例性沟槽JFET的垂直截面图。由于器件阈值电压由驻留在栅极区202之间的电荷确定,因此该结构被设计以精确控制该电荷。这通过改变外延结构并使用成角度注入对沟道进行掺杂来实现。与图1中示出的器件类似,图2的JFET在衬底250顶部具有漂移区240。从漂移区240上升的是活性单元台面。在台面顶部是源极层201。衬底250、漂移240和源极201掺杂有第一种类的掺杂。在图2至4中,这些区和沟道区被示出为具有n型的第一种类的掺杂,并且栅极区的第二掺杂种类被示出为p型,使得这些结构形成NPN器件。实际上,可以切换掺杂类型以使用相同的结构来形成PNP器件。
在图2中,沟槽被示出为被蚀刻穿过源极层201并且一直蚀刻穿过轻掺杂沟道芯层230进入漂移层240。因此,与图1的沟道层130相比,图2的沟道芯层230比沟槽浅。沟道芯层230尽可能轻掺杂以使其电荷最小化。沟道芯层230掺杂有第一掺杂类型。例如,对于1200VSiC JFET,可以使用1e16cm-3的漂移层掺杂以及1e15cm-3的沟道芯层掺杂。相比之下,为了产生非常高的电压的JFET,可能需要对漂移和沟道芯层230二者均使用1e15cm-3的掺杂水平,因此在这种情况下,漂移240和沟道芯层230可以是同义的。
沟槽的底部和侧壁使用垂直注入和成角度注入203被注入以形成栅极区202。栅极掺杂类型是第二类型(p或n)的,其与源极区、沟道区、漂移区和衬底区的掺杂类型相反。
垂直沟道区205然后可以沿方向204被成角度注入。垂直沟道掺杂类型是第一掺杂类型的,即,与源极相同的掺杂类型以及与栅极的掺杂类型相反的掺杂类型。该注入可以以高能量完成,以实现与栅极侧壁注入相比的较深的注入。因此,可以在形成栅极区202之后形成垂直沟道区205。
实际上,触点(未示出)包括形成到源极区201的源极触点、形成到衬底区250的底部的漏极触点以及形成到栅极区202的栅极触点。
栅极区202之间的电荷由确定器件阈值电压的电荷袋205控制。区230的背景电荷贡献通过其轻掺杂水平而被最小化,因此不会显著影响阈值。作为示例,可以使栅极区202之间的沟道芯区230的电荷贡献小于驻留在袋205中的电荷的5%。在这种情况下,如果存在大约为20%的区230的掺杂水平变化,则该变化因而将对栅极区202之间的总电荷具有小于1%的影响,因此不会引起任何显著的阈值变化。类似地,如果用于形成沟槽的光刻和蚀刻工艺导致栅极区202之间的台面宽度的显著变化,则这将仅导致由层230贡献的电荷的变化。而且,可以使这种影响非常小。由于栅极区202和注入沟槽袋205相对于沟槽侧壁的深度由注入角度和能量精确地确定——其可以被控制为优于3%的精度,所以即使台面宽度(即沟槽区之间的宽度)改变,栅极区202之间的电荷也是基本上不变的。通过这些手段,基本上抵消了由光刻和蚀刻工艺变化引起的外延层掺杂变化和台面宽度变化二者的影响。
例如,为了产生1200V SiC JFET,可以使用1e16cm-3的漂移层掺杂以及1e15cm-3的沟道芯层掺杂和2e19cm-3的源极区掺杂进行掺杂。如果台面为1μm宽,则沟道层电荷为:
1e15*1μm=1e11cm-2
垂直沟道注入电荷袋取决于期望的阈值。对于宽度为0.2μm的两个区中的每一个,典型的数字可以是1e17cm-3的掺杂。在这些充电袋中的每侧的电荷袋的情况下,袋中的总电荷为:
2*1e17cm-3*0.2μm=4e12cm-2
换句话说,在注入的沟道区中将存在比在沟道芯层中多四十倍的电荷。因此,注入的电荷主导电压阈值影响。
图3和图4是图2的沟槽JFET在其制造期间的不同点处的垂直截面图。在图3中,在沟槽被蚀刻穿过轻掺杂沟道层230之后施加栅极注入203。在硬掩模层310就位的情况下完成注入。硬掩模层310可以包括氧化物、金属或上述两者。由于栅极注入掺杂剂具有与源极相反的极性,因此在标准垂直JFET工艺中也使用该硬掩模层310来防止栅极注入对源极区201进行反掺杂。栅极注入203包括以角度α的注入。基于沟槽深度、硬掩模层310厚度和沟槽宽度中的最差情况评估来选择角度α。这是为了确保成角度的注入束不被相邻的台面遮蔽。设置注入能量和电荷以确保存在足够的电荷来供应耗尽区的栅极侧,以支持远高于器件的最大栅源电压额定值的栅源击穿。例如通过在栅极注入203中包括垂直注入或不太急剧的注入,底部的栅极掺杂剂202与侧壁相比可以被布置得较深并且掺杂到较高的水平。沟槽底部的较高掺杂剂水平是有帮助的,因为这是通常形成栅极触点的地方。
在图4中,去除硬掩模层310,然后以角度β执行沟道注入204。实际上,可以在硬掩模310就位的情况下执行沟道注入204。然而,先去除硬掩模层310使得能够以较大的角度β施加沟道注入204。这又使得较容易地将电荷袋205布置得与栅极相比而较深,而不需要采用非常高的注入能量。
在图4中未示出的是,在沟道注入期间,器件的边缘区例如终止区可能需要与沟道注入204屏蔽开,使得它不影响除其中要发生导通状态下的电流导通的活性JFET单元之外的任何区。
图4的结构示出了沿侧壁的沟道注入的期望深度接近栅极区的深度。实际上,它可能稍微较浅或较深。如果太浅,则将产生较高的导通电阻但会产生较好的断开状态阻断,而如果太深则将产生相反的情况。还允许使该沟道注入如此深以使其沿侧部和底部包覆栅极区302。然后必须通过减少漂移区240掺杂来补偿阻断能力的下降,使得仍然可以满足目标击穿额定值。
考虑到外延厚度和沟槽蚀刻深度控制的正常工艺变化,通常(但并非总是)优选将沟道层230修改为尽可能轻掺杂,并且减小其深度,使得沟槽将被蚀刻成直接穿过它。在较高的阻断电压(例如,对于4H-SiC大于3300V)下,漂移区掺杂足够轻,使得沟道层230掺杂可以与漂移层掺杂相同。
图5示出了利用注入波动参数、外延生长参数和台面宽度参数的阈值电压控制的精确度的结果。线条显示了在所有其他参数保持不变的情况下对台面宽度变化的敏感度。线条周围的阴影区表示由外延层掺杂和注入控制变化引起的附加波动。
本文中描述的沟槽JFETS的几何形状可以显著变化。例如,在图2、图3和图4中,源极区201的典型垂直厚度可以在0.1与1μm之间,并且源极区201之外的沟槽的深度可以在0.5到3μm的范围内。例如,台面和沟槽的宽度通常可以在0.3与2μm之间。在沟槽底部的下方延伸的p+栅极区202通常可以从0.2μm延伸到2μm。沟道注入区205可以延伸超出p+栅极区202达例如0.1至0.5μm。当然,取决于期望的操作特性,其他几何形状是可能的。
在台面的芯处的n-区230的几何形状和掺杂影响诸如图2、图3和图4中所示的沟槽JFET的操作。为了优化阈值电压的控制,区230的掺杂水平应当远低于漂移区240和注入沟道区205的掺杂水平。例如,区230的掺杂水平可以比漂移区240的掺杂水平低至少10倍并且比注入沟道205中的峰值浓度低10到100倍。例如,对于650V常通器件,漂移区240可以被掺杂成在2e16cm-3到3e16cm-3的范围内,并且n-区230可以以1e15cm-3被掺杂,而注入沟道区205中的峰值浓度可以在4e17cm-3与4e18cm-3之间。由于区230中的掺杂水平非常低,台面宽度的变化对台面区中的净N-电荷几乎没有影响,这又使得阈值电压(Vth)对于这种工艺变化是不变的。
在常通JFET的形成中,沟道峰值浓度可以非常高,例如4e17cm-3至4e18cm-3。由于可能要求栅源Vgs=-15V至-20V以完全关断这种器件,因此可能有必要具有例如至少30V至40V的栅源击穿电压,使得实际上可以以低的漏电流来施加这种反向偏置。出于该原因,可以减小P栅极侧壁浓度,并且沟道注入205的峰值可以与结间隔开,以较深地进入台面区。这又产生具有较高击穿电压的渐变结。实际上,在该器件中,甚至源极区201被掺杂成使得靠近结的下部与p栅极形成类似的渐变结。
图6示出了沿图4的截面B-B'的示例掺杂分布。在与图4的区202内的截面线B-B'的一部分对应的曲线图中的点B和650之间的p栅极区中,杂质浓度可以在例如2e18cm-3与5e18cm-3之间。进入与图6上的点650至652之间的区对应的图4的注入沟道区205,浓度下降,并且在点654处转变为n型,然后在再次下降到与图4的区230对应的在点B'处的台面的芯处发现的较低值之前,在点654处上升至峰值。在点654处的沟道205的峰值n型浓度可以例如比在点B'处大10到100倍,从而确保注入沟道205的掺杂主导针对垂直JFET 400的阈值电压的确定。
为了最佳性能,可以保持n区230比沟道注入区205浅。如果区230由外延生长来限定,而沟道注入205的深度由注入条件以及沟槽深度确定,则一些工艺容差应当是沟槽JFET设计的一部分。例如,区230可以比注入区205的底部浅0.1至1μm。
图7示出了其中注入沟道区705未延伸得足够远以获得最佳性能的沟槽JFET。如在图2一样,图7的沟槽JFET 700具有衬底250和第一掺杂类型的漂移区240。台面顶部是第一掺杂类型的源极区201。台面的侧部和沟槽的底部是具有第二掺杂类型的栅极材料202。与栅极材料202相邻的台面内是具有第一掺杂类型的注入沟道区705,并且台面的芯处是轻掺杂区230。在该示例中,在注入沟道区705下方的台面内存在区740。这可以使得在栅极区202之间的区740中形成第二JFET区。在常通JFET中,由于区740共享与基于区240相同的掺杂——其可以被选择用于>600V的目标Vds击穿电压,因此JFET可以在比由沟道注入部205设定的目标低得多的电压下夹断。例如,在1200V常通JFET中,如果在区240和740中外延掺杂为8e15cm-3,则虽然针对-6至-8V的目标Vth的沟道205峰值掺杂为1e18cm-3,但是较低区740可以具有-2至-4V的Vth,其远离期望值。这也会产生高得多的导通电阻和较低的饱和电流。
为了解决这些问题,可以例如通过使用特定能量的成角度注入和垂直注入来布置沟道注入205,以确保n注入包覆台面底部的p栅极区202的一部分。这确保了沟道底部的Vth比台面芯区230附近的沟道205上部更负,并且不控制器件Vth。这使器件Vth、导通电阻和饱和电流的变化最小化。
图8是具有成角度注入的垂直沟道区的替选沟槽JFET 800的垂直截面图。JFET800的结构类似于图2的JFET 200的结构,具有衬底250、漂移区240和掺杂有第一种类的掺杂的源极区201。源极区201位于台面顶部,该台面具有轻掺杂的芯区230和也具有第一掺杂类型的沟道区805。台面的侧部和沟槽的底部具有栅极区202,栅极区202具有第二种类的掺杂。与图2的沟道区205相比,沟道区805例如在台面下方延伸并且包覆沟槽底部的栅极202的一部分的下方。这通过调节用于形成沟道区805的注入804的角度和能量来实现。使用诸如区805的包覆沟道区具有在JFET800处于导航模式RDSon时减小漏极至源极电阻的效果。
图9是具有成角度注入的垂直沟道区的另一替选沟槽JFET 900的垂直截面图。JFET 800的结构类似于图2的JFET 200和图6的JFET 800的结构,具有衬底250、漂移区240和掺杂有第一种类的掺杂的源极区201。源极区201位于台面顶部,该台面具有轻掺杂的芯区230和也具有第一掺杂类型的沟道区905。台面的侧部和沟槽的底部具有栅极区202,栅极区202具有第二种类的掺杂。与图6的沟道区805相比,沟道区905例如不仅在台面下方延伸,而且包覆沟槽底部的栅极202的全部的下方。这通过调节用于形成区805的注入904的角度和能量来实现。而且,使用诸如区905的包覆沟道区具有减小RDSon的效果。
示例
在本文中的概念可以实施在沟槽JFET晶体管中,该沟槽JFET晶体管包括例如:具有重掺杂的背侧漏极区和中等掺杂的顶侧衬底漂移区的衬底,漏极区和漂移区具有第一掺杂类型;从漂移区顶部延伸的活性单元台面,台面具有衬底材料并通过切入衬底材料的沟槽分隔开;在台面顶部处的重掺杂源极区,源极区具有第一掺杂类型;在台面的底部中心处的中等掺杂的台面漂移区,台面漂移区具有第一掺杂类型;沟槽表面上的重掺杂栅极区,栅极区具有与第一掺杂类型相反的第二掺杂类型;以及在沟槽的垂直壁上的栅极区的一部分与台面的中心之间的成角度注入掺杂的垂直沟道区,成角度注入掺杂的垂直沟道区延伸基本上台面的高度,并且具有第一掺杂类型并且具有高于漂移区的掺杂水平。这种沟槽JFET晶体管可以包括碳化硅、氮化镓和/或其他半导体材料。这种沟槽JFET晶体管还可以包括在台面中间处的轻掺杂沟道芯区,沟道芯区具有第一掺杂类型,沟道芯区在成角度注入较高掺杂沟道区之间水平延伸并且从源极区向下垂直延伸台面高度的一部分。垂直成角度注入掺杂沟道区的掺杂水平可以比漂移区的掺杂水平高几倍,例如高五倍或十倍或更多。
可以根据特定的设计目标例如间隙和/或阈值电压来调整精确的掺杂水平。通常,背侧漏极区与漂移区相比而较为重掺杂。这样做是为了有助于背侧欧姆接触或欧姆区形成。类似地,源极区相对于漂移区被重掺杂,也是为了产生接触或接触区。栅极区也被重掺杂,但是具有与漏极区、漂移区和源极区的掺杂类型相反的掺杂类型。在台面中间处的可选的轻掺杂沟道芯区与漂移区相比可以被较轻掺杂。
在本文中的概念可以体现在由第一掺杂类型的衬底制造沟槽JFET的方法中,其中,例如,衬底包括:重掺杂的背侧漏极区;中心的中等掺杂的漂移区;和顶侧的重掺杂源极区。该方法可以包括:从顶侧将沟槽蚀刻到衬底中以形成包括漂移区材料和源极区材料的台面;在沟槽的底部和侧部注入第二掺杂类型的掺杂剂以形成栅极区;将第一掺杂的掺杂剂注入穿过沟槽侧部的栅极区并进入台面。衬底可以包括碳化硅、氮化镓和/或其他半导体材料。方法还可以包括使用以下衬底,该衬底在漂移区和源极区之间还包括轻掺杂沟道区。在这种情况下,所述工艺还可以包括:当从顶侧将沟槽蚀刻到衬底中时,蚀刻穿过源极区和沟道区,使得台面还包括漂移区材料和源极区材料之间的沟道区材料的一部分。可以设计第一种类的掺杂剂的注入以产生被掺杂成比漂移区高几倍例如高五倍或十倍或更多的垂直成角度注入掺杂的沟道区。
在描述本公开内容的主题的优选实施方式时,如图中所示,为了清楚起见使用了特定术语。然而,所要求保护的主题并不旨在受限于如此选择的特定术语,并且应当理解,每个特定元件包括以类似方式操作以实现类似目的的所有技术等同物。当在本文中使用针对物理性质例如化学式中的化学性质的范围时,旨在包括其中的具体实施方式的范围的所有组合和子组合。
本领域的技术人员将理解,可以对本发明的优选实施方式进行许多改变和修改,并且可以在不脱离本发明的精神的情况下进行这些改变和修改。因此,所附权利要求旨在覆盖落入本发明的真实精神和范围内的所有这些等同变化。
Claims (19)
1.一种沟槽JFET,包括:
衬底,其包括背侧漏极区和顶侧漂移区,所述背侧漏极区和所述顶侧漂移区具有第一掺杂类型;
从所述顶侧漂移区延伸的活性单元台面,其中,所述活性单元台面通过切入所述顶侧漂移区的沟槽分隔开;
在所述台面的顶部处的源极区,所述源极区具有所述第一掺杂类型;
在所述沟槽的表面上的栅极区,所述栅极区具有第二掺杂类型,所述第二掺杂类型与所述第一掺杂类型相反;
垂直沟道区,所述垂直沟道区沿所述台面的高度延伸并且具有所述第一掺杂类型;以及
台面芯区,所述台面芯区具有所述第一掺杂类型并且从所述台面的中心延伸,其中,所述台面芯区的中心处的掺杂浓度比所述顶侧漂移区的掺杂浓度低至少五倍,所述台面芯区比所述垂直沟道区的底部浅0.1μm至1μm;
其中,所述垂直沟道区在所述沟槽的垂直壁上的栅极区的部分与所述台面芯区之间横向延伸,并且其中,所述垂直沟道区的峰值掺杂浓度比所述台面芯区的中心的掺杂水平高至少五倍。
2.根据权利要求1所述的沟槽JFET,其中,所述衬底还包括碳化硅。
3.根据权利要求1所述的沟槽JFET,其中,所述衬底还包括氮化镓。
4.根据权利要求1所述的沟槽JFET,其中,所述第一掺杂类型是n型,并且所述第二掺杂类型是p型。
5.根据权利要求1所述的沟槽JFET,其中,所述垂直沟道区的峰值掺杂浓度比所述台面芯区的中心的掺杂水平高至少二十倍。
6.根据权利要求1所述的沟槽JFET,其中,所述垂直沟道区的峰值掺杂浓度比所述台面芯区的中心的掺杂水平高至少五十倍。
7.根据权利要求1所述的沟槽JFET,其中,所述垂直沟道区延伸通过所述台面的底部并且朝向所述沟槽的水平中心在所述栅极区的一部分的下方横向延伸。
8.根据权利要求7所述的沟槽JFET,其中,所述衬底还包括碳化硅。
9.根据权利要求7所述的沟槽JFET,其中,所述衬底还包括氮化镓。
10.根据权利要求7所述的沟槽JFET,其中,所述第一掺杂类型是n型,并且所述第二掺杂类型是p型。
11.根据权利要求7所述的沟槽JFET,其中,所述垂直沟道区的峰值掺杂浓度比所述台面芯区的中心的掺杂水平高至少二十倍。
12.根据权利要求7所述的沟槽JFET,其中,所述垂直沟道区的峰值掺杂浓度比所述台面芯区的中心的掺杂水平高至少五十倍。
13.根据权利要求1所述的沟槽JFET,其中,所述垂直沟道区延伸通过所述台面的底部并且沿所述沟槽的底部在所述栅极区的下方横向延伸。
14.根据权利要求13所述的沟槽JFET,其中,所述衬底还包括碳化硅。
15.根据权利要求13所述的沟槽JFET,其中,所述衬底还包括氮化镓。
16.根据权利要求13所述的沟槽JFET,其中,所述第一掺杂类型是n型,并且所述第二掺杂类型是p型。
17.根据权利要求1至16中任一项所述的沟槽JFET,其中,所述台面芯区的中心处的掺杂浓度比所述顶侧漂移区的掺杂浓度低至少十倍。
18.根据权利要求1至16中任一项所述的沟槽JFET,其中,所述垂直沟道区的峰值掺杂浓度比所述台面芯区的中心的掺杂水平高至少十倍。
19.根据权利要求1至16中任一项所述的沟槽JFET,其中,所述垂直沟道区的峰值掺杂浓度比所述台面芯区的中心的掺杂水平高至少一百倍。
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