CN109783340A - Test code programming method, IP test method and the device of SoC - Google Patents
Test code programming method, IP test method and the device of SoC Download PDFInfo
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Abstract
Test code programming method, IP test method and the device of a kind of SoC chip are disclosed herein, the test code programming method of the SoC, it include: to cut BOOT code, the code of IP test case is added to the BOOT code, and it is in the BOOT code that preset test instruction is corresponding with the IP test case, obtain test code；The test code is compiled, binary file is generated；Utilize the resolution chart write in advance, the binary file is write into the embedded multi-media card EMMC of the test platform by D2S simulation Xmodem Protocol, the resolution chart includes predefined combinations information, and the combined information includes predefined timing information and level information.The application simplifies the process of code upgrade, has saved the time of upgrading test code.
Description
Technical field
The present invention relates to chip testing technology fields, and in particular to a kind of test code programming method of SoC chip, IP are surveyed
Method for testing and device.
Background technique
In general, system on chip (SoC, System on Chip) is by microprocessor, Analog IP core, digital IP kernel and mutually
Join that bus, memory etc. (or piece external storage control interface) are integrated on a single chip, it be usually customization or face
To the standardized product of special-purpose.In some special application scenarios, chip is designed without setting test pattern (Test
Mode), or for cost consideration, some crucial pins are not encapsulated out, IP cannot be tested at Test Mode leads to volume production
When chip testing coverage rate it is inadequate.
Summary of the invention
In order to solve some or all of IP of chip can not be tested at Test Mode lead to volume production when test coverage it is low
The technical issues of, the embodiment of the invention provides test code programming method, IP test method and the devices of a kind of SoC chip.
This application provides following technical solutions:
A kind of IP test method of system on chip SoC chip, comprising:
SoC chip is obtained by universal asynchronous receiving-transmitting transmitter UART interface and is instructed come the test of test platform；
SoC chip loads the test code in embedded multi-media card EMMC by BOOT CPU, and the test is called to refer to
Corresponding IP test case and configuration register are enabled, IP test is completed；
Wherein, the test code includes that IP test case and its corresponding test instruct.
A kind of test code programming method of system on chip SoC, comprising:
BOOT code is cut, the code of IP test case is added to the BOOT code, and in the BOOT code
Preset test instruction is corresponding with the IP test case, obtain test code；
The test code is compiled, binary file is generated；
Using the resolution chart write in advance, by D2S simulate Xmodem Protocol the binary file write into it is described
The embedded multi-media card EMMC of test platform, the resolution chart include predefined combinations information, the combined information packet
Containing predefined timing information and level information.
Wherein, the cutting BOOT code also wraps before the code of IP test case is added to the BOOT code
It includes: being pre-configured with the test instruction set for SoC chip IP test, the test instruction set includes that at least one described test refers to
It enables.
Wherein, the method also includes: generate for the programming by the binary file programming into the test platform
Program；It is described using the resolution chart write in advance, by D2S simulate Xmodem Protocol the binary file write into it is described
The EMMC of test platform, comprising: using the programming program and be based on the resolution chart, Xmodem Protocol is simulated by D2S
The binary file is write into the EMMC of the test platform.
Wherein, the method also includes: establish in test platform port based on UART protocol, define timing information and
Level information forms the resolution chart based on the port, timing information and level information.
Wherein, the EMMC that the binary file is write into the test platform by D2S simulation Xmodem Protocol,
It include: that the binary file is stored in IRAM by universal asynchronous receiving-transmitting transmitter UART；Again from the UART to SoC
It sends order to read out the binary file from IRAM, programming specifies block into EMMC.
Wherein, the EMMC that the binary file is write into the test platform by D2S simulation Xmodem Protocol,
Include:
Image file is read using C++, by byte storage into vector v ector；
D2S simulation Xmodem Protocol reads the data in vector and is sent to UART_RXD, grabs UART_TXD return value
Judge whether data are sent correct, D2S sends instruction and burns the file for testing code when the UART_TXD return value is correct
Write EMMC.
Wherein, the EMMC that the binary file is write into the test platform by D2S simulation Xmodem Protocol,
Include:
Under xm instruction, Xmodem Protocol is selected to send data in IRAM；
Under go instruction, the second level BOOT started from UART is completed；
Under wm instruction, the data stored in the IRAM write-in EMMC is specified in block.
A kind of IP test device of system on chip SoC chip, comprising:
Module is obtained, for obtaining the test instruction come test platform by UART interface；
Test module, for loading the test code in embedded multi-media card EMMC by BOOT CPU, described in calling
Test instructs corresponding IP test case and configuration register, completes IP test；
Wherein, the test code includes that IP test case and its corresponding test instruct.
A kind of test code programming device of system on chip SoC, comprising:
The code of IP test case is added to the BOOT code, and in institute for cutting BOOT code by generation module
State in BOOT code by preset test instruct it is corresponding with the IP test case, obtain test code；
Collector generates binary file for compiling the test code；
Writing module, for simulating Xmodem Protocol for the binary system text by D2S using the resolution chart write in advance
Part writes into the embedded multi-media card EMMC of the test platform, and the resolution chart includes predefined combinations information, described
Combined information includes predefined timing information and level information.
A kind of system on chip SoC chip, comprising:
IP module；
It is stored with the memory of IP test program；
Processor is configured to execute the operation of IP test method of the IP test program to execute above-mentioned SoC chip.
A kind of test code programming device of system on chip SoC, comprising:
It is stored with the memory of test code programming program；
Processor is configured to execute test code programming of the test code programming program to execute above-mentioned SoC chip
The operation of method.
A kind of computer readable storage medium is stored with computer program on the computer readable storage medium, described
The step of IP test method of above-mentioned SoC chip is realized when computer program is executed by processor.
Another computer readable storage medium is stored with computer program on the computer readable storage medium, institute
The step of stating the test code programming method that above-mentioned SoC is realized when computer program is executed by processor.
On the one hand, through the embodiment of the present invention, the IP that can not be covered under Test Mode can be tested, test is solved and covers
The inadequate problem of lid rate；
On the other hand, it also can avoid the inconvenient problem of code upgrade maintenance in such a way that code is tested in programming, simplify
The process of code upgrade, has saved the time of upgrading test code.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can be by specification, right
Specifically noted structure is achieved and obtained in claim and attached drawing.
Detailed description of the invention
Attached drawing is used to provide to further understand technical solution of the present invention, and constitutes part of specification, with this
The embodiment of application technical solution for explaining the present invention together, does not constitute the limitation to technical solution of the present invention.
Fig. 1 is the application environment exemplary structure schematic diagram of technical scheme；
Fig. 2 is the test code programming method flow schematic diagram of one SoC of embodiment；
The structural schematic diagram for the test code programming device that Fig. 3 is one SoC of embodiment；
The exemplary implementation process schematic diagram for the test code programming method that Fig. 4 is one SoC of embodiment；
Fig. 5 establishes Test Flow programming in 93K test platform for embodiment one and tests example code figure；
Fig. 6 is the flow diagram of the IP test method of two SoC chip of embodiment；
Fig. 7 is the exemplary flow diagram of SoC IP test；
Fig. 8 is that HDMI tests high and low frequency test item and group divides exemplary diagram；
Fig. 9 is the exemplary flow diagram of from the programming Chip ID to EFUSE；
Figure 10 is the structural schematic diagram of the IP test device of two SoC chip of embodiment.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature can mutual any combination.
Step shown in the flowchart of the accompanying drawings can be in a computer system such as a set of computer executable instructions
It executes.Also, although logical order is shown in flow charts, and it in some cases, can be to be different from herein suitable
Sequence executes shown or described step.
It can not be tested at Test Mode to solve some or all of IP of chip, test coverage is low when volume production
Problem, the following technical solutions are proposed by the application, which tests IP in a manner of CPU BOOT, i.e., with CPU BOOT's
Mode calls test case to execute IP test.In addition, the application also provides another technical solution, which is that will survey
Try code conversion be 93K identification resolution chart (Pattern), by D2S simulate Xmodem Protocol will test code programming into
EMMC can call directly corresponding test case when to test IP.
As shown in Figure 1, being the application environment exemplary structure of technical scheme.In the exemplary context of use, adopt
With 93K test platform.Pass through universal asynchronous receiving-transmitting transmitter (UART, Universal between 93K test platform and SoC
Asynchronous Receiver/Transmitter) interface communicated.It is communicated between SoC and EMMC by SDIO.Its
In, simulated on 93K test platform UART protocol by test predetermined it is instruction morphing be loaded into for Pattern it is corresponding general
On asynchronous receiving-transmitting transmitter (UART, Universal Asynchronous Receiver/Transmitter) interface, realize
Communication between 93K test platform and SoC.93K test platform will test binary system (bin) the file programming of code into embedded
Multimedia card (EMMC, Embedded Multi Media Card), SoC are instructed according to the test of 93K test platform, are passed through
BOOT CPU calls corresponding IP test case configuration register in the bin file for testing code in EMMC to realize that the volume production of IP is surveyed
Examination simplifies the escalation process of test code to greatly reduce manual operation.
Fig. 1 is merely illustrative structure.In practical application, the application environment of technical scheme can also use other
Structure.For example, the equipment that other support SoC IP test except 93K test platform can be used, EMMC can also be stored by other
Device replaces.The communication interface between communication interface and SoC and EMMC between 93K test platform and SoC can also use it
His type.
In the application, the various functional modules integrated in SoC include being referred to as intellectual property (IP) kernel in industry, in IP
The functional module of core module or referred to as IP.Herein, these functional modules are referred to as IP module or are referred to as " IP ".One IP
The one or more special functions of module service, the available circuit including exploitation secure permission from each supplier or internal design mould
Block.
The implementation of technical scheme is described in detail below.
Embodiment one
A kind of test code programming method of SoC, as shown in Fig. 2, may include:
Step 201, BOOT code is cut, the code of IP test case is added to the BOOT code, and described
It is in BOOT code that preset test instruction is corresponding with the IP test case, obtain test code；
Step 202, the test code is compiled, binary file is generated；
Step 203, using the resolution chart write in advance, by dynamic to static structure (Dynamic to Static,
D2S) binary file is write into the EMMC of the test platform by simulation Xmodem Protocol, and the resolution chart may include
Predefined combinations information, the combined information include predefined timing information and level information.
In the present embodiment, the cutting BOOT code, before the code of IP test case is added to the BOOT code,
It can also include: the test instruction set being pre-configured with for SoC chip IP test, the test instruction set includes at least one institute
State test instruction.
In the present embodiment, test code compilation is generated into binary system bin file, may include: to establish translation and compiling environment, on demand
Selection compiling option is sought, compiling generates binary system bin file；
In a kind of implementation, the method can also include: generate for by the binary file programming into described
The programming program of test platform；It is described using the resolution chart write in advance, by D2S simulate Xmodem Protocol by described two into
File processed writes into the EMMC of the test platform, comprising: using the programming program and is based on the resolution chart, passes through D2S
The binary file is write into the EMMC of the test platform by simulation Xmodem Protocol.
In a kind of implementation, the method can also include: established in test platform port based on UART protocol,
Timing information and level information are defined, the resolution chart is formed based on the port, timing information and level information.Than
Such as, port (Port) is established in 93K test platform, is defined timing (timing) and level (level) information, is write test chart
Shape (Pattern) and relevant test code (Test Method).For another example, can establish Port based on UART protocol,
Timing, Level, D2S template and relevant Test Method；
It is described Xmodem Protocol to be simulated by D2S the binary file is write into the test in a kind of implementation
The EMMC of platform, comprising: the binary file is stored in IRAM by universal asynchronous receiving-transmitting transmitter UART；Again by institute
It states UART and reads out the binary file from IRAM to SoC transmission order, programming specifies block into EMMC.
It is described Xmodem Protocol to be simulated by D2S the binary file is write into the test in a kind of implementation
The EMMC of platform, comprising: image file is read using C++, by byte storage into vector v ector；D2S simulates Xmodem association
The data that view reads in vector are sent to UART_RXD, and crawl UART_TXD return value judges whether data are sent correct,
D2S, which sends instruction, when the UART_TXD return value is correct will test the file programming of code to EMMC.
It is described Xmodem Protocol to be simulated by D2S the binary file is write into the test in a kind of implementation
The EMMC of platform, comprising: under xm instruction, Xmodem Protocol is selected to send data in IRAM；Go instruction under, complete from
The second level BOOT of UART starting；Under wm instruction, the data stored in the IRAM write-in EMMC is specified in block.
For example, the above method of the present embodiment realizes that process may is that the first step, BOOT code, addition IP test are cut
With obtain test code；Second step, the test code that the compiling first step obtains, generates binary system bin file；Third step is being surveyed
Examination platform defines port, timing, level information, writes the test code under resolution chart and test platform；4th step is being tested
The binary system bin file programming that platform is generated second step by D2S simulation Xmodem Protocol is into EMMC, programming binary system
The bin file combination of binary zero and " 1 " (bin file content be), this step need to know through which kind of interface programming (the
Three steps define port), the level of binary " 0 " and " 1 " of programming is (for example, be that 1.8V represents " 1 " or 3.3V is represented
" 1 "), binary " 0 " and " 1 " duration (timing that third step defines) of programming, and pass through any agreement for " 0 "
" 1 " sends SoC (that is, third step writes code simulation Xmodem Protocol under test platform) to.Third step is flat in test
The preparation of programming is carried out on platform, the 4th step is the process in test platform simulation programming bin file.
Correspondingly, the test code programming device of SoC a kind of is also provided, as shown in figure 3, may include:
The code of IP test case is added to the BOOT code for cutting BOOT code by generation module 31, and
It is in the BOOT code that preset test instruction is corresponding with the IP test case, obtain test code；
Collector 32 generates binary file for compiling the test code；
Writing module 33, for simulating Xmodem Protocol for the binary system by D2S using the resolution chart write in advance
File writes into the EMMC of the test platform, and the resolution chart includes predefined combinations information, and the combined information includes
Predefined timing information and level information.
In a kind of implementation, it can also include: configuration module 34 in above-mentioned test code programming device, can be used in institute
Cutting BOOT code is stated to be pre-configured with before the code of IP test case is added to the BOOT code for SoC chip IP
The test instruction set of test, the test instruction set include at least one described test instruction.
In a kind of implementation, the writing module 33, be particularly used in generation for by the binary file programming into
The programming program of the test platform；Using the programming program and it is based on the resolution chart, Xmodem association is simulated by D2S
The binary file is write into the EMMC of the test platform by view.
In a kind of implementation, above-mentioned writing module 33 can be also used for establishing in test platform based on UART protocol
Port defines timing information and level information, forms the test chart based on the port, timing information and level information
Shape.
In a kind of implementation, above-mentioned writing module 33 for it is described by D2S simulation Xmodem Protocol by the binary system
File writes into the EMMC of the test platform, may include: that the binary file is stored in IRAM by UART；Again by
The UART sends order to SoC and reads out the binary file from IRAM, and programming specifies block into EMMC.
In a kind of implementation, above-mentioned writing module 33 is used for the binary file through D2S simulation Xmodem Protocol
The EMMC for writing into the test platform may include: to read image file using C++, by byte storage into vector v ector；
D2S simulation Xmodem Protocol reads the data in vector and is sent to UART_RXD, and crawl UART_TXD return value judges data
Whether correct send, when the UART_TXD return value is correct, D2S, which sends instruction, will test the file programming of code to EMMC.
In a kind of implementation, above-mentioned writing module 33 is used for the binary file through D2S simulation Xmodem Protocol
The EMMC for writing into the test platform may include: to select Xmodem Protocol to send data in IRAM under xm instruction；?
Under go instruction, the second level BOOT started from UART is completed；Under wm instruction, the data stored in the IRAM write-in EMMC is referred to
Determine in block.
In practical application, in the test code programming device of above-mentioned SoC, generation module 31, collector 32, writing module
33, configuration module 34 can be the combination of software, hardware or both respectively.
Correspondingly, also providing the test code programming device of system on chip SoC a kind of, comprising: be stored with test code and burn
The memory of program writing；Processor is configured to execute operation of the test code programming program to execute the above method.
The implementation process of the present embodiment is described in detail by taking 93K test platform as an example below.
As shown in figure 4, the test code programming process for being applied to 93K test platform may include:
Step 401, power on, powered on to SoC；
Step 402, as needed, switch relay state；
Step 403, the Pattern that operation BOOT needs, into level-one BOOT；
Step 404, it sends and instructs to bootrom, selection is transmitted data in IRAM with Xmodem Protocol, will test code
It is stored in IRAM；
Step 405, it sends and instructs to bootrom, complete second level BOOT；
Step 406, it sends and instructs to bootrom, the test code being stored in IRAM write-in EMMC is specified in block.
In the present embodiment, establishing test Test Flow in 93K test platform can be with the process for simulating manual programming
It is: reads image file with C++, by byte storage into vector, D2S simulation Xmodem Protocol sends data to UART_
RXD grabs UART_TXD return value by the Digital Capture of test platform and judges whether data are sent correct, finally
D2S, which sends instruction, will test code file programming to EMMC.
In the present embodiment, by the way of UART+EMMC, UART starting is first passed through, test code is stored in IRAM,
Test code is read out from IRAM again, programming is specified in block into EMMC, by establishing programming flow, it is only necessary to update and survey
The binary system bin file (test code file for generating after compiling) for trying code, the programming flow that reruns can will be new
Code programming is tested into EMMC, enormously simplifies escalation process, it is not only easy to operate, but also do not need by auxiliary tool,
Test code is facilitated to upgrade in the update of testing factory.
As shown in figure 5, the Test Flow exemplary diagram established for 93K test platform.Wherein, Xm_bootrom be to
Bootrom sends xm instruction, is ready for sending data；Xmodem_bootrom is that Xmodem Protocol is selected to send data to IRAM
In；The second level BOOT started from UART is completed in go instruction；Wm instruction specifies the data stored in IRAM write-in EMMC in block.
The present embodiment also provides a kind of computer readable storage medium, and meter is stored on the computer readable storage medium
The step of calculation machine program, the computer program realizes the test code programming method of above-mentioned SoC when being executed by processor.Specifically
For, the computer program realizes step 201~step of the test code programming method of the SoC when being executed by processor
203, other details can refer to the part of method above.
Embodiment two
The present embodiment provides a kind of IP test methods of SoC chip, as shown in fig. 6, may include:
Step 601, SoC chip is instructed by UART interface acquisition come the test of test platform；
Step 602, SoC chip loads the test code in EMMC by BOOT CPU, calls the test instruction opposite
The IP test case and configuration register answered complete IP test；
Wherein, the test code includes that IP test case and its corresponding test instruct.
In a kind of implementation, the exemplary implementing procedure of the IP test method of above-mentioned SoC chip, as shown in fig. 7, can be with
Include:
Step 701, the instruction set of test is defined, the corresponding different IP test item of different instructions, when test sends instruction
Different test cases can be called to SoC.
For example, with high-definition multimedia interface (HDMI, High Definition Multimedia Interface)
For, thh, thl, thsp tri- instructions are defined, high-frequency test, low-frequency test is respectively corresponded and stops three test items of test.
Step 702, CPU BOOT code is cut, removes unwanted part, retains the smallest starting code, IP is tested
Use-case code add, and in BOOT code test instruction and IP test case be mapped.
Step 703, the above preparation all after the completion of, need to confirm bare die BOOT need condition (for example, bare die BOOT
The state of the Pin and Pin that need to use), while corresponding port (Port), resolution chart are established in 93K test platform
(Pattern), timing (Timing), level (Level) file；
It should be noted that establish three ports (Port) in the present embodiment, be respectively pBOOT, pUART_Write,
pUART_Read；Wherein pBOOT contain BOOT needs Pin, pUART_Write only have UART transmitting terminal (UART_TXD) this
A Pin only has the receiving end UART (UART_RXD) this Pin to be used for outside for receiving external testing instruction, pUART_Read
Type information.In other embodiments, other Port, the foundation of Port described in the present embodiment can also be established as needed
It is merely illustrative reference.
Step 704, the test code (Test Method) that test is used is write.
In the present embodiment, it is all the burning for being sent in SoC by UART interface, while testing code that all tests, which instruct,
Write is also to be realized by UART interface, it is therefore desirable to realize the interaction between 93K and SoC with D2S simulation UART protocol.
Step 705, test set (Test Suit) and testing process (Test Flow) are established.
Step 706, IP test is carried out.
Step 707, programming EFUSE.
It should be noted that Test Method is the test code write with c++；Test Suite is Test
Method/timing/level/pattern is grouped together to test a certain index；Test flow is the collection of Test Suit
It closes, contains all test items.In the present embodiment, corresponding test item can be established for different IP according to demand, divided
Group establishes Test Flow, pays attention to the switching of relay and the selection of power supply power supply and corresponding Test Method, such as schemes
Shown in 8, high and low frequency test item is tested for HDMI and group divides exemplary diagram.Wherein: HDMI_High_Freq_
Relay_Switch/HDMI_Low_Freq_Relay_Switch is the switching for the relay state for needing to use when testing HDMI；
HDMI_High_Freq_d2s_uart_Write/HDMI_Low_Freq_d2s_uart_Wri te is that d2s simulates UART to SoC
Instruction is sent, the corresponding test case of HDMI test item is called to be initially configured register；Wait_HDMI_High_Freq/Wait_
HDMI_Low_Freq is to wait for a period of time, and configures register and waits for a period of time to output waveform needs are generated；HDMI_
High_Freq_Cap_9G/HDMI_Low_Freq_Cap_PS1600 is after waiting for a period of time with digital capture
Crawl output waveform is calculated, and the judgement of pass/fail is carried out to calculated result；HDMI_High_Freq_Stop/
HDMI_Low_Freq_Stop is off test, stops calling the configuration deposit of HDMI test case after completing to result judgement
Device completes the test to HDMI.
In a kind of implementation, in the programming information into EFUSE, need with Digital Capture crawl from UART
The information printed the characteristics of according to UART protocol, writes Test Method and extracts information and perform corresponding processing, judges
Whether programming is correct.For example, by Chip id information programming into EFUSE after pre-assigned register, then will be read by UART
The value for the register got prints, and 93K test platform grabs UART return value, extracts Chip id information and write-in
Whether value compares, correct come the Chip ID value for judging write-in with this.
As shown in figure 9, judging that the whether correct process of programming may include: when programming Chip ID into EFUSE
Step 901, Chip ID is obtained from server；
Step 902, Chip ID to SoC is sent by UART interface；
Step 903, EFUSE register is written into Chip ID；
Step 904, it sends and instructs to SoC, read the Chip ID stored in EFUSE register；
Step 905, SoC exports Chip ID by UART interface；
Step 906, the Chip ID that parsing UART interface returns；
Step 907, whether the Chip ID that UART interface returns is identical as the Chip ID of write-in EFUSE, gos to step
908 or step 909；
Step 908, test item programming corresponding to Chip ID is correct.
Step 909, test item programming corresponding to Chip ID fails.
The present embodiment provides a kind of IP test devices of SoC chip may include: as shown in Figure 10
Module 101 is obtained, for obtaining the test instruction come test platform by UART interface；
Test module 102 calls institute for loading the test code in embedded multi-media card EMMC by BOOT CPU
It states test and instructs corresponding IP test case and configuration register, complete IP test；
Wherein, the test code includes that IP test case and its corresponding test instruct.
The present embodiment provides a kind of system on chip SoC chips, comprising: IP module；It is stored with the memory of IP test program；
Processor is configured to execute operation of the IP test program to execute the above method.
In the present embodiment, " IP can be tested at Function Mode by configuration register " characteristic, SoC are utilized
It calls corresponding IP test case configuration register in EMMC to realize that the volume production of IP is tested by BOOT CPU, solves in Test
The problem of can not testing IP under Mode, improve test coverage.
The present embodiment also provides a kind of computer readable storage medium, and meter is stored on the computer readable storage medium
The step of calculation machine program, the computer program realizes the IP test method of above-mentioned SoC chip when being executed by processor.It is specific next
It says, the computer program realizes step 601~step 602 of the IP test method of the SoC chip when being executed by processor,
Other details can refer to the part of method above.
Those of ordinary skill in the art will appreciate that all or part of the steps in the above method can be instructed by program
Related hardware (such as processor) is completed, and described program can store in computer readable storage medium, as read-only memory,
Disk or CD etc..Optionally, one or more integrated circuits also can be used in all or part of the steps of above-described embodiment
It realizes.Correspondingly, each module/unit in above-described embodiment can take the form of hardware realization, such as pass through integrated circuit
It realizes its corresponding function, can also be realized in the form of software function module, such as be stored in and deposited by processor execution
Program/instruction in reservoir realizes its corresponding function.The application is not limited to the knot of the hardware and software of any particular form
It closes.
The advantages of basic principles and main features and the application of the application have been shown and described above.The application is not by upper
The limitation for stating embodiment, the above embodiments and description only describe the principles of the application, are not departing from the application
Under the premise of spirit and scope, the application be will also have various changes and improvements, these changes and improvements both fall within claimed
Within the scope of the application.
Claims (12)
1. a kind of IP test method of system on chip SoC chip characterized by comprising
SoC chip is obtained by universal asynchronous receiving-transmitting transmitter UART interface and is instructed come the test of test platform；
SoC chip loads the test code in embedded multi-media card EMMC by BOOT CPU, and the test is called to instruct phase
Corresponding IP test case and configuration register complete IP test；
Wherein, the test code includes that IP test case and its corresponding test instruct.
2. the test code programming method of system on chip SoC a kind of, comprising:
BOOT code is cut, the code of IP test case is added to the BOOT code, and will be pre- in the BOOT code
The test instruction first set is corresponding with the IP test case, obtains test code；
The test code is compiled, binary file is generated；
Using the resolution chart write in advance, Xmodem Protocol is simulated by D2S, the binary file is write into the test
The embedded multi-media card EMMC of platform, the resolution chart include predefined combinations information, and the combined information includes pre-
The timing information and level information of definition.
3. according to the method described in claim 2, it is characterized in that, the cutting BOOT code, by the code of IP test case
It is added to before the BOOT code, further includes:
It is pre-configured with the test instruction set for SoC chip IP test, the test instruction set includes at least one described test
Instruction.
4. according to the method described in claim 2, it is characterized in that,
The method also includes: it generates for the programming program by the binary file programming into the test platform；
It is described using the resolution chart write in advance, by D2S simulate Xmodem Protocol the binary file write into it is described
The EMMC of test platform, comprising: using the programming program and be based on the resolution chart, Xmodem Protocol is simulated by D2S
The binary file is write into the EMMC of the test platform.
5. method according to claim 2 or 4, which is characterized in that the method also includes:
Establish port based on UART protocol in test platform, define timing information and level information, based on the port, when
Sequence information and level information form the resolution chart.
6. according to the method described in claim 2, it is characterized in that, it is described by D2S simulate Xmodem Protocol by described two into
File processed writes into the EMMC of the test platform, comprising:
The binary file is stored in IRAM by universal asynchronous receiving-transmitting transmitter UART；
It sends order to SoC from the UART again to read out the binary file from IRAM, programming is specified into EMMC
Block.
7. the method according to claim 2 or 6, which is characterized in that described to simulate Xmodem Protocol for described two by D2S
Binary file writes into the EMMC of the test platform, comprising:
Image file is read using C++, by byte storage into vector v ector；
D2S simulation Xmodem Protocol reads the data in vector and is sent to UART_RXD, crawl UART_TXD return value judgement
Data send it is whether correct, when the UART_TXD return value is correct D2S send instruction will test the file programming of code to
EMMC。
8. according to method described in claim 2,5 or 6, which is characterized in that it is described Xmodem Protocol is simulated by D2S will be described
Binary file writes into the EMMC of the test platform, comprising:
Under xm instruction, Xmodem Protocol is selected to send data in IRAM；
Under go instruction, the second level BOOT started from UART is completed；
Under wm instruction, the data stored in the IRAM write-in EMMC is specified in block.
9. a kind of IP test device of system on chip SoC chip, comprising:
Module is obtained, for obtaining the test instruction come test platform by UART interface；
Test module calls the test for loading the test code in embedded multi-media card EMMC by BOOT CPU
Corresponding IP test case and configuration register are instructed, IP test is completed；
Wherein, the test code includes that IP test case and its corresponding test instruct.
10. the test code programming device of system on chip SoC a kind of, comprising:
The code of IP test case is added to the BOOT code, and described for cutting BOOT code by generation module
It is in BOOT code that preset test instruction is corresponding with the IP test case, obtain test code；
Collector generates binary file for compiling the test code；
Writing module, for simulating Xmodem Protocol by D2S and writing the binary file using the resolution chart write in advance
Into the embedded multi-media card EMMC of the test platform, the resolution chart includes predefined combinations information, the combination
Information includes predefined timing information and level information.
11. a kind of system on chip SoC chip characterized by comprising
IP module；
It is stored with the memory of IP test program；
Processor is configured to execute the operation that the IP test program requires 1 the method with perform claim.
12. the test code programming device of system on chip SoC a kind of characterized by comprising
It is stored with the memory of test code programming program；
Processor is configured to execute the behaviour that the test code programming program requires any one of 2 to 8 the methods with perform claim
Make.
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