CN109768102A - A kind of silicon/crystalline silicon heterogenous joint solar cell and preparation method thereof - Google Patents
A kind of silicon/crystalline silicon heterogenous joint solar cell and preparation method thereof Download PDFInfo
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- CN109768102A CN109768102A CN201811612890.6A CN201811612890A CN109768102A CN 109768102 A CN109768102 A CN 109768102A CN 201811612890 A CN201811612890 A CN 201811612890A CN 109768102 A CN109768102 A CN 109768102A
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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- Y02E10/547—Monocrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a kind of silicon/crystalline silicon heterogenous joint solar cell and preparation method thereof, battery structures are as follows: Ag/ITO/ZnTe/i-a-Si/n-c-Si/i-a-Si/CdSe/Ag；When preparation, surface clean is carried out to remove its surface contamination impurity to monocrystalline silicon piece；One layer of intrinsic amorphous silicon is grown in silicon wafer front and rear surfaces；On the amorphous silicon membrane of front side of silicon wafer, ZnTe film and ITO conductive film are grown；On the amorphous silicon membrane of silicon chip back side, CdSe film is grown；Growth front and back Ag electrode.The present invention proposes the p-type amorphous silicon (p-a-Si) and N-shaped amorphous silicon (n-a-Si) that utilize zinc telluridse (ZnTe) and cadmium selenide (CdSe) to be substituted in traditional amorphous silicon/crystalline silicon structure respectively, and the efficiency expectation of the heterojunction solar battery of ZnTe/a-Si/c-Si/a-Si/CdSe structure is highly improved.
Description
Technical field
The present invention relates to a kind of silicon/crystalline silicon heterogenous joint solar cell, with and preparation method thereof, belong to solar battery skill
Art field.
Background technique
The design based on the surface amorphous silicon (a-Si) thin film passivation crystalline silicon (c-Si) of Matsushita Corporation of Japan research and development is one
The absorbed layer of the typical crystal silicon bulk heterojunction solar cell structure of kind, battery uses N-shaped pulling of crystals silicon wafer, first in monocrystalline
Silicon front growth thickness is the intrinsic amorphous silicon layer of 10nm or so as surface passivation layer, the p-type amorphous of regrowth 10nm or so
Silicon layer, the two collectively form front hole transmission layer, then successively grow 10nm or so intrinsic amorphous silicon and n at the monocrystalline silicon back side
Type amorphous silicon layer forms the electron transfer layer at the back side, and the photoelectric conversion efficiency of current this structure battery has reached
26.3%.In order to further increase the efficiency of silicon/crystalline silicon heterogenous junction battery, only by improve and optimization amorphous silicon membrane and
With the quality of crystalline silicon contact interface, it has been found that the efficiency of battery is difficult have promotion by a relatively large margin.Therefore, people should be another
Path is warded off, the classical hetero-junction solar cell mentality of designing using amorphous silicon passivation surface of crystalline silicon is abandoned, it is non-to find a kind of substitution
The passivating material of polycrystal silicon film obtains the structure of more preferably crystal silicon bulk heterojunction battery.
The design of the silicon heterogenous battery structure of novel crystal needs to consider there are two key factor, first, substitution amorphous silicon
The passivating material of film should have well passivated effect to silicon crystal silicon, reduce interface state defects to the maximum extent.Second, this
The passivating material of kind substitution will have the reflection potential barrier of minority carrier at positive and negative two interfaces of crystalline silicon, in heterojunction boundary
Surface of crystalline silicon is formed about the minority carrier inversion layer of high concentration.Since there are energy between crystalline silicon and surface passivation material
Band bending and conduction band (or valence band) offset, the photo-generated carrier (electronics or hole) generated inside crystalline silicon is from the table of crystalline silicon
Face is reflected back, and then towards another apparent motion, is finally collected by corresponding external electrode.For a certain fixed hetero-junctions
For interface, the conduction band offset at interface is bigger, and minority carrier (electronics) is bigger from interface potential barrier reflection probability, but if this
When interface valence band offset be consequently increased, then increased potential barrier can also prevent majority carrier (hole) logical from this interface
It crosses.So for the same interface potential barrier of heterogenous junction or being that conduction band offset is big, valence band offset is few or being valence band offset
Greatly, conduction band offset is few, and such minority carrier reflection probability is big, and the probability that majority carrier passes through is also big, in this way can be substantially
Increase the probability that photo-generated carrier is collected by electrode both ends, to increase the efficiency of battery.
Summary of the invention
The object of the present invention is to provide a kind of silicon/crystalline silicon heterogenous joint solar cell, with and preparation method thereof.
To realize that first goal of the invention, used technical solution are such that a kind of silicon/crystalline silicon heterogenous joint solar
Battery, it is characterised in that there is following battery structure: Ag/ITO/ZnTe/i-a-Si/n-c-Si/i-a-Si/CdSe/Ag,
Middle Ag is metallic silver, and ITO is the indium oxide transparent conductive film for mixing tin, and ZnTe is p-type semiconductor, and i-a-Si is intrinsic amorphous
Silicon, n-c-Si are n-type single-crystal silicon substrate, and CdSe is n-type semiconductor.
To realize that second goal of the invention, used technical solution are such that a kind of silicon/crystalline silicon heterogenous joint solar
The preparation method of battery, which comprises the following steps:
1) surface clean is carried out to remove its surface contamination impurity to monocrystalline silicon piece；
2) intrinsic amorphous silicon that a layer thickness is 10~20nm is grown in silicon wafer front and rear surfaces；
3) on the amorphous silicon membrane of front side of silicon wafer, growth thickness is the ZnTe film of 10~20nm, then regrowth
With a thickness of the ITO conductive film of 80nm；
4) on the amorphous silicon membrane of silicon chip back side, growth thickness is the CdSe film of 10~20nm；
5) growth front and back Ag electrode.
The present invention proposes to substitute traditional amorphous silicon/crystalline silicon structure respectively using zinc telluridse (ZnTe) and cadmium selenide (CdSe)
In p-type amorphous silicon (p-a-Si) and N-shaped amorphous silicon (n-a-Si), since ZnTe is a kind of p-type semiconductor, forbidden bandwidth is
2.26eV, electron affinity energy 3.53eV, and zinc selenide n-type semiconductor, forbidden bandwidth 1.75eV, electron affinity energy are
4.56eV, therefore the conduction band offset for increasing p-type amorphous silicon is big, the valence band offset for reducing N-shaped amorphous silicon is few.With traditional amorphous silicon/
Silicon/crystalline silicon heterogenous junction battery is compared, the efficiency expectation of the heterojunction solar battery of ZnTe/a-Si/c-Si/a-Si/CdSe structure
It is highly improved.According to theoretical calculation, the efficiency of this novel battery can be more than 30%.
Detailed description of the invention
It is described in further detail below in conjunction with attached drawing and embodiments of the present invention
Fig. 1 is battery structure schematic diagram of the invention.
In the figure, it is marked as monocrystalline substrate 1, intrinsic amorphous silicon layer 2, ZnTe film 3, CdSe film 4, ito thin film 5, Ag
Electrode 6.
Specific embodiment
Solar battery described in the present embodiment, battery structure is from top to bottom successively are as follows:
Ag electrode 6, ito thin film 5, ZnTe film 3, intrinsic amorphous silicon layer 2, n-type single-crystal silicon substrate 1, intrinsic amorphous silicon layer
2, CdSe film 4, Ag electrode 6, wherein Ag is metallic silver, and ITO is the indium oxide transparent conductive film for mixing tin, and ZnTe is p-type half
Conductor, CdSe are n-type semiconductor.
The preparation method of solar battery the following steps are included:
(1) cleaning of silicon wafer
Monocrystalline substrate 1 is the pulling of crystals silicon wafer of N-shaped twin polishing, with a thickness of 180~300 μm, resistivity is 0.1~
2 Ω cm, minority carrier life time are greater than 200 μ s.First successively with organic matter, the H of acetone removal silicon chip surface2SiO4And H2O2Mixing
Solution (3:1) further removes the hydrofluoric acid solution removal surface oxide layer of surface organic matter, 1%.Then, using RCA standard
(the wet chemical cleans method being commonly used, the nineteen sixty-five New Jersey Princeton laboratory RCA mention cleaning method
Surface clean is carried out to silicon wafer out), removes surface contamination impurity.Next, the hydrofluoric acid solution with 1% removes surface oxidation
Layer, H2SiO4And H2O2Mixed solution (3:1) removes organic matter, forms surface oxidation protective layer.
(2) intrinsic amorphous silicon layer 2 is grown in silicon wafer front and rear surfaces
When using plasma enhanced chemical vapor deposition (PECVD) method deposition intrinsic amorphous silicon membrane, plasma
A large amount of hydrogen atoms of middle generation have excellent passivation effect.Silicon wafer after over cleaning uses before being put into vacuum chamber
1% hydrofluoric acid solution removes surface oxide layer.The radio frequency of PECVD is 13.56MHz, the base vacuum of deposition chamber better than 6 ×
10-4Pa, radio frequency power density are 0.1~0.3W/cm2, using electronic-grade silane and hydrogen as growth source, the flow of silane and hydrogen
Than for 1:8~12, operating air pressure is 20~60Pa, growth temperature is 150~200 DEG C, in the intrinsic non-of silicon wafer front surface growth
Polycrystal silicon film is with a thickness of 10~20nm.
(3) ZnTe film 3 is grown in front side of silicon wafer
Using Vacuum sublimation, ZnTe film is grown on the intrinsic amorphous silicon surface of front side of silicon wafer.Purity is greater than
99.999% zinc and tellurium carries out grinding and dusting, is mixed by the molar ratio of 1:1, then after being fully ground, is put
In the evaporation source (tungsten boat) for entering vacuum chamber.The vacuum degree of thermal evaporation cavity is better than 1 × 10-4Pa, the reverse side mask plate lid of silicon wafer
Firmly, and with tinfoil paper it wraps up.Underlayer temperature is room temperature, opens evaporation power supply, thin by adjusting heated current and evaporation time control
The growth thickness of film growth thickness, film is monitored by quartz oscillator, and ZnTe film 3 is with a thickness of 10~20nm.
(4) CdSe film 4 is grown in silicon wafer reverse side
Equally with step (3), method is steamed using Vacuum Heat, grows CdSe film on the intrinsic amorphous silicon surface of silicon wafer reverse side.
Evaporating raw material is the CdSe powder that purity is greater than 99.999%, is put into the evaporation source (tungsten boat) of vacuum chamber.CdSe film 4 is thick
Degree is 10~20nm.
(5) ito thin film 5 is grown on ZnTe film 3
Sputtering target material is ITO (purity 99.999%), and the background vacuum of sputter chamber is better than 8 × 10-4Pa, working gas
For argon gas (99.999%), operating air pressure is 0.5~2Pa, and sputtering power is 30~70W, and underlayer temperature is 150 DEG C.In order to obtain
High conductivity ito thin film, be passed through high purity oxygen gas (99.999%) in sputtering chamber, the flow-rate ratio of argon gas and oxygen is 40~
80:1.After pre-sputtering, the pollution of target material surface is removed, baffle is then opened, starts to sputter ito thin film, the growth of film
Thickness is monitored by quartz oscillator, and 5 thickness of ito thin film is by for 80nm.
(6) prepared by Ag electrode 6
The silver-colored front electrode for being sputtered one layer of fourchette shape on ito thin film using mask plate, is sputtered on CdSe film
One layer of silver-colored back electrode, before and 6 thickness of back side Ag electrode be all 500nm.
(7) battery performance test
In standard test condition (AM1.5,100mW/cm2, 25 DEG C) under, Ag/ITO/ZnTe/i-a-Si/n-c-Si/i-a-
The highest transfer efficiency of Si/CdSe/Ag novel crystal silion cell is 19.5%.The hetero-junction solar cell efficiency prepared at present is still not
It is very high, is because each section growthing process parameter of battery need to be advanced optimized.
Claims (2)
1. a kind of silicon/crystalline silicon heterogenous joint solar cell, it is characterised in that: have following battery structure: Ag/ITO/ZnTe/i-
A-Si/n-c-Si/i-a-Si/CdSe/Ag, wherein Ag is metallic silver, and ITO is the indium oxide transparent conductive film for mixing tin, ZnTe
For p-type semiconductor, i-a-Si is intrinsic amorphous silicon, and n-c-Si is n-type single-crystal silicon substrate, and CdSe is n-type semiconductor.
2. a kind of preparation method of solar battery described in claims, it is characterised in that: the following steps are included:
1) surface clean is carried out to remove its surface contamination impurity to monocrystalline silicon piece；
2) intrinsic amorphous silicon that a layer thickness is 10~20nm is grown in silicon wafer front and rear surfaces；
3) on the amorphous silicon membrane of front side of silicon wafer, growth thickness is the ZnTe film of 10~20nm, then regrowth thickness
For the ITO conductive film of 80nm；
4) on the amorphous silicon membrane of silicon chip back side, growth thickness is the CdSe film of 10~20nm；
5) growth front and back Ag electrode.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114000108A (en) * | 2021-10-30 | 2022-02-01 | 平顶山学院 | Preparation method for embedding CdSe regulation and control layer in ZnSe/Si heterojunction interface |
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| CN103247720A (en) * | 2013-05-10 | 2013-08-14 | 苏州阿特斯阳光电力科技有限公司 | Method for preparing crystalline silicon heterojunction solar cells |
| CN103688366A (en) * | 2011-04-11 | 2014-03-26 | 国家科学研究中心 | Semiconductor heterostructure and photovoltaic cell including such a heterostructure |
| US20150048300A1 (en) * | 2008-04-18 | 2015-02-19 | Invisage Technologies, Inc. | Materials, fabrication equipment, and methods for stable, sensitive photodetectors and image sensors made therefrom |
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| US20150048300A1 (en) * | 2008-04-18 | 2015-02-19 | Invisage Technologies, Inc. | Materials, fabrication equipment, and methods for stable, sensitive photodetectors and image sensors made therefrom |
| CN102013331A (en) * | 2009-09-04 | 2011-04-13 | 北京大学 | Method for preparing photo-electrode |
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| CN103688366A (en) * | 2011-04-11 | 2014-03-26 | 国家科学研究中心 | Semiconductor heterostructure and photovoltaic cell including such a heterostructure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114000108A (en) * | 2021-10-30 | 2022-02-01 | 平顶山学院 | Preparation method for embedding CdSe regulation and control layer in ZnSe/Si heterojunction interface |
| CN114000108B (en) * | 2021-10-30 | 2023-10-17 | 平顶山学院 | Preparation method for embedding CdSe regulating layer at ZnSe/Si heterojunction interface |
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Application publication date: 20190517 |