CN109755261A - A kind of array substrate and preparation method thereof - Google Patents
A kind of array substrate and preparation method thereof Download PDFInfo
- Publication number
- CN109755261A CN109755261A CN201811602885.7A CN201811602885A CN109755261A CN 109755261 A CN109755261 A CN 109755261A CN 201811602885 A CN201811602885 A CN 201811602885A CN 109755261 A CN109755261 A CN 109755261A
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- layer
- array substrate
- active layer
- electrode
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- 239000000758 substrate Substances 0.000 title claims abstract description 78
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 238000009413 insulation Methods 0.000 claims abstract description 19
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 18
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 15
- 229910052733 gallium Inorganic materials 0.000 claims description 15
- 229910052738 indium Inorganic materials 0.000 claims description 15
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 15
- 238000002161 passivation Methods 0.000 claims description 15
- 239000011787 zinc oxide Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 230000003287 optical effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 13
- 239000010408 film Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000583 Nd alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 229910007541 Zn O Inorganic materials 0.000 description 1
- VVTQWTOTJWCYQT-UHFFFAOYSA-N alumane;neodymium Chemical compound [AlH3].[Nd] VVTQWTOTJWCYQT-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Present applicant proposes a kind of array substrates and preparation method thereof.The array substrate includes substrate.The active layer being disposed on the substrate.Gate insulation layer on active layer is set.Metal layer on gate insulation layer is set.Wherein, the active layer includes the source electrode and drain electrode at both ends, and the channel region between the source electrode and drain electrode.The application to can reduce twice optical cover process on the basis of saving a layer insulating, effectively simplifies the manufacture craft of array substrate, reduces the cost of product by using at the both ends of active layer directly as source electrode and drain electrode.
Description
Technical field
This application involves display field, in particular to a kind of array substrate and preparation method thereof.
Background technique
In recent years, the thin film transistor (TFT) based on metal oxide is because its mobility is high, translucency is good, membrane structure is steady
Calmly, the advantages that preparation temperature is low and at low cost is more and more paid attention to.Especially with indium gallium zinc oxide (In-Ga-
Zn-O, IGZO) be representative metal oxide TFT, it is higher that compatibility is made with current a-Si TFT, thus show in large scale
It is widely used in the production of panel.
The method for preparing thin film transistor (TFT) in the prior art includes four light shield steps, is respectively as follows:
Active layer pattern is made on substrate using the first light shield；
Use second the first insulating layer pattern of light shield manufacture；
Use third light shield manufacture metal layer pattern；
Use the 4th light shield manufacture second insulating layer pattern；
Use the drain electrode of the 5th light shield manufacture and source electrode pattern.
Therefore, how to save the cost of light shield and simplify the project that technique is persistently studied for industry.
Summary of the invention
The application provides a kind of array substrate and preparation method thereof, is used with solving array substrate processing procedure using light shield technique
The problem of number is more, production technology complexity and higher cost.
To solve the above problems, technical solution provided by the present application is as follows:
According to the one aspect of the application, a kind of array substrate is provided, comprising:
Substrate；
Active layer on the substrate is set；
Gate insulation layer on the active layer is set；
Metal layer on the gate insulation layer is set；
Wherein, the active layer includes the source electrode and drain electrode at both ends, and between the source electrode and the drain electrode
Channel region.
According to one embodiment of the application, the making material of the active layer includes its in polysilicon and indium gallium zinc oxide
Middle one.
According to one embodiment of the application, the material for preparing of the active layer includes indium gallium zinc oxide, and the active layer is also
Including pixel electrode, the pixel electrode is located at side of the channel region far from the source electrode.
According to one embodiment of the application, position and pattern phase of the position and pattern of the gate insulation layer with the channel region
It is corresponding.
According to one embodiment of the application, the array substrate further include:
Side on the metal layer is set and covers the passivation layer of the active layer；
Transparent electrode on the passivation layer is set.
According to another invention of the application, additionally provide a kind of production method of array substrate, comprising:
Step S10, a substrate is provided；
Step S20, patterned channel layer is formed by the first light shield technique on the substrate；
Step S30, on the substrate by the second light shield technique formed the patterned gate insulation layer that is stacked and
Patterned metal layer, the gate insulation layer are contacted with the channel layer；
Step S40, using the metal layer as light shield, it is active to be formed that ion implanting is carried out to the both ends of the channel layer
Layer, the active layer include the channel region of centre and the source electrode and drain electrode for being located at the channel region both ends.
According to one embodiment of the application, the making material of the active layer includes its in polysilicon and indium gallium zinc oxide
Middle one.
According to one embodiment of the application, the material for preparing of the active layer includes indium gallium zinc oxide, and the active layer is also
Including pixel electrode, the pixel electrode is located at side of the channel region far from the source electrode, the pixel electrode, the source
Pole is formed in ion implanting with the drain electrode with along with.
According to one embodiment of the application, ion implanting is carried out to the channel layer using plasma-based technique.
According to one embodiment of the application, the production method of the array substrate further include:
Step S50, non-metallic layer is formed on the metal layer, and the non-metallic layer is carried out using third light shield technique
Patterning is to form passivation layer；
Step S60, transparent electrode is formed on the passivation layer.
The utility model has the advantages that the application by by the both ends of active layer directly as source electrode and drain electrode use, thus saving one
On the basis of layer insulating, twice optical cover process can be reduced, effectively simplifies the manufacture craft of array substrate, reduces production
The cost of product.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only some of invention
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is the structural schematic diagram for the array substrate that the application first embodiment provides；
Fig. 2 is the structural schematic diagram for the array substrate that the application second embodiment provides；
Fig. 3 is the structural schematic diagram for the array substrate that the application 3rd embodiment provides；
Fig. 4 is the structural schematic diagram for the array substrate that the application fourth embodiment provides；
Fig. 5 is the flow diagram of the production method for the array substrate that the 5th embodiment of the application provides；
Fig. 6 a-6c is the structural schematic diagram of the production method for the array substrate that the 5th embodiment of the application provides；
Fig. 7 is the structural schematic diagram of array substrate in the production method for the array substrate that the application sixth embodiment provides.
Specific embodiment
The explanation of following embodiment is referred to the additional illustration, the particular implementation that can be used to implement to illustrate the application
Example.The direction term that the application is previously mentioned, such as [on], [under], [preceding], [rear], [left side], [right side], [interior], [outer], [side]
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand the application, rather than to
Limit the application.The similar unit of structure is with being given the same reference numerals in the figure.
The application provides a kind of array substrate and preparation method thereof, to solve existing array substrate processing procedure using light shield technique
The problem of access times are more, production technology complexity and higher cost.
Referring to Fig. 1, Fig. 1 is the structural schematic diagram for the array substrate that the application first embodiment provides.
This application provides a kind of array substrates 100, including substrate 11, active layer 12, gate insulation layer 13, metal layer 14.
In one embodiment, the substrate 11 is the one of them in flexible base board and rigid substrates.
In one embodiment, the material for preparing of the flexible base board is polyimides.
In one embodiment, the material for preparing of the rigid substrates is glass substrate.
In one embodiment, the material for preparing of the active layer 12 includes but are not limited to polysilicon and the oxidation of indium gallium zinc
One of them in object (IGZO).The indium gallium zinc oxide is transparent material.
The active layer 12 includes source electrode 121 and the drain electrode 122 at both ends, and is located at the source electrode 121 and the drain electrode
Channel region 123 between 122.
Relative to existing array substrate, source electrode 121 and drain electrode 122 in the application are set up directly on channel region 123
The problem of two sides increase so as to avoid film layer number caused by source electrode 121, drain electrode 122 is separately provided, and light shield technique increases,
And then save the preparation cost of array substrate 100.
Referring to Fig. 2, Fig. 2 is the structural schematic diagram for the array substrate that the application second embodiment provides.
In one embodiment, the material for preparing of the array substrate 100 includes indium gallium zinc oxide.Due to indium gallium zinc oxygen
Compound is transparent material, therefore the pixel electrode 124 of array substrate 100 also can be with channel region 123, source electrode 121 and drain electrode 122
Same layer setting.
The active layer 12 further includes pixel electrode 124, and the pixel electrode 124 is located at the channel region 123 far from institute
The side of source electrode 121 is stated, i.e., the described source electrode 121 is located at 123 side of channel region, the drain electrode 122 and the pixel electrode
124 other sides for being located at the channel region 123 simplify array substrate so as to avoid being prepared separately for pixel electrode 124
100 film layer structure.
In one embodiment, the material for preparing of the gate insulation layer 13 includes at least one in silicon nitride and silica
Person, the gate insulation layer 13 is for protecting the metal layer 14.
In one embodiment, the position and pattern of the position of the gate insulation layer 13 and pattern and the channel region 123
It is corresponding.
In one embodiment, the metal layer 14 is gate metal layer.
In one embodiment, the material for preparing of the metal layer 14 includes aluminium, copper, the one of them in aluminium neodymium alloy.
Referring to Fig. 3, Fig. 3 is the structural schematic diagram for the array substrate that the application 3rd embodiment provides.
Referring to Fig. 4, Fig. 4 is the structural schematic diagram for the array substrate that the application fourth embodiment provides.
Whether the difference of the application 3rd embodiment and fourth embodiment is the pixel electrode 124 in array substrate 100
It is arranged with source electrode 121, drain electrode 122 and 123 same layer of channel region, concrete application can be configured according to the actual situation, not do here
It limits.
In one embodiment, the array substrate 100 further includes 15 He of passivation layer being arranged on the metal layer 14
Transparent electrode 16；
Wherein, the passivation layer 15 is being arranged above the metal layer 14 and is covering the active layer 12；
The transparent electrode 16 is arranged on the passivation layer 15.
Referring to Fig. 5, Fig. 5 is the flow diagram of the production method for the array substrate that the 5th embodiment of the application provides.
According to further aspect of the application, a kind of production method of array substrate is additionally provided, is included the following steps.
Fig. 6 a is please referred to, step S10, a kind of substrate 11 is provided.
In one embodiment, the substrate 11 is the one of them in flexible base board and rigid substrates.
In one embodiment, the material for preparing of the flexible base board is polyimides.
In one embodiment, the material for preparing of the rigid substrates is glass substrate.
Step S20, patterned channel layer 17 is formed by the first light shield technique on the substrate.
The channel layer 17 forms active layer 12 by ion implanting, and the material for preparing of the channel layer 17 includes but not only
The one of them being limited in polysilicon and indium gallium zinc oxide.
Fig. 6 b is please referred to, step S30, is stacked on the substrate by the formation of the second light shield technique patterned
Gate insulation layer 13 and patterned metal layer 14, the gate insulation layer 13 are contacted with channel layer 17.
The step S30 is specifically included: being sequentially depositing nonmetallic film layer and metallic diaphragm on the channel layer 17, is used
Second light shield technique patterns the nonmetallic film layer and the metallic diaphragm, and then forms patterned 13 He of gate insulation layer
Patterned metal layer 14.
Please refer to Fig. 6 c, step S40, using the metal layer 14 as light shield, to the both ends of the channel layer 17 carry out from
To form active layer 12, the active layer 12 includes intermediate channel region 123 and is located at the channel region 123 for son injection
The source electrode 121 at both ends and drain electrode 122.
Since 123 position of channel region is blocked by the metal layer 14, the channel region 123 is undoped
Area is semiconductor；The source electrode 121 at both ends and drain electrode 122 have ion doping, are conductor.
Referring to Fig. 7, being the structure of array substrate in the production method for the array substrate that the application sixth embodiment provides
Schematic diagram.
In one embodiment, the material for preparing of the active layer 12 includes indium gallium zinc oxide, and the active layer 12 also wraps
Pixel electrode 124 is included, the pixel electrode 124 is located at side of the channel region 123 far from the source electrode 121, the pixel
Electrode 124, the source electrode 121 and the drain electrode 122 are formed in ion implanting with along with, so as to avoid pixel electrode 124
Be prepared separately, simplify the film layer structure of array substrate 100.
In one embodiment, ion implanting is carried out to the channel layer 17 using plasma-based technique.
In one embodiment, the production method of the array substrate 100 further include:
Step S50, form non-metallic layer on the metal layer 14, using third light shield technique to the non-metallic layer into
Row patterning is to form passivation layer 15.
Step S60, transparent electrode 16 is formed on the passivation layer 15.
In one embodiment, the step S60 is specifically included: on the passivation layer 15 16 area of coverage of transparent electrode with
Outer region is coated with photoresist layer, and transparent electrode 16 is deposited on the passivation layer 15, removes the photoresist layer, forms transparent electrode
16。
The utility model has the advantages that the application by by the both ends of active layer directly as source electrode and drain electrode use, thus saving one
On the basis of layer insulating, twice optical cover process can be reduced, effectively simplifies the manufacture craft of array substrate, reduces production
The cost of product.
Although above preferred embodiment is not to limit in conclusion the application is disclosed above with preferred embodiment
The application processed, those skilled in the art are not departing from spirit and scope, can make various changes and profit
Decorations, therefore the protection scope of the application subjects to the scope of the claims.
Claims (10)
1. a kind of array substrate characterized by comprising
Substrate；
Active layer on the substrate is set；
Gate insulation layer on the active layer is set；
Metal layer on the gate insulation layer is set；
Wherein, the active layer includes the source electrode and drain electrode at both ends, and the channel between the source electrode and the drain electrode
Area.
2. array substrate according to claim 1, which is characterized in that the making material of the active layer include polysilicon and
One of them in indium gallium zinc oxide.
3. array substrate according to claim 1, which is characterized in that the material for preparing of the active layer includes indium gallium zinc oxygen
Compound, the active layer further include pixel electrode, and the pixel electrode is located at side of the channel region far from the source electrode.
4. array substrate according to claim 1, which is characterized in that the position of the gate insulation layer and pattern and the ditch
The position in road area and pattern are corresponding.
5. array substrate according to claim 1, which is characterized in that the array substrate further include:
Side on the metal layer is set and covers the passivation layer of the active layer；
Transparent electrode on the passivation layer is set.
6. a kind of production method of array substrate characterized by comprising
Step S10, a substrate is provided；
Step S20, patterned channel layer is formed by the first light shield technique on the substrate；
Step S30, the patterned gate insulation layer and figure that are stacked are formed by the second light shield technique on the channel layer
The metal layer of case, the gate insulation layer are contacted with the channel layer；
Step S40, using the metal layer as light shield, ion implanting is carried out to form active layer to the both ends of the channel layer,
The active layer includes the channel region of centre and the source electrode and drain electrode for being located at the channel region both ends.
7. the production method of array substrate according to claim 6, which is characterized in that the making material packet of the active layer
Include the one of them in polysilicon and indium gallium zinc oxide.
8. the production method of array substrate according to claim 6, which is characterized in that the active layer prepares material packet
Indium gallium zinc oxide is included, the active layer further includes pixel electrode, and the pixel electrode is located at the channel region far from the source
The side of pole, the pixel electrode, the source electrode are formed in ion implanting with the drain electrode with along with.
9. the production method of array substrate according to claim 6, which is characterized in that using plasma-based technique to the channel
Layer carries out ion implanting.
10. the production method of array substrate according to claim 6, which is characterized in that the production side of the array substrate
Method further include:
Step S50, non-metallic layer is formed on the metal layer, and pattern is carried out to the non-metallic layer using third light shield technique
Change to form passivation layer；
Step S60, transparent electrode is formed on the passivation layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811602885.7A CN109755261A (en) | 2018-12-26 | 2018-12-26 | A kind of array substrate and preparation method thereof |
| PCT/CN2019/076232 WO2020133672A1 (en) | 2018-12-26 | 2019-02-27 | Array substrate and manufacturing method therefor and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811602885.7A CN109755261A (en) | 2018-12-26 | 2018-12-26 | A kind of array substrate and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109755261A true CN109755261A (en) | 2019-05-14 |
Family
ID=66404142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811602885.7A Pending CN109755261A (en) | 2018-12-26 | 2018-12-26 | A kind of array substrate and preparation method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109755261A (en) |
| WO (1) | WO2020133672A1 (en) |
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| CN101090125A (en) * | 2006-06-12 | 2007-12-19 | 三菱电机株式会社 | Active matrix display |
| CN102237411A (en) * | 2010-05-05 | 2011-11-09 | 元太科技工业股份有限公司 | Oxide thin film transistor and manufacturing method thereof |
| CN102651403A (en) * | 2012-04-16 | 2012-08-29 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and manufacturing method of array substrate and display panel |
| CN103018974A (en) * | 2012-11-30 | 2013-04-03 | 京东方科技集团股份有限公司 | Liquid crystal display device, polysilicon array substrate and manufacturing method |
| CN103021942A (en) * | 2012-12-14 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, display device |
| CN103715094A (en) * | 2013-12-27 | 2014-04-09 | 京东方科技集团股份有限公司 | Thin film thyristor and manufacturing method thereof, array substrate and manufacturing method thereof and display device |
| CN104681627A (en) * | 2015-03-10 | 2015-06-03 | 京东方科技集团股份有限公司 | Array substrate, thin-film transistor and manufacturing methods thereof as well as display device |
-
2018
- 2018-12-26 CN CN201811602885.7A patent/CN109755261A/en active Pending
-
2019
- 2019-02-27 WO PCT/CN2019/076232 patent/WO2020133672A1/en active Application Filing
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050134754A1 (en) * | 2003-12-22 | 2005-06-23 | Lg.Philips Lcd Co., Ltd. | Method of fabricating liquid crystal display device |
| CN101090125A (en) * | 2006-06-12 | 2007-12-19 | 三菱电机株式会社 | Active matrix display |
| CN102237411A (en) * | 2010-05-05 | 2011-11-09 | 元太科技工业股份有限公司 | Oxide thin film transistor and manufacturing method thereof |
| CN102651403A (en) * | 2012-04-16 | 2012-08-29 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and manufacturing method of array substrate and display panel |
| CN103018974A (en) * | 2012-11-30 | 2013-04-03 | 京东方科技集团股份有限公司 | Liquid crystal display device, polysilicon array substrate and manufacturing method |
| CN103021942A (en) * | 2012-12-14 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, display device |
| CN103715094A (en) * | 2013-12-27 | 2014-04-09 | 京东方科技集团股份有限公司 | Thin film thyristor and manufacturing method thereof, array substrate and manufacturing method thereof and display device |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2020133672A1 (en) | 2020-07-02 |
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Application publication date: 20190514 |