CN104505372A - Manufacturing method of metal oxide thin film transistor array substrate - Google Patents
Manufacturing method of metal oxide thin film transistor array substrate Download PDFInfo
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- CN104505372A CN104505372A CN201410784257.0A CN201410784257A CN104505372A CN 104505372 A CN104505372 A CN 104505372A CN 201410784257 A CN201410784257 A CN 201410784257A CN 104505372 A CN104505372 A CN 104505372A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Abstract
The invention relates to a manufacturing method of a metal oxide thin film transistor array substrate. The manufacturing method comprises the following steps of manufacturing and forming a grid on the substrate; manufacturing and forming a gate insulation layer on the grid; manufacturing and forming a semiconductor layer, a pixel electrode layer, a source electrode, a drain electrode and a channel protecting layer on the gate insulation layer, wherein the semiconductor layer and the pixel electrode layer are simultaneously manufactured and formed by transparent metal-oxide semiconductor film layers in the same layer through one-time patterning, and the channel protecting layer is covered on the semiconductor layer; carrying out ion implantation on the pixel electrode layer on the premise of covering and protecting the semiconductor layer by the channel protecting layer, and converting the pixel electrode layer from a transparent semiconductor to a transparent conductor. The semiconductor layer and the pixel electrode layer adopt metal-oxide semiconductor materials so as to be manufactured and formed simultaneously in the same layer through one-time patterning by a photomask, so that a photomask manufacturing process can be omitted, the usage quantity of photomasks is reduced, the manufacturing cost is reduced, and the production efficiency is improved.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of manufacture method of metal oxide thin-film transistor array base palte.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor-Liquid Crystal Display, TFT-LCD) have that image quality is good, volume is little, lightweight, low driving voltage, low-power consumption, the advantage that radiationless and manufacturing cost is relatively low, occupy an leading position in flat display field at present.Early stage most TFT-LCD adopts TN (TwistedNematic, twisted nematic) pattern, in the liquid crystal display of TN pattern, for driving the pixel electrode of liquid crystal deflecting element (pixel electrode) and public electrode (common electrode) to be respectively formed at upper and lower two substrates, its angular field of view is smaller.
Along with the development of technology, adopt the liquid crystal display of wide viewing angle Technical Architecture owing to having the multiple advantage such as larger visible angle and better color representation, start the concern being subject to consumer.At present, the technology that can realize wide viewing angle has FFS (Fringe-field-Switch, fringe field switch) pattern etc., in the liquid crystal display of FFS mode, pixel electrode and public electrode for driving liquid crystal deflecting element are formed in same substrate such as array base palte.
Amorphous silicon (a-Si) and polysilicon (p-Si) are the semi-conducting materials of current TFT main flow, and wherein amorphous silicon is most widely used, but amorphous silicon has the problems such as electron mobility is low, light durability is poor.Although it is a lot of that polysilicon exceeds amorphous silicon in electron mobility is low, there is the problems such as complex structure, leakage current is large, film quality homogeneity is poor.Along with the fast development of Display Technique, propose more and more higher requirement to the performance of TFT, amorphous silicon and polysilicon can not meet these requirements completely.
In addition, pixel electrode is generally made up of transparent ITO (Indium Tin Oxide, tin indium oxide) material.When making semiconductor layer and the pixel electrode of TFT, need to adopt twice optical cover process, to make semiconductor layer and the pixel electrode of TFT respectively, cause needing more light shield (mask) usage quantity and more complicated manufacture craft, make cost of manufacture increase, reduce production efficiency.
Summary of the invention
The object of the invention is the manufacture method providing a kind of metal oxide thin-film transistor array base palte, this array base palte uses metal oxide semiconductor material as the semiconductor layer of TFT, while lifting display performance, decrease the usage quantity of light shield when making array base palte, reduce cost of manufacture, improve production efficiency.
The embodiment of the present invention provides a kind of manufacture method of metal oxide thin-film transistor array base palte, and this manufacture method comprises:
Underlay substrate makes and forms grid;
Make on the gate and form gate insulator;
This gate insulator makes and forms semiconductor layer, pixel electrode layer, source electrode, drain electrode and channel protective layer, wherein this semiconductor layer and this pixel electrode layer are made through a patterning within the same layer by transparent metal-oxide semiconductor (MOS) rete simultaneously and are formed, and this channel protective layer covers on this semiconductor layer; And
At this semiconductor layer by under the prerequisite of this channel protective layer covering protection, ion implantation is carried out to this pixel electrode layer, make this pixel electrode layer change transparent conductor into by transparent semiconductor.
Further, the mode of carrying out ion implantation to this pixel electrode layer is carry out independent plasma treatment to this pixel electrode layer.
Further, independent plasma treatment is carried out to this pixel electrode layer and comprises: in PECVD device, carry out plasma treatment with H ion or this pixel electrode layer of Ar ion pair.
Further, this manufacture method also comprises further: in this channel protective layer, make formation second protective layer, and on this second protective layer, make formation common electrode layer.
Further, the material selection silicon nitride of this second protective layer, carries out the mode of ion implantation for incidentally completing when making this second protective layer to this pixel electrode layer.
Further; on this gate insulator make formed semiconductor layer, pixel electrode layer, source electrode, drain electrode and channel protective layer time; first make on this gate insulator and form this source electrode and this drain electrode; and then make this semiconductor layer of formation and this pixel electrode layer, make again afterwards and form this channel protective layer.
Further; on this gate insulator make formed semiconductor layer, pixel electrode layer, source electrode, drain electrode and channel protective layer time; first make on this gate insulator and form this semiconductor layer and this pixel electrode layer; and then make this source electrode of formation and this drain electrode, make again afterwards and form this channel protective layer.
Further; on this gate insulator make formed semiconductor layer, pixel electrode layer, source electrode, drain electrode and channel protective layer time; first make on this gate insulator and form this semiconductor layer and this pixel electrode layer; and then make this channel protective layer of formation, make again afterwards and form this source electrode and this drain electrode.
Further, the material of this metal-oxide semiconductor (MOS) rete is IGZO or ITZO.
The manufacture method that the embodiment of the present invention provides, be applicable to making metal oxide thin-film transistor array base palte, the semiconductor layer of its thin-film transistor adopts metal oxide semiconductor material, possess that electron mobility is high, light durability good, photopermeability is high, aperture opening ratio high, the performance of display can be promoted; And, because semiconductor layer and pixel electrode layer adopt metal oxide semiconductor material, and make formation through a patterning within the same layer by a light shield simultaneously, namely in an optical cover process, define semiconducting channel region and pixel electrode area simultaneously, and then utilize ion implantation technology to make pixel electrode layer change transparent conductor into by transparent semiconductor, using the pixel electrode as pixel region.And in prior art, semiconductor layer and pixel electrode layer need twice independently optical cover process make respectively, the present invention can save one optical cover process compared to existing technology, decreases the usage quantity of light shield, reduces cost of manufacture, improves production efficiency.
Accompanying drawing explanation
Fig. 1 is the flow chart of the manufacture method of metal oxide thin-film transistor array base palte in the embodiment of the present invention.
Fig. 2 is the partial cutaway schematic of the metal oxide thin-film transistor array base palte making formation in first embodiment of the invention.
Fig. 3 is the partial cutaway schematic of the metal oxide thin-film transistor array base palte making formation in second embodiment of the invention.
Fig. 4 is the partial cutaway schematic of the metal oxide thin-film transistor array base palte making formation in third embodiment of the invention.
Fig. 5 is the partial cutaway schematic of the metal oxide thin-film transistor array base palte making formation in fourth embodiment of the invention.
Fig. 6 is the partial cutaway schematic of the metal oxide thin-film transistor array base palte making formation in fifth embodiment of the invention.
Fig. 7 is the partial cutaway schematic of the metal oxide thin-film transistor array base palte making formation in sixth embodiment of the invention.
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with drawings and Examples, to the specific embodiment of the present invention, structure, feature and effect thereof, be described in detail as follows.
Metal oxide TFT refers to thin-film transistor prepared by semiconductor layer employing metal oxide.Because metal oxide has as semi-conducting material, electron mobility is high, light durability good, photopermeability is high, aperture opening ratio high, can substitute amorphous silicon and the polysilicon semi-conducting material as TFT.Namely the embodiment of the present invention proposes a kind of manufacture method of metal oxide thin-film transistor array base palte.
First it should be noted that, thin-film transistor array base-plate comprises multi-strip scanning line and a plurality of data lines and mutually intersect the multiple pixel regions limited, scan line and data wire crossover location place are provided with thin-film transistor, the grid of thin-film transistor is connected with corresponding scan line, the source electrode of thin-film transistor is connected with corresponding data wire, the drain electrode of thin-film transistor is connected with the corresponding pixel electrode being positioned at pixel region, and this is well known to those skilled in the art.In order to illustrative simplicity, Fig. 1 to Fig. 7 only illustrates the part section structural representation of one of them pixel region.
First embodiment
Fig. 1 is the flow chart of the manufacture method of metal oxide thin-film transistor array base palte in the embodiment of the present invention, Fig. 2 is the partial cutaway schematic of the metal oxide thin-film transistor array base palte making formation in first embodiment of the invention, please refer to the drawing 1 and Fig. 2, this manufacture method comprises:
S11: make on underlay substrate 101 and form grid 102.Underlay substrate 101 is such as transparent glass substrate; When underlay substrate 101 makes grid 102, by such as sputtering (sputter) method first deposition formation layer of metal layer on underlay substrate 101, the material of this metal level is such as pure Mo, Mo/Ti, AlNd/MoTi etc., then carry out etch patterning by photoetching process to this metal level, grid 102 is formed to make on underlay substrate 101, wherein photoetching process mainly comprises the operations such as light blockage coating, exposure, development, etching, removing photoresistance, this knows for those skilled in the art, is not repeated herein.
S12: make on grid 102 and form gate insulator 103.The material of gate insulator 103 is such as silica (SiOx) or silicon nitride (SiNx), gate insulator 103 is formed on grid 102 by such as PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) method deposition.In the present embodiment, gate insulator 103 adopts the film layer structure of individual layer.In other embodiments, gate insulator 103 also can for the composite membrane formed by double-layer structure, namely on grid 102, first adopt higher deposition rate to make form lower floor's gate insulator 103 (i.e. GH), its rete is thicker, as the major part of gate insulator 103; Then on the basis of lower floor's gate insulator 103, adopt lower deposition rate to make again form upper strata gate insulator 103 (i.e. GL), its rete is thinner, the crucial rete contacted with semiconductor layer as gate insulator 103.
S13: make on gate insulator 103 and form semiconductor layer 104, pixel electrode layer 105, source electrode 106, drain electrode 107 and channel protective layer 108; wherein semiconductor layer 104 and pixel electrode layer 105 are made through a patterning within the same layer by transparent metal-oxide semiconductor (MOS) rete simultaneously and are formed, and channel protective layer 108 covers on semiconductor layer 104.
For step S13; in the present embodiment; when gate insulator 103 makes formation semiconductor layer 104, pixel electrode layer 105, source electrode 106,107 and the channel protective layer 108 of draining; take first to make on gate insulator 103 to form source electrode 106 and drain electrode 107; and then make formation semiconductor layer 104 and pixel electrode layer 105, make again afterwards and form channel protective layer 108.Particularly, first on gate insulator 103, form one deck source and drain metal level by such as sputtering method deposition, the material of this source and drain metal level is such as pure Mo, Mo/Ti, AlNd/MoTi etc., and carry out etch patterning by photoetching process to this source and drain metal level, form source electrode 106 and drain electrode 107 to make, source electrode 106 and drain electrode 107 are spaced from each other, then, source electrode 106 and drain electrode 107 deposit by such as sputtering method the metal-oxide semiconductor (MOS) rete forming layer of transparent again, the material of this metal-oxide semiconductor (MOS) rete is such as IGZO (Indium Gallium ZincOxide, indium gallium zinc oxide), ITZO (Indium Tin Zinc Oxide, indium tin zinc oxide) etc., IGZO is selected in the present embodiment, and carry out etch patterning by photoetching process to this metal-oxide semiconductor (MOS) rete, specifically comprise light blockage coating, exposure, development, etching, the operations such as removing photoresistance, semiconductor layer 104 and pixel electrode layer 105 is formed to make simultaneously, that is, simultaneously semiconductor layer 104 and pixel electrode layer 105 to be made through a patterning within the same layer by employing light shield (mask) by this metal-oxide semiconductor (MOS) rete to be formed, wherein semiconductor layer 104 is inserted in the gap between source electrode 106 and drain electrode 107, source electrode 106 and drain electrode 107 all contact with semiconductor layer 104, semiconductor layer 104 is connected with pixel electrode layer 105 by drain electrode 107, afterwards, semiconductor layer 104 and pixel electrode layer 105 are deposited by such as PECVD method again and forms layer protecting film layer, the material of this protective film is such as silica, and carry out etch patterning by photoetching process to this protective film, form channel protective layer 108 to make, and channel protective layer 108 covers on semiconductor layer 104.In this stage, semiconductor layer 104 and the transparent semiconductor of pixel electrode layer 105 all for being made up of IGZO.
S14: at semiconductor layer 104 by under the prerequisite of channel protective layer 108 covering protection, carries out ion implantation to pixel electrode layer 105, makes pixel electrode layer 105 change transparent conductor into by transparent semiconductor.Particularly, in order to realize the ion implantation to pixel electrode layer 105, independent plasma treatment can be carried out to this pixel electrode layer 105, be included in PECVD device, with H ion or Ar ion etc., plasma treatment is carried out to pixel electrode layer 105, be specially: in the reaction chamber of PECVD device, pass into H2 or Ar gas, pass into the flow control of H2 or Ar gas between 2000 ~ 8000sccm (under the status of criterion ml/min), the radio-frequency power applied controls between 4400 ~ 5360W (watt), and the time controlling plasma treatment is between 60 ~ 120s (second).After aforementioned plasma process, H ion or Ar ion implantation are in the metal oxide semiconductor material of pixel electrode layer 105, and pixel electrode layer 105 changes transparent conductor into by transparent semiconductor, using the pixel electrode as pixel region.In aforementioned plasma processing procedure, due to semiconductor layer 104 being coated with channel protective layer 108, semiconductor layer 104 is by channel protective layer 108 covering protection, thus semiconductor layer 104 can not be subject to the impact of ion implantation, is still maintained semiconductor.
Hold above-mentioned, the present invention, when making semiconductor layer 104 and pixel electrode layer 105, only needs one optical cover process, namely only needs use light shield (mask).And in prior art, pixel electrode is generally made up of ITO, semiconductor layer 104 and pixel electrode layer 105 need twice independently optical cover process make respectively.In the embodiment of the present invention, together with semiconductor layer 104 utilizes with pixel electrode layer 105, optical cover process is made through a patterning within the same layer by metal oxide semiconductor material simultaneously and is formed, and then ion implantation is carried out to pixel electrode layer 105, pixel electrode layer 105 is made to change transparent conductor into by transparent semiconductor, like this, array base palte uses metal oxide as the semiconductor layer of TFT, while lifting display performance, can also reduce by one optical cover process, save the expense of a light shield, reduce cost of manufacture, also improve production efficiency simultaneously.
Array base palte shown in Fig. 2, can as the infrabasal plate of the liquid crystal display of TN pattern, the liquid crystal layer that the liquid crystal display of TN pattern can also comprise upper substrate (i.e. colored filter substrate) and be folded between infrabasal plate and upper substrate, pixel electrode is formed at infrabasal plate, public electrode is formed at upper substrate, this is well known to those skilled in the art, and does not repeat them here.In fig. 2, because the pixel electrode of drain direct and pixel region is formed in electrical contact, not needing to make in addition through hole (through hole) like this, that drain electrode and pixel electrode are formed is in electrical contact again, has also simplified processing procedure further and has been beneficial to raising aperture opening ratio.
Second embodiment
Fig. 3 is the partial cutaway schematic of the metal oxide thin-film transistor array base palte making formation in second embodiment of the invention, and the difference of the present embodiment and the first embodiment is, the present embodiment also comprises further:
S15: make formation second protective layer 110 in channel protective layer 108, and on the second protective layer 110, make formation common electrode layer 111.Particularly, the material of the second protective layer 110 is such as silica or silicon nitride, is formed in channel protective layer 108, and covers pixel electrode layer 105 simultaneously by such as PECVD method deposition.The material of common electrode layer 111 is such as ITO (Indium Tin Oxide; tin indium oxide) or IZO (Indium Zinc Oxide; indium zinc oxide) etc.; be formed on the second protective layer 110 by such as sputtering method deposition; and carry out etch patterning by photoetching process to common electrode layer 111; in the present embodiment, common electrode layer 111 is etched at each pixel region and is formed as having multiple list structure, such as, in comb shape.
Array base palte shown in Fig. 3, can as the infrabasal plate of the liquid crystal display of FFS mode, the liquid crystal layer that the liquid crystal display of FFS mode can also comprise upper substrate (i.e. colored filter substrate) and be folded between infrabasal plate and upper substrate, be formed with pixel electrode and public electrode at infrabasal plate simultaneously, this is well known to those skilled in the art, and does not repeat them here.
In addition, in figure 3, as material selection silicon nitride (SiNx) of the second protective layer 110, when depositing formation the second protective layer 110, the plasma treatment to pixel electrode layer 105 can also be realized.When adopting PECVD method to prepare the SiNx film of the second protective layer 110; a large amount of H ions can be dissociateed in reacting gas SiH4 and NH3; H ionic adsorption is injected in the metal oxide semiconductor material of pixel electrode layer 105; make pixel electrode layer 105 become transparent conductor by transparent semiconductor, reaction equation is: SiH4+NH3+N2 → SiNx:H.At this, the concrete technology parameter utilizing PECVD method to prepare the SiNx film of the second protective layer 110 is: the gas flow of SiH4 is 1760sccm, the gas flow of NH3 is 17000sccm, the gas flow of N2 is 12760sccm, radio-frequency power is 4400 ~ 5360W, plate clearance (spacing) in reaction chamber is 900 ~ 1500mm (millimeter), plate clearance refers to the spacing between diffuser plate (diffuser) and bottom base (susceptor), diffuser plate is used for passing into gas, bottom base is for carrying by the substrate of film forming, gas pressure in reaction chamber is 1000 ~ 1350mtorr (person of outstanding talent's holder), film-forming temperature controls between 200 ~ 300 DEG C.
That is, the technique of pixel electrode layer 105 being carried out to ion implantation incidentally can complete when making the second protective layer 110, by a large amount of H ion implantations of dissociateing when making the second protective layer 110 in pixel electrode layer 105, realize the ion implantation to pixel electrode layer 105, pixel electrode layer 105 is made to become transparent conductor by transparent semiconductor, so namely, the step of pixel electrode layer 105 being carried out separately to ion implantation before making second protective layer 110 can be saved, namely before making second protective layer 110, without the need to carrying out ion implantation to pixel electrode layer 105 separately.
When the SiNx film of aforementioned making second protective layer 110; due to semiconductor layer 104 being coated with channel protective layer 108; semiconductor layer 104 is by channel protective layer 108 covering protection, thus semiconductor layer 104 can not be subject to the impact of ion implantation, is still maintained semiconductor.
3rd embodiment
Fig. 4 is the partial cutaway schematic of the metal oxide thin-film transistor array base palte making formation in third embodiment of the invention; the difference of the present embodiment and the first embodiment is; the present embodiment is for step S13; when gate insulator 103 makes formation semiconductor layer 104, pixel electrode layer 105, source electrode 106,107 and the channel protective layer 108 of draining, production order is different from the first embodiment.In the present embodiment, take first to make on gate insulator 103 to form semiconductor layer 104 and pixel electrode layer 105, and then make formation source electrode 106 and drain electrode 107, make again afterwards and form channel protective layer 108.Particularly, first on gate insulator 103, form the metal-oxide semiconductor (MOS) rete of layer of transparent by such as sputtering method deposition, the material of this metal-oxide semiconductor (MOS) rete is such as IGZO, ITZO etc., IGZO is selected in the present embodiment, and carry out etch patterning by photoetching process to this metal-oxide semiconductor (MOS) rete, specifically comprise light blockage coating, exposure, development, etching, the operations such as removing photoresistance, semiconductor layer 104 and pixel electrode layer 105 is formed to make simultaneously, that is, simultaneously semiconductor layer 104 and pixel electrode layer 105 to be made through a patterning within the same layer by employing light shield by this metal-oxide semiconductor (MOS) rete to be formed, then, semiconductor layer 104 and pixel electrode layer 105 are deposited by such as sputtering method again and forms one deck source and drain metal level, the material of this source and drain metal level is such as pure Mo, Mo/Ti, AlNd/MoTi etc., and carry out etch patterning by photoetching process to this source and drain metal level, source electrode 106 and drain electrode 107 is formed to make, source electrode 106 and drain electrode 107 are spaced from each other, source electrode 106 and drain electrode 107 all contact with semiconductor layer 104, and semiconductor layer 104 is connected with pixel electrode layer 105 by drain electrode 107, afterwards, source electrode 106 and drain electrode 107 are deposited by such as PECVD method again and forms layer protecting film layer, the material of this protective film is such as silica, and carry out etch patterning by photoetching process to this protective film, form channel protective layer 108 to make, and channel protective layer 108 covers on semiconductor layer 104.In this stage, semiconductor layer 104 and the transparent semiconductor of pixel electrode layer 105 all for being made up of IGZO.The foregoing etching to source and drain metal level can cause damage to the back of the body raceway groove of semiconductor layer 104, cause TFT hydraulic performance decline, therefore can increase that O2 electricity slurry processes, the processing procedure such as to anneal in oxygen-containing atmosphere to repair the back of the body raceway groove of metal oxide TFT, electrical to obtain good TFT.
About other steps of the present embodiment, see above-mentioned first embodiment, can not repeat them here.Array base palte shown in Fig. 4, can as the infrabasal plate of the liquid crystal display of TN pattern.
4th embodiment
Fig. 5 is the partial cutaway schematic of the metal oxide thin-film transistor array base palte making formation in fourth embodiment of the invention, and the difference of the present embodiment and the 3rd embodiment is, the present embodiment also comprises further:
S15: make formation second protective layer 110 in channel protective layer 108, and on the second protective layer 110, make formation common electrode layer 111.Particularly, the material of the second protective layer 110 is such as silica or silicon nitride, is formed in channel protective layer 108, and covers pixel electrode layer 105 simultaneously by such as PECVD method deposition.The material of common electrode layer 111 is such as ITO or IZO etc.; be formed on the second protective layer 110 by such as sputtering method deposition; and carry out etch patterning by photoetching process to common electrode layer 111; in the present embodiment; common electrode layer 111 is etched at each pixel region and is formed as having multiple list structure, such as, in comb shape.Array base palte shown in Fig. 5, can as the infrabasal plate of the liquid crystal display of FFS mode.
In addition, in Figure 5, as material selection silicon nitride (SiNx) of the second protective layer 110, when depositing formation the second protective layer 110, the plasma treatment to pixel electrode layer 105 can also be realized.When adopting PECVD method to prepare the SiNx film of the second protective layer 110; a large amount of H ions can be dissociateed in reacting gas SiH4 and NH3; H ionic adsorption is injected in the metal oxide semiconductor material of pixel electrode layer 105, makes pixel electrode layer 105 become transparent conductor by transparent semiconductor.That is, the technique of pixel electrode layer 105 being carried out to ion implantation incidentally can complete when making the second protective layer 110, by a large amount of H ion implantations of dissociateing when making the second protective layer 110 in pixel electrode layer 105, realize the ion implantation to pixel electrode layer 105, pixel electrode layer 105 is made to become transparent conductor by transparent semiconductor, so namely, the step of pixel electrode layer 105 being carried out separately to ion implantation before making second protective layer 110 can be saved, namely before making second protective layer 110, without the need to carrying out ion implantation to pixel electrode layer 105 separately.
When the SiNx film of aforementioned making second protective layer 110; due to semiconductor layer 104 being coated with channel protective layer 108; semiconductor layer 104 is by channel protective layer 108 covering protection, thus semiconductor layer 104 can not be subject to the impact of ion implantation, is still maintained semiconductor.
5th embodiment
Fig. 6 is the partial cutaway schematic of the metal oxide thin-film transistor array base palte making formation in fifth embodiment of the invention; the difference of the present embodiment and the first embodiment is; the present embodiment is for step S13; when gate insulator 103 makes formation semiconductor layer 104, pixel electrode layer 105, source electrode 106,107 and the channel protective layer 108 of draining, production order is different from the first embodiment.In the present embodiment, take first to make on gate insulator 103 to form semiconductor layer 104 and pixel electrode layer 105, and then make formation channel protective layer 108, make again afterwards and form source electrode 106 and drain electrode 107.Particularly, first on gate insulator 103, form the metal-oxide semiconductor (MOS) rete of layer of transparent by such as sputtering method deposition, the material of this metal-oxide semiconductor (MOS) rete is such as IGZO, ITZO etc., IGZO is selected in the present embodiment, and carry out etch patterning by photoetching process to this metal-oxide semiconductor (MOS) rete, specifically comprise light blockage coating, exposure, development, etching, the operations such as removing photoresistance, semiconductor layer 104 and pixel electrode layer 105 is formed to make simultaneously, that is, simultaneously semiconductor layer 104 and pixel electrode layer 105 to be made through a patterning within the same layer by employing light shield by this metal-oxide semiconductor (MOS) rete to be formed, then, semiconductor layer 104 and pixel electrode layer 105 are deposited by such as PECVD method again and forms layer protecting film layer, the material of this protective film is such as silica, and carry out etch patterning by photoetching process to this protective film, form channel protective layer 108 to make, and channel protective layer 108 covers on semiconductor layer 104, afterwards, channel protective layer 108 is deposited by such as sputtering method again and forms one deck source and drain metal level, the material of this source and drain metal level is such as pure Mo, Mo/Ti, AlNd/MoTi etc., and carry out etch patterning by photoetching process to this source and drain metal level, source electrode 106 and drain electrode 107 is formed to make, source electrode 106 and drain electrode 107 are spaced from each other, and source electrode 106 and drain electrode 107 all contact with semiconductor layer 104, and semiconductor layer 104 is connected with pixel electrode layer 105 by drain electrode 107.In this stage, semiconductor layer 104 and the transparent semiconductor of pixel electrode layer 105 all for being made up of IGZO.
About other steps of the present embodiment, see above-mentioned first embodiment, can not repeat them here.
In the present embodiment; owing to being coated with channel protective layer 108 on semiconductor layer 104; can be covered the semiconductor layer 104 of below by channel protective layer 108; thus make in the process forming source electrode 106 and drain electrode 107, can effectively prevent the etching technics making source electrode 106 and drain electrode 107 from causing damage to semiconductor layer 104 utilizing etching technics to etch source and drain metal level.And carrying out in the technique of ion implantation to pixel electrode layer 105, channel protective layer 108 also protects semiconductor layer 104 not by the impact of ion implantation technology.
In order to protect TFT region, the present embodiment also can make formation second protective layer 110 further in source electrode 106, drain electrode 107 and channel protective layer 108.The material of the second protective layer 110 is such as silica or silicon nitride, is formed on TFT region by such as PECVD method deposition.
Array base palte shown in Fig. 6, can as the infrabasal plate of the liquid crystal display of TN pattern.
6th embodiment
Fig. 7 is the partial cutaway schematic of the metal oxide thin-film transistor array base palte making formation in sixth embodiment of the invention, and the difference of the present embodiment and the 5th embodiment is, the present embodiment also comprises further:
S15: make formation second protective layer 110 in channel protective layer 108, and on the second protective layer 110, make formation common electrode layer 111.Particularly, the material of the second protective layer 110 is such as silica or silicon nitride, is formed in channel protective layer 108, and covers pixel electrode layer 105 simultaneously by such as PECVD method deposition.The material of common electrode layer 111 is such as ITO or IZO etc.; be formed on the second protective layer 110 by such as sputtering method deposition; and carry out etch patterning by photoetching process to common electrode layer 111; in the present embodiment; common electrode layer 111 is etched at each pixel region and is formed as having multiple list structure, such as, in comb shape.Array base palte shown in Fig. 7, can as the infrabasal plate of the liquid crystal display of FFS mode.
In addition, in the figure 7, as material selection silicon nitride (SiNx) of the second protective layer 110, when depositing formation the second protective layer 110, the plasma treatment to pixel electrode layer 105 can also be realized.When adopting PECVD method to prepare the SiNx film of the second protective layer 110; a large amount of H ions can be dissociateed in reacting gas SiH4 and NH3; H ionic adsorption is injected in the metal oxide semiconductor material of pixel electrode layer 105, makes pixel electrode layer 105 become transparent conductor by transparent semiconductor.That is, the technique of pixel electrode layer 105 being carried out to ion implantation incidentally can complete when making the second protective layer 110, by a large amount of H ion implantations of dissociateing when making the second protective layer 110 in pixel electrode layer 105, realize the ion implantation to pixel electrode layer 105, pixel electrode layer 105 is made to become transparent conductor by transparent semiconductor, so namely, the step of pixel electrode layer 105 being carried out separately to ion implantation before making second protective layer 110 can be saved, namely before making second protective layer 110, without the need to carrying out ion implantation to pixel electrode layer 105 separately.
When the SiNx film of aforementioned making second protective layer 110; due to semiconductor layer 104 being coated with channel protective layer 108; semiconductor layer 104 is by channel protective layer 108 covering protection, thus semiconductor layer 104 can not be subject to the impact of ion implantation, is still maintained semiconductor.
Comprehensively above-mentioned, the manufacture method that the above embodiment of the present invention provides, be applicable to making metal oxide thin-film transistor array base palte, the semiconductor layer of its thin-film transistor adopts metal oxide semiconductor material, possess that electron mobility is high, light durability good, photopermeability is high, aperture opening ratio high, the performance of display can be promoted; And, because semiconductor layer and pixel electrode layer adopt metal oxide semiconductor material, and make formation through a patterning within the same layer by a light shield simultaneously, namely in an optical cover process, define semiconducting channel region and pixel electrode area simultaneously, and then utilize ion implantation technology to make pixel electrode layer change transparent conductor into by transparent semiconductor, using the pixel electrode as pixel region.And in prior art, semiconductor layer and pixel electrode layer need twice independently optical cover process make respectively, the present invention can save one optical cover process compared to existing technology, decreases the usage quantity of light shield, reduces cost of manufacture, improves production efficiency.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be do not depart from technical solution of the present invention content, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (10)
1. a manufacture method for metal oxide thin-film transistor array base palte, is characterized in that, this manufacture method comprises:
Underlay substrate makes and forms grid;
Make on the gate and form gate insulator;
This gate insulator makes and forms semiconductor layer, pixel electrode layer, source electrode, drain electrode and channel protective layer, wherein this semiconductor layer and this pixel electrode layer are made through a patterning within the same layer by transparent metal-oxide semiconductor (MOS) rete simultaneously and are formed, and this channel protective layer covers on this semiconductor layer; And
At this semiconductor layer by under the prerequisite of this channel protective layer covering protection, ion implantation is carried out to this pixel electrode layer, make this pixel electrode layer change transparent conductor into by transparent semiconductor.
2. the manufacture method of metal oxide thin-film transistor array base palte as claimed in claim 1, it is characterized in that, the mode of this pixel electrode layer being carried out to ion implantation is carry out independent plasma treatment to this pixel electrode layer.
3. the manufacture method of metal oxide thin-film transistor array base palte as claimed in claim 2, it is characterized in that, carry out independent plasma treatment to this pixel electrode layer to comprise: in PECVD device, carry out plasma treatment with H ion or this pixel electrode layer of Ar ion pair.
4. the manufacture method of metal oxide thin-film transistor array base palte as claimed in claim 2; it is characterized in that; this manufacture method also comprises further: in this channel protective layer, make formation second protective layer, and on this second protective layer, make formation common electrode layer.
5. the manufacture method of metal oxide thin-film transistor array base palte as claimed in claim 1; it is characterized in that; this manufacture method also comprises further: in this channel protective layer, make formation second protective layer, and on this second protective layer, make formation common electrode layer.
6. the manufacture method of metal oxide thin-film transistor array base palte as claimed in claim 5; it is characterized in that; the material selection silicon nitride of this second protective layer, carries out the mode of ion implantation for incidentally completing when making this second protective layer to this pixel electrode layer.
7. the manufacture method of metal oxide thin-film transistor array base palte as claimed in claim 1; it is characterized in that; on this gate insulator make formed semiconductor layer, pixel electrode layer, source electrode, drain electrode and channel protective layer time; first make on this gate insulator and form this source electrode and this drain electrode; and then make this semiconductor layer of formation and this pixel electrode layer, make again afterwards and form this channel protective layer.
8. the manufacture method of metal oxide thin-film transistor array base palte as claimed in claim 1; it is characterized in that; on this gate insulator make formed semiconductor layer, pixel electrode layer, source electrode, drain electrode and channel protective layer time; first make on this gate insulator and form this semiconductor layer and this pixel electrode layer; and then make this source electrode of formation and this drain electrode, make again afterwards and form this channel protective layer.
9. the manufacture method of metal oxide thin-film transistor array base palte as claimed in claim 1; it is characterized in that; on this gate insulator make formed semiconductor layer, pixel electrode layer, source electrode, drain electrode and channel protective layer time; first make on this gate insulator and form this semiconductor layer and this pixel electrode layer; and then make this channel protective layer of formation, make again afterwards and form this source electrode and this drain electrode.
10. the manufacture method of the metal oxide thin-film transistor array base palte as described in any one of claim 1 to 9, is characterized in that, the material of this metal-oxide semiconductor (MOS) rete is IGZO or ITZO.
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| CN111613576A (en) * | 2020-05-21 | 2020-09-01 | 南京中电熊猫平板显示科技有限公司 | Array substrate and manufacturing method thereof |
| CN111725134A (en) * | 2020-05-21 | 2020-09-29 | 南京中电熊猫液晶显示科技有限公司 | Array substrate and manufacturing method thereof |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee after: Kunshan Longteng Au Optronics Co Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee before: Kunshan Longteng Optronics Co., Ltd. |