CN109727854B - 半导体装置及其形成方法 - Google Patents
半导体装置及其形成方法 Download PDFInfo
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Abstract
鳍式场效晶体管的栅极隔离插塞的形成方法包含形成长形栅极,形成与长形栅极的第一和第二侧壁接触的第一和第二间隙物,使用第一蚀刻步骤和第二蚀刻步骤将长形栅极分离为第一栅极部分和第二栅极部分,以及在第一栅极部分与第二栅极部分之间形成栅极隔离插塞,其中栅极隔离插塞的长度大于第一栅极部分或第二栅极部分的长度。
Description
技术领域
本公开实施例涉及半导体装置及其形成方法,特别涉及鳍式场效晶体管及其形成方法。
背景技术
金属氧化物半导体(metal-oxide-semiconductor,MOS)装置为集成电路中基础的构成元件。典型上,现存的金属氧化物半导体装置具有掺杂P型或 N型杂质的多晶硅的栅极电极,使用例如为离子注入或热扩散的掺杂操作 (operation)。调整栅极电极的功函数至硅的能带边缘(band-edge)。对于N型的金属氧化物半导体(NMOS)装置,可将其功函数调整至接近硅的传导带 (conduction band)。对于P型的金属氧化物半导体(PMOS)装置,可将其功函数调整至接近硅的价带(valence band)。通过选择合适的杂质以达成多晶硅栅极电极的功函数的调整。
具有多晶硅栅极电极的金属氧化物半导体装置展现出载流子空乏 (carrierdepletion)效应,也称为多晶硅空乏(poly depletion)效应。当施加的电场自靠近栅极介电质的栅极区域清除载流子形成空乏层时,即产生多晶硅空乏效应。在N型掺杂的多晶硅层中,空乏层包含离子化不可移动的施体 (donor)位置,而在P型掺杂的多晶硅层中,空乏层包含离子化不可移动的受体(acceptor)位置。空乏效应使得有效栅极介电质的厚度增加,进而使半导体的表面较难产生反转(inversion)层。
多晶硅空乏问题可通过形成金属栅极电极或金属硅化物栅极电极以解决,且N型金属氧化物半导体(NMOS)装置和P型金属氧化物半导体(PMOS) 装置中使用的金属栅极也可具有能带边缘的功函数。由于N型金属氧化物半导体装置和P型金属氧化物半导体装置在功函数方面具有不同的需求,故使用双栅极(dual-gate)的互补式金属氧化物半导体(complementary metal-oxide-semiconductor,CMOS)装置。
在金属栅极电极的形成中,先形成长的虚设(dummy)栅极,然后将其蚀刻,以使长的虚设栅极的部分彼此分离。接着在通过蚀刻移除长的虚设栅极的部分留下的孔洞内填入介电材料。随后研磨介电材料,留下在虚设栅极的剩余部分之间的介电材料的部分。接着以金属栅极替换虚设栅极的分离部分。
发明内容
根据本公开的一实施例,半导体装置的形成方法包含形成长形 (elongated)栅极,以及形成与长形栅极的第一侧壁和第二侧壁接触的第一间隙物和第二间隙物。半导体装置的形成方法也包含使用第一蚀刻步骤和第二蚀刻步骤将长形栅极分离为第一栅极部分和第二栅极部分。半导体装置的形成方法还包含在第一栅极部分与第二栅极部分之间形成栅极隔离插塞,其中栅极隔离插塞的长度大于第一栅极部分或第二栅极部分的长度。
根据本公开的另一实施例,半导体装置的形成方法包含形成长形栅极,其包含第一长度。半导体装置的形成方法也包含形成接触长形栅极的第一间隙物和第二间隙物,以及蚀刻长形栅极以形成第一开口,其中第一开口将长形栅极分离为第一栅极部分和第二栅极部分。半导体装置的形成方法还包含蚀刻长形栅极以形成大于第一开口的第二开口,第二开口包含大于第一长度的第二长度,以及在第二开口内沉积介电层。
根据本公开的又一实施例,半导体装置包含长形栅极,其包含第一长度,以及栅极隔离插塞,将长形栅极区分为第一栅极部分和第二栅极部分,其中栅极隔离插塞包含大于第一长度的第二长度。半导体装置也包含第一鳍式场效晶体管,其包含第一半导体鳍,其中第一栅极部分横跨第一半导体鳍。半导体装置还包含第二鳍式场效晶体管,其包含第二半导体鳍,其中第二栅极部分横跨第二半导体鳍。
附图说明
通过以下的详述配合所附附图,我们能更加理解本公开实施例的内容。需注意的是,根据工业上的标准惯例,许多部件(feature)并未按照比例绘制。事实上,为了能清楚地讨论,这些部件的尺寸可能被任意地增加或减少。
图1A-图1C、图2A-图2C、图3A-图3C、图4A-图4C、图5A-图5C 和图6A-图6D是根据一些实施例,显示形成鳍式场效晶体管(finfield effect transistor,FinFET)和栅极隔离插塞的各个中间阶段的剖面示意图、俯视图和透视图;
图7A-图7D和图8是根据一些实施例,显示形成栅极隔离插塞的工艺流程图。
附图标记说明:
1C-1C、1A-1A、2A-2A、2C-2C~剖面;
2~半导体晶片;
20~基底;
22~隔离区;
22A、22B~隔离位置;
24~半导体鳍;
26~栅极介电质;
28~虚设栅极电极;
30~硬掩模;
32、32A、32B~虚设栅极堆叠;
34~栅极间隙物;
34A、34B~栅极间隙物部分;
34A’、34B’~缩小尺寸的栅极间隙物部分;
36~层间介电层;
38~源极和漏极区;
40~源/漏极硅化物区;
42~源/漏极接触插塞;
46~开口;
48~装置区;
50~装置部分;
52~介电栅极隔离插塞;
52A、52B、52C、52D~栅极隔离插塞;
56A、56B~金属栅极部分;
58、62、64、68~末端部分;
60、66~中央部分;
70A、70B、70C、70D~插塞长度;
72A、72B、72C、72D~金属栅极长度;
200~制造流程;
202、204、206、208、210、212、214、302、304、306A、306B、306C、 306D~步骤。
具体实施方式
以下提供了很多不同的实施例或范例,用于实施本公开实施例的不同部件。组件和配置的具体范例描述如下,以简化本公开实施例的说明。当然,这些仅仅是范例,并非用以限定本公开实施例。举例而言,以下叙述中提及第一部件形成于第二部件之上或上方,可能包含第一和第二部件直接接触的实施例,也可能包含额外的部件形成于第一和第二部件之间,使得第一和第二部件不直接接触的实施例。此外,本公开实施例在各种范例中可能重复参考数字和/或字母,此重复是为了简化和清楚,并非在讨论的各种实施例和/或组态之间指定其关系。
再者,空间上相关的措辞,例如“在……之下”、“在……下方”、“下方的”、“在……上方”、“上方的”和其他类似的用语可用于此,使得描述图中所示的一元件或部件与其他元件或部件之间的关系更容易。此空间上相关的措辞意欲包含除附图描绘的方向外,使用或操作中的装置的不同方向。设备可以其他方向定位(旋转90度或其他定位方向),且在此使用的空间相关描述可同样依此解读。
根据各种示范的实施例,提供半导体装置及其形成方法,特别是有关于栅极隔离结构及其形成方法。根据一些实施例,显示形成栅极隔离结构的各个中间阶段。一些实施例的一些变化将在此进行讨论。在以下各个示意图和显示的实施例中,相似的参考符号用以指明相似的元件。
图1A-图1C、图2A-图2C、图3A-图3C、图4A-图4C、图5A-图5C 和6A-6D是根据一些实施例,显示形成鳍式场效晶体管(FinFET)和栅极隔离结构的各个中间阶段的剖面示意图、俯视图和透视图。图1A-图1C、图 2A-图2C、图3A-图3C、图4A-图4C、图5A-图5C和图6A-图6D所示出的各个中间阶段也示意性地显示于图7A-图7D和图8的工艺流程中。
图1A是根据一些实施例,显示初始步骤及产生的结构。提供基底20,基底20为半导体晶片2的一部分。基底20可为半导体基底,例如硅基底,或者可使用其他材料,例如硅锗、碳化硅或其相似物。基底20也可为整体 (bulk)半导体基底或绝缘层上覆半导体(semiconductor-on-insulator)基底。
在一实施例中,形成延伸进入基底20的隔离区22,然而,若使用其他方法来制造半导体鳍24可能并非这种情况。隔离区22可例如为浅沟槽隔离(shallow trench isolation,STI)区。浅沟槽隔离区22的形成方式可包含蚀刻半导体基底20以形成沟槽(未示出),并将介电材料填入沟槽以形成浅沟槽隔离区22。浅沟槽隔离区22可由氧化硅形成,然而在其他实施例中也可使用其他的介电材料。
半导体鳍24自浅沟槽隔离区22的顶面突出,且与底下的半导体长条 (strip)重叠,半导体长条是指在浅沟槽隔离区22之间的半导体基底20的部分。半导体鳍24的形成方式可包含形成顶面齐平于半导体鳍24的顶面的浅沟槽隔离区22,以及将浅沟槽隔离区22凹陷。在浅沟槽隔离区22移除的部分之间的半导体材料的部分因此成为半导体鳍24。半导体鳍24以及一些或大抵上整体的半导体长条可由硅或其他包含硅的化合物(包含但不限于碳化硅、硅锗或其相似物)形成。
在浅沟槽隔离区22和半导体鳍24上形成虚设栅极堆叠32。相应的步骤显示于图8所示的制造流程200的步骤202中。虚设栅极堆叠32包含栅极介电质26和位于栅极介电质26上的虚设栅极电极28。根据一些实施例,可在后续的步骤中移除位于虚设栅极电极28下的部分的栅极介电质26,因此,栅极介电质26为虚设栅极介电质。根据一些实施例,虚设栅极电极28 下的部分的栅极介电质26也可保留至最终装置中,因此,栅极介电质26 作为结果产生的鳍式场效晶体管的栅极介电质。根据本公开的一些实施例,栅极介电质26包含氧化硅。根据一些其他的实施例,栅极介电质26也可使用其他材料来形成,例如氮化硅、碳化硅或其相似物。栅极介电质26可通过将半导体鳍24氧化以形成,因此栅极介电质26如图1A所示共形地 (conformally)形成于半导体鳍24上。根据一些其他的实施例,通过沉积以形成栅极介电质26,因此栅极介电质26除了显示的部分以外,也将包含位于浅沟槽隔离区22的顶面上的水平部分。栅极介电质26的水平部分是以虚线显示。
虚设栅极电极28可包含多晶硅。根据一些实施例,虚设栅极堆叠32 还包含在虚设栅极电极28上的硬掩模30。举例而言,硬掩模30可由氮化硅形成,然而也可使用其他材料来形成,例如碳化硅、氮氧化硅或其相似物。一些其他的实施例中可不形成硬掩模30。因此,图1A中使用虚线以显示硬掩模30的位置。
如图1A所示,虚设栅极堆叠32横跨于多个半导体鳍24之上。图1B 是根据一些实施例显示虚设栅极堆叠32的俯视图,其中图1A为沿着图1B 的线1A-1A的剖面示意图,以下又称为顺着栅极方向的剖面示意图。可以理解的是,虽然为了简化,图1A和图1B显示虚设栅极堆叠32横跨于两个半导体鳍24之上,然而虚设栅极堆叠32可横跨于三个、四个或更多的半导体鳍24之上(且延伸至半导体鳍24的侧壁上)。
参见图1B,在虚设栅极堆叠32的侧壁上形成栅极间隙物34。栅极间隙物34可形成为包围虚设栅极堆叠32的环。栅极间隙物34可由氧化物、氮化物、氮氧化物、碳化物或其相似物形成。在一些特别的实施例中,栅极间隙物34可由SiN、SiON、SiOCN、SiC或SiOC,或者其他相似的材料以形成。栅极间隙物34可具有约至的厚度。根据一些示范的实施例,栅极间隙物34可包含氧化硅层和氧化硅层上的氮化硅层,其中氧化硅层可具有L形的剖面,且氮化硅层位于氧化硅层的水平的脚(即水平的部分)上。
再参见图1B,层间介电(inter-layer dielectric,ILD)层36环绕虚设栅极堆叠32和栅极间隙物34。也参见图1B的装置区48,装置区48对应至后续将详细描述的图案化的硬掩模30的区域,包含栅极间隙物部分34A和 34B。
图1C显示图1B中结构的剖面示意图,其中图1C为沿着图1B的线 1C-1C的剖面示意图,以下又称为穿过栅极的方向的剖面示意图。层间介电层36的顶面与虚设栅极堆叠32的顶面和栅极间隙物34的顶面共平面(栅极间隙物34包含栅极间隙物部分34A和34B)。层间介电层36可毯覆性地形成于高于虚设栅极堆叠32的顶面的高度上,然后进行平坦化(例如化学机械研磨(chemical mechanical polish,CMP))以移除层间介电层36超出的部分,其中层间介电层36超出的部分是指高于虚设栅极堆叠32的顶面和栅极间隙物34的顶面的部分。层间介电层36可包含流动式的氧化物,使用例如流动式化学气相沉积(flowable chemicalvapor deposition,FCVD)以形成。层间介电层36也可为使用旋转涂布(spin coating)以形成的旋涂式玻璃(spin-on glass)。层间介电层36也可由磷硅酸盐玻璃(phosopho-silicate glass,PSG)、硼硅酸盐玻璃(boron-silicate glass,BSG)、掺硼磷硅酸盐玻璃(boron-doped phosopho-silicate glass,BPSG)、四乙氧基硅烷(tetraethylorthosilicate,TEOS) 氧化物、TiN、SiOC或其他低介电常数(low-k)无孔洞(non-porous)的介电材料以形成。
根据一些实施例,如图1C所示,在半导体鳍24两侧末端部分未由虚设栅极堆叠32所覆盖处形成源极和漏极区38(后续又称为源/漏极区)。可通过在半导体鳍24的末端部分进行注入以形成源/漏极区38,或者通过凹陷半导体鳍24的末端部分以形成凹陷,随后在凹陷内再生长源/漏极区38。源/漏极硅化物区40可形成于源/漏极区38的表面上。可形成延伸进入层间介电层36以电性连接于源/漏极区38的源/漏极接触插塞42。源/漏极接触插塞42可由钨或其他导电材料/金属以形成。在其他实施例中,将源/漏极硅化物区40和源/漏极接触插塞42在后续的阶段形成,而非在此阶段形成。相似地,源/漏极接触插塞42也可于初始阶段或在后续的阶段形成,因此,使用虚线以示出源/漏极接触插塞42的位置。
图1C也显示装置部分50,相关的部分包含一部分的层间介电层36、栅极间隙物34和虚设栅极堆叠32。图1A至图1C示出根据一些实施例准备形成栅极隔离插塞的装置的三个不同的示意图。特别来说,图1A至图 1C显示图8中工艺步骤202与204之间包含个别部件的细节。图1B示出虚设栅极堆叠32与相关的栅极间隙物部分34A和34B以及包含装置区48 的俯视图。图1A示出顺着装置的虚设栅极堆叠32、选择性形成的硬掩模 30、半导体鳍24和隔离区22的栅极方向的剖面示意图。图1C示出穿过装置的栅极的方向的剖面示意图,显示隔离区22、分离的层间介电层36、栅极间隙物部分34A和34B、虚设栅极堆叠32以及选择性形成的硬掩模30。
参见图2A,将硬掩模30图案化。图2B显示出图2A的结构的俯视图。如图2B所示,硬掩模30覆盖虚设栅极堆叠32的两侧末端部分,同时留下未覆盖的虚设栅极堆叠32的中央部分。然后通过硬掩模30中的开口蚀刻虚设栅极堆叠32。相应的步骤显示于图8所示的制造流程200的步骤204 中。结果,如图2A和图2B所示,移除虚设栅极堆叠32的中央部分,根据一些实施例,将长的虚设栅极堆叠32切为两个分离且彼此不连续的部分。剩余的部分称为虚设栅极堆叠32A和32B。在本实施例中,图1B的虚设栅极堆叠32横跨三个、四个或更多的半导体鳍24,可将虚设栅极堆叠32切为三个、四个或更多个分离的部分。再者,虚设栅极堆叠32的每一个分离的部分可横跨一个、两个或更多的半导体鳍24,以形成具有单一个鳍的鳍式场效晶体管,或具有多个鳍的鳍式场效晶体管。
蚀刻虚设栅极堆叠32的结果,使得虚设栅极堆叠32A与32B之间形成开口46。再者,开口46形成于栅极间隙物部分34A与34B之间,且栅极间隙物部分34A和34B为栅极间隙物34的两侧平行部分。每一个栅极间隙物部分34A和34B具有暴露于开口46的侧壁。如图2A所示,当虚设栅极介电质26具有如虚线所示出的水平部分时,开口46可暴露出水平部分。再者,在蚀刻虚设栅极堆叠32的期间,可移除栅极介电质26暴露出的水平部分,或留下(且薄化)栅极介电质26暴露出的水平部分。
根据一些实施例,图2A至图2C示出形成装置的栅极隔离插塞的第一蚀刻步骤期间的三个示意图。如前述关于图1A至图1C的讨论,图2B显示在第一蚀刻步骤之后,相同装置部分俯视图,后续将进行详细的讨论,其中图2A为沿着图2B的线2A-2A的装置部分的剖面示意图,即前述的顺着栅极的方向,且图2C为沿着图2B的线2C-2C的装置部分的剖面示意图,即前述的穿过栅极的方向。图2A、图2B和图2C示出X、Y和Z轴,其中以虚线示出自附图的表面向外延伸的轴向。
特别来说,图2A至图2C显示在图8的工艺步骤204的第一蚀刻步骤期间的装置。图2B示出通过第一蚀刻步骤使用硬掩模30(未示出于图2B 中)将虚设栅极堆叠32于开口46的位置分离为虚设栅极堆叠32A和32B。图2A示出通过第一蚀刻步骤使用硬掩模30将虚设栅极堆叠32于开口46 的位置分离为虚设栅极堆叠32A和32B,且顺着装置的虚设栅极堆叠32的栅极方向的剖面示意图。图2C示出使用第一蚀刻步骤将开口46处的虚设栅极堆叠32移除,且穿过栅极的方向的装置部分50的剖面示意图。
根据一些实施例,参照图3A至图3C、图4A至图4C和图5A至图5C,进一步解释蚀刻虚设栅极堆叠32以在虚设栅极堆叠32A与32B之间形成开口46。特别在与图1A的剖面示意图相关的特殊后续工艺步骤、结构及个别部件中,装置区48(示出于图1B的俯视图中)和装置部分50(示出于图1C 的剖面示意图中)将在以下做进一步地详述。根据一些实施例,图6A至图6C显示放置于虚设栅极堆叠32A与32B之间的开口46内的不同形状的栅极隔离插塞。
根据一些实施例,图3A至图3C示出形成装置的栅极隔离插塞的第二蚀刻步骤期间的三个示意图。特别来说,图3A至图3C显示出在图8的工艺步骤204的第二蚀刻步骤期间的装置。根据一些实施例,图3B示出使用第二蚀刻步骤使开口46扩大及延伸进入栅极间隙物部分34A和34B的装置区48的俯视图。图3A示出通过第二蚀刻步骤使用硬掩模30在开口46的位置持续分离栅极堆叠部分32A和32B,顺着装置的栅极方向的剖面示意图。图3C示出使用第二蚀刻步骤缩小栅极间隙物部分34A和34B的尺寸,以产生缩小尺寸的栅极间隙物部分34A’和34B’。第一蚀刻步骤使用干式蚀刻,且第二蚀刻步骤可为干式蚀刻或湿式蚀刻步骤。再者,以下将根据一些实施例,详述第一蚀刻步骤和第二蚀刻步骤,以及可形成的相应的栅极隔离插塞的各种形状和尺寸。
根据一些实施例,图4A至图4C示出在形成栅极隔离插塞和移除虚设栅极的期间装置的三个示意图。特别来说,图4A至图4C显示出在图8的工艺步骤206、208和210的装置。图4B示出装置区48的俯视图,显示沉积介电栅极隔离插塞52、化学机械研磨,以及随后移除隔离位置22A和22B 上的虚设栅极堆叠部分。图4A示出顺着装置的栅极方向的剖面示意图,显示沉积介电栅极隔离插塞52,以及移除虚设栅极堆叠。图4C示出穿过栅极方向的装置部分50的剖面示意图,显示沉积介电栅极隔离插塞52,以及化学机械研磨步骤的结果。
根据一些实施例,图5A至图5C示出在形成金属替代栅极的期间装置的三个示意图。特别来说,图5A至图5C显示出在图8的工艺步骤214的装置。图5B示出装置区48的俯视图,显示由栅极隔离插塞52所分离的金属栅极部分56A和56B。图5A示出顺着装置的栅极方向的剖面示意图,显示由栅极隔离插塞52所分离的金属栅极部分56A和56B。图5C示出穿过栅极方向的装置部分50的剖面示意图,显示金属栅极形成之后的剖面示意图。由于在图5C中无法看见金属栅极,因此图4C和图5C图大抵上相同。
金属栅极部分56A和56B可由钨(W)、Al、Cu、AlCu、Ti、TiAlN、TaC、 TaCN、TaSiN、Mn、Zr、TiN、Ta、TaN、Co、Ni,或者其他金属或金属合金以形成。金属栅极部分56A和56B可具有约至的厚度。
图6A至图6D显示包含金属栅极部分56A和56B(又称为第一和第二金属栅极部分)、相关的栅极间隙物部分34A和34B,以及对应的栅极隔离插塞52A、52B、52C和52D的装置区48的四个俯视图。以下将详述每一个栅极隔离插塞52A、52B、52C和52D的形状、尺寸和形成方法。
图6A大致相应于先前的图5B,但被重复以显示出其与另外三个栅极隔离插塞的形状对比,以及包含金属栅极长度和栅极隔离插塞长度的尺寸。图6A示出包含金属栅极部分56A和56B、栅极间隙物部分34A和34B以及栅极隔离插塞52A(又称为介电栅极隔离插塞)的装置区48的俯视图。在一实施例中,栅极隔离插塞52A具有椭圆或橄榄球的形状。以下接着描述产生椭圆形的栅极隔离插塞52A的第一和第二蚀刻步骤。注意插塞长度70A 大于金属栅极长度72A,且栅极隔离插塞52A延伸进入栅极间隙物部分34A 和34B。在图6A至图6D中,插塞长度70A和金属栅极长度72A定义在相同的方向上。在一实施例中,金属栅极长度72A大约为7nm,然而也可使用其他的栅极长度,例如14nm、16nm、20nm和45nm,以及其他为了符合特殊应用而设定的栅极长度。在一实施例中,插塞长度70A与金属栅极长度72A之间的差异大于约因此,在一实施例中,金属栅极长度72A 大约为且插塞长度70A大于约
如前所述,在第一蚀刻步骤中,使用干式蚀刻以移除硅虚设栅极的一部分。第一蚀刻步骤中的干式蚀刻化学液使用F、Cl或HBr干式蚀刻,具有高度的Si对SiN的蚀刻选择性(只蚀刻Si),以及使用非常高的500伏特至1500伏特的偏压电压(垂直蚀刻)和20毫托(mTorr)至100mTorr的压力(或其他合适的工作压力)。干式蚀刻的时间长度约为30分钟至200分钟,持续时间视使用的电压及压力而定。第一蚀刻步骤之后,接着在温度范围约50℃至100℃的状态下使用稀释的HF(10%-90%)进行约20至120分钟的清洗步骤。清洗步骤的持续时间视使用的浓度和温度而定。
在一实施例中,第二蚀刻步骤为湿式蚀刻步骤,且第二蚀刻步骤用于回推栅极间隙物的SiN。第二蚀刻步骤中的湿式蚀刻化学液使用湿式蚀刻工艺(H3PO4)以回推SiN,H3PO4具有高度的SiN对Si的蚀刻选择性(只蚀刻 SiN)。H3PO4在约50℃至100℃的温度下使用。使用约10分钟至35分钟的蚀刻时间。第二蚀刻步骤的蚀刻时间视使用的温度而定。
图6B示出包含金属栅极部分56A和56B、栅极间隙物部分34A和34B 以及介电栅极隔离插塞52B的装置区48的俯视图。在一实施例中,栅极隔离插塞52B具有正方形的形状,且具有圆滑的角落。以下接着描述产生正方形的栅极隔离插塞52B的第一和第二蚀刻步骤。注意插塞长度70B大于金属栅极长度72B,且栅极隔离插塞52B延伸进入栅极间隙物部分34A和34B。在一实施例中,插塞长度70B与金属栅极长度72B之间的差异大于约在一实施例中,如前所述,栅极隔离插塞52B的外部尺寸至少在长度上为
形成栅极隔离插塞52B的第一蚀刻步骤和相应的清洗步骤与前述图6A 所示的栅极隔离插塞52A相同。
第二蚀刻步骤为干式蚀刻步骤。第二蚀刻步骤中的干式蚀刻化学液使用干式蚀刻工艺(CH3F或CHF3),以及500伏特至1400伏特的高偏压电压和约5mTorr至60mTorr的低压。使用在约7分钟至约55分钟之间的蚀刻时间,蚀刻时间视使用的压力、化学液及偏压电压而定。
图6C示出包含金属栅极部分56A和56B、栅极间隙物部分34A和34B 以及介电栅极隔离插塞52C的装置区48的俯视图。在一实施例中,栅极隔离插塞52C具有变形的正方形的形状,其具有规则的中央部分60以及第一和第二不规则的末端部分58和62。以下接着描述产生栅极隔离插塞52C 的第一和第二蚀刻步骤。注意插塞长度70C大于金属栅极长度72C,且栅极隔离插塞52C延伸进入栅极间隙物部分34A和34B。在一实施例中,插塞长度70C与金属栅极长度72C之间的差异大于约在一实施例中,如前所述,栅极隔离插塞52C的外部尺寸至少在长度上为
形成栅极隔离插塞52C的第一蚀刻步骤和相应的清洗步骤与前述图6A 所示的栅极隔离插塞52A相同。
第二蚀刻步骤为干式蚀刻步骤。第二蚀刻步骤中的干式蚀刻化学液使用CH3F或CHF3,以及在100伏特至200伏特的低偏压电压和80mTorr至 160mTorr的高压力下进行。使用约14分钟至约100分钟之间的蚀刻时间,蚀刻时间可视使用的压力、化学液及偏压电压而定。
图6D示出包含金属栅极部分56A和56B、栅极间隙物部分34A和34B 以及介电栅极隔离插塞52D的装置区48的俯视图。在一实施例中,栅极隔离插塞52D具有柠檬形的形状,具有大致椭圆的中央部分66以及两个末端部分64和68。以下接着描述产生柠檬形的栅极隔离插塞52D的第一和第二蚀刻步骤。注意插塞长度70D大于金属栅极长度72D,且栅极隔离插塞52D延伸进入栅极间隙物部分34A和34B。在一实施例中,插塞长度70D 与金属栅极长度72D之间的差异大于约在一实施例中,如前所述,栅极隔离插塞52D的外部尺寸至少在长度上为
形成栅极隔离插塞52D的第一蚀刻步骤和相应的清洗步骤与前述图6A 所示的栅极隔离插塞52A相同。
第二蚀刻步骤为湿式蚀刻步骤,如前所述,湿式蚀刻步骤使用H3PO4以回推栅极间隙物的SiN,H3PO4具有高度的SiN对Si的蚀刻选择性(只蚀刻SiN)。H3PO4在约50℃至100℃的温度下使用。使用约35分钟至90分钟的蚀刻时间,视第二蚀刻工艺使用的温度而定。
图7A至图7D为第一和第二蚀刻步骤以及清洗步骤的总结,第一和第二蚀刻步骤以及清洗步骤用于将第一和第二虚设栅极部分,以及后续的金属栅极部分分离且形成栅极隔离插塞。第一和第二蚀刻步骤,以及清洗步骤全部皆发生在图8的切割虚设栅极堆叠以及形成开口的步骤204,以下将进行总结。图7A显示关于椭圆形栅极隔离插塞52A的一实施方式,包含干式蚀刻步骤302、清洗步骤304和进行第一时间区段T1的湿式蚀刻步骤 306A。图7B显示关于正方形栅极隔离插塞52B的一实施方式,包含干式蚀刻步骤302、清洗步骤304,以及在第一偏压电压V1和第一压力P1下进行的干式蚀刻步骤306B。图7C显示关于变形的正方形栅极隔离插塞52C 的一实施方式,包含干式蚀刻步骤302、清洗步骤304,以及在第二偏压电压V2和第二压力P2下进行的干式蚀刻步骤306C。图7D显示关于柠檬形栅极隔离插塞52D的一实施方式,包含干式蚀刻步骤302、清洗步骤304 和进行第二时间区段T2的湿式蚀刻步骤306D。一些实施例中,第一时间区段T1与第二时间区段T2为不同的时间区段,第一偏压电压V1与第二偏压电压V2为不同的电压,且第一压力P1与第二压力P2为不同的压力。
图8总结了前述使用栅极隔离插塞的鳍式场效晶体管的实施方法的制造流程200。虚设栅极堆叠于步骤202中形成,且在步骤204中切割虚设栅极结构以及形成开口。在步骤206中将介电层填入开口,以及在步骤208 中进行平坦化以形成栅极隔离插塞。在步骤210中移除虚设栅极堆叠,且在步骤212中将栅极隔离插塞平坦化。在步骤214中形成替代栅极,例如金属栅极。
可以理解的是,虽然在此使用鳍式场效晶体管为范例,本公开的一些实施例的概念也可用于平面(planar)晶体管。平面晶体管的结构和形成方法以及相应的栅极隔离插塞相似于前述内容及前述所示,除了使用平面主动区而非半导体鳍以外。
本公开的一些实施例具有一些优势特征。参照图6A至图6D,可使用任何栅极隔离插塞52A至52D以缩小或大抵上消除关于不同电性隔离的鳍式场效晶体管的栅极金属部分56A与56B之间的漏电流。
根据本公开的一实施例,半导体装置的形成方法包含形成长形栅极,以及形成与长形栅极的第一侧壁和第二侧壁接触的第一间隙物和第二间隙物。半导体装置的形成方法也包含使用第一蚀刻步骤和第二蚀刻步骤将长形栅极分离为第一栅极部分和第二栅极部分。半导体装置的形成方法还包含在第一栅极部分与第二栅极部分之间形成栅极隔离插塞,其中栅极隔离插塞的长度大于第一栅极部分或第二栅极部分的长度。栅极隔离插塞与第一栅极部分或第二栅极部分的长度差至少为一些实施例中,栅极隔离插塞可包含椭圆的形状、正方形的形状或柠檬的形状,且可包含规则中央部分、第一不规则末端部分和第二不规则末端部分。第一栅极部分和第二栅极部分可包含金属栅极部分或虚设栅极部分。第一间隙物和第二间隙物可包含介电间隙物,且栅极隔离插塞可包含介电栅极隔离插塞。
根据本公开的另一实施例,半导体装置的形成方法包含形成长形栅极,包含第一长度。半导体装置的形成方法也包含形成接触长形栅极的第一间隙物和第二间隙物,以及蚀刻长形栅极以形成第一开口,其中第一开口将长形栅极分离为第一栅极部分和第二栅极部分。半导体装置的形成方法还包含蚀刻长形栅极以形成大于第一开口的第二开口,第二开口包含大于第一长度的第二长度,以及在第二开口内沉积介电层。蚀刻长形栅极以形成第一开口可包含干式蚀刻方法。蚀刻长形栅极以形成第二开口可包含湿式蚀刻方法或干式蚀刻方法。第二长度与第一长度之差至少为
根据本公开的又一实施例,半导体装置包含长形栅极,包含第一长度,以及栅极隔离插塞,将长形栅极区分为第一栅极部分和第二栅极部分,其中栅极隔离插塞包含大于第一长度的第二长度。半导体装置也包含第一鳍式场效晶体管,包含第一半导体鳍,其中第一栅极部分横跨第一半导体鳍。半导体装置还包含第二鳍式场效晶体管,包含第二半导体鳍,其中第二栅极部分横跨第二半导体鳍。第二长度和第一长度之差至少为栅极隔离插塞的形状可包含椭圆的形状、正方形的形状,或者包含具有规则中央部分、第一不规则末端部分和第二不规则末端部分的形状。
以上概述数个实施例或范例的特征,以便本领域技术人员可以更理解本公开实施例的观点。本领域技术人员应该理解,他们能以本公开实施例为基础,设计或修改其他工艺和结构,以达到与在此介绍的实施例或范例相同的目的和/或优势。本领域技术人员也应该理解到,此类等效的结构并无悖离本公开实施例的构思与范围,且他们能在不违背本公开实施例的构思和范围之下,做各式各样的改变、取代和替换。
Claims (20)
1.一种半导体装置的形成方法,包括:
形成一长形栅极;
形成与该长形栅极的一第一侧壁和一第二侧壁接触的一第一间隙物和一第二间隙物;
使用一第一蚀刻步骤和一第二蚀刻步骤将该长形栅极分离为一第一栅极部分和一第二栅极部分;以及
在该第一栅极部分与该第二栅极部分之间形成一栅极隔离插塞,其中该栅极隔离插塞的长度大于该第一栅极部分或该第二栅极部分的长度且小于该第一间隙物的外侧壁与该第二间隙物的外侧壁之间的距离。
3.如权利要求1所述的半导体装置的形成方法,其中该栅极隔离插塞包括一椭圆的形状。
4.如权利要求1所述的半导体装置的形成方法,其中该栅极隔离插塞包括一正方形的形状。
5.如权利要求1所述的半导体装置的形成方法,其中该栅极隔离插塞包括一柠檬的形状。
6.如权利要求1所述的半导体装置的形成方法,其中该栅极隔离插塞的形状包括一规则中央部分、一第一不规则末端部分和一第二不规则末端部分。
7.如权利要求1所述的半导体装置的形成方法,其中该第一栅极部分和该第二栅极部分包括金属栅极部分。
8.如权利要求1所述的半导体装置的形成方法,其中该第一栅极部分和该第二栅极部分包括虚设栅极部分。
9.如权利要求1所述的半导体装置的形成方法,其中该第一间隙物和该第二间隙物包括介电间隙物。
10.如权利要求1所述的半导体装置的形成方法,其中该栅极隔离插塞包括介电栅极隔离插塞。
11.一种半导体装置的形成方法,包括:
形成一长形栅极,其包括一第一长度;
形成接触该长形栅极的一第一间隙物和一第二间隙物;
蚀刻该长形栅极以形成一第一开口,其中该第一开口将该长形栅极分离为一第一栅极部分和一第二栅极部分;
蚀刻该长形栅极以形成大于该第一开口的一第二开口,该第二开口包括大于该第一长度的一第二长度,其中该第二长度小于该第一间隙物的外侧壁与该第二间隙物的外侧壁之间的距离;以及
在该第二开口内沉积一介电层。
12.如权利要求11所述的半导体装置的形成方法,其中蚀刻该长形栅极以形成该第一开口包括一干式蚀刻方法。
13.如权利要求11所述的半导体装置的形成方法,其中蚀刻该长形栅极以形成该第二开口包括一湿式蚀刻方法。
14.如权利要求11所述的半导体装置的形成方法,其中蚀刻该长形栅极以形成该第二开口包括一干式蚀刻方法。
16.一种半导体装置,包括:
一长形栅极,其包括一第一长度;
一栅极隔离插塞,将该长形栅极区分为一第一栅极部分和一第二栅极部分,其中该栅极隔离插塞包括大于该第一长度的一第二长度;
一第一鳍式场效晶体管,包括一第一半导体鳍,其中该第一栅极部分横跨该第一半导体鳍;
一第二鳍式场效晶体管,包括一第二半导体鳍,其中该第二栅极部分横跨该第二半导体鳍;以及
一第一间隙物与一第二间隙物,分别位于该长形栅极的两侧,其中该第一间隙物的外侧壁与该第二间隙物的外侧壁之间的距离大于该第二长度。
18.如权利要求16所述的半导体装置,其中该栅极隔离插塞的形状包括一椭圆的形状。
19.如权利要求16所述的半导体装置,其中该栅极隔离插塞的形状包括一正方形的形状。
20.如权利要求16所述的半导体装置,其中该栅极隔离插塞的形状包括一规则中央部分、一第一不规则末端部分和一第二不规则末端部分。
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US10468527B2 (en) | 2017-11-15 | 2019-11-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal gate structure and methods of fabricating thereof |
US11031290B2 (en) | 2017-11-30 | 2021-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure with cutting depth control and method for fabricating the same |
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US20210202321A1 (en) * | 2019-12-30 | 2021-07-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | High Voltage Devices |
US11521969B2 (en) | 2020-01-29 | 2022-12-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Isolation structures for semiconductor devices |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1379444A (zh) * | 2001-03-29 | 2002-11-13 | 株式会社东芝 | 半导体器件的制造方法和半导体器件 |
CN103855221A (zh) * | 2012-12-03 | 2014-06-11 | 英飞凌科技股份有限公司 | 半导体器件和制造半导体器件的方法 |
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US8487378B2 (en) | 2011-01-21 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Non-uniform channel junction-less transistor |
US8887106B2 (en) | 2011-12-28 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process |
US9991375B2 (en) * | 2012-05-30 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate electrode of a semiconductor device |
US8729634B2 (en) | 2012-06-15 | 2014-05-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with high mobility and strain channel |
US9041125B2 (en) | 2013-03-11 | 2015-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin shape for fin field-effect transistors and method of forming |
US8826213B1 (en) | 2013-03-11 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Parasitic capacitance extraction for FinFETs |
US8943455B2 (en) | 2013-03-12 | 2015-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for layout verification for polysilicon cell edge structures in FinFET standard cells |
KR102208063B1 (ko) * | 2014-04-22 | 2021-01-27 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US9312388B2 (en) * | 2014-05-01 | 2016-04-12 | Globalfoundries Inc. | Methods of forming epitaxial semiconductor material in trenches located above the source and drain regions of a semiconductor device |
KR102217246B1 (ko) * | 2014-11-12 | 2021-02-18 | 삼성전자주식회사 | 집적회로 소자 및 그 제조 방법 |
US9773912B2 (en) | 2016-01-28 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and manufacturing method thereof |
US9704754B1 (en) | 2016-09-22 | 2017-07-11 | International Business Machines Corporation | Self-aligned spacer for cut-last transistor fabrication |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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