CN109714024A - A kind of CMOS relaxation oscillator circuit of temperature-compensating - Google Patents
A kind of CMOS relaxation oscillator circuit of temperature-compensating Download PDFInfo
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Abstract
The invention discloses a kind of CMOS relaxation oscillator circuits of temperature-compensating, including RC charge and discharge electric network, hysteresis comparator, PD control module, buffer, two divided-frequency；RC charge and discharge electric network includes first resistor, second resistance, capacitor, and buffer includes the first phase inverter, the second phase inverter；One end of first resistor is connect with the input terminal of the output end of PD control module, buffer, the other end is connect with the input terminal of capacitor, hysteresis comparator, the input terminal connection of the input terminal, two divided-frequency of the output end and the second phase inverter of first phase inverter of one end of second resistance and capacitance connection, the other end and buffer；The output end of hysteresis comparator is connect with the first input end of PD control module；The output end of PD control module and the input terminal of buffer connect, and the second input terminal of PD control module is connect with external control signal PD；The output end of buffer and the input terminal of two divided-frequency connect.The present invention is improved in temperature-compensating and power supply sensitivity, reduces leakage current when circuit shutdown.
Description
Technical field
The present invention relates to a kind of pierce circuit more particularly to a kind of for stablizing output frequency in certain temperature range
Relaxation pierce circuit, belongs to integrated circuit fields.
Background technique
Oscillator is widely used in integrated circuit the purpose of to provide clock signal, there is some application requirement oscillators
It can keep stablizing in big temperature change, and have harsh requirement to power consumption and area simultaneously.Such as in wireless sensor
In network (WSNs), each node is made of Centimeter Level even grade equipment, these small equipment will be environment, biology doctor
It learns, military and industrial application provides ubiquitous sensor platform.Wirelessly communicate power consumption, size and the frequency stability of clock
It is the main problem of grade wireless sensor network (WSNs).
Crystal oscillator is usually applied to wireless sensor network since the inhibiting effect changed to PVT is good
(WSNs) in, but the size of crystal oscillator is to hinder a huge obstacle of node miniaturization trend, and crystal oscillation
The frequency robustness of device is to sacrifice power consumption as cost.
Summary of the invention
The purpose of the present invention is overcoming and solve the above problems, a kind of relaxation oscillator circuit of temperature-compensating is provided,
Under the premise of reducing power consumption and area, while providing enough precision.
The technical solution adopted by the invention is as follows: a kind of CMOS relaxation oscillator circuit of temperature-compensating, the circuit packet
Include RC charge and discharge electric network, hysteresis comparator, PD control module, buffer, two divided-frequency；Wherein, RC charge and discharge electric network includes first
Resistance, second resistance, capacitor, buffer include the first phase inverter, the second phase inverter；One end of first resistor and PD control module
Output end, buffer input terminal be connected, the other end of first resistor is connected with the input terminal of capacitor, hysteresis comparator
Connect, one end of second resistance is connected with capacitor, the output end of the first phase inverter of the other end and buffer of second resistance with
And the input terminal of second input terminal of phase inverter, two divided-frequency is connected；The of the output end of hysteresis comparator and PD control module
One input terminal is connected；The output end of PD control module and the input terminal of buffer are connected with each other, and the second of PD control module is defeated
Enter end to be connected with external control signal PD；The output end of buffer is connected with the input terminal of two divided-frequency；The sluggishness is relatively
Device, PD control module, all metal-oxide-semiconductors in buffer are connected using cascade system.
Further, first resistor is the p-type resistance (non-silicidated) with low negative temperature coefficient, N-type polycrystalline silicon
Resistance (non-silicidated) or high resistance polysilicon resistance, second resistance are that have low negative temperature coefficient p-type resistance (non-silicon
Change) or diffusion resistance with positive temperature coefficient.
Further, capacitor is by zero capacitance, first capacitor, first switch, the second capacitor, second switch, third electricity
Appearance, third switch, the 4th capacitor, the 4th switch composition 4 capacitors trim array, first resistor and zero capacitance one end, the
The input terminal of one end, hysteresis comparator that one end of one switch, one end of second switch, one end of third switch, the 4th switch
It is connected, the other end of first switch is connected with one end of first capacitor, and the one of the other end of second switch and the second capacitor
End is connected, and the other end of third switch is connected with one end of third capacitor, the 4th other end and the 4th capacitor switched
One end is connected, the other end of the zero capacitance other end and first capacitor, the other end of the second capacitor, third capacitor it is another
End, the other end of the 4th capacitor, second resistance one end be connected.
Further, the hysteresis comparator contains 3rd resistor, the 4th resistance, the first p-type metal-oxide-semiconductor, the second p-type MOS
Pipe, third p-type metal-oxide-semiconductor, the 4th p-type metal-oxide-semiconductor, the 5th p-type metal-oxide-semiconductor, the 6th p-type metal-oxide-semiconductor, the first N-type metal-oxide-semiconductor, the second N-type
Metal-oxide-semiconductor, third N-type metal-oxide-semiconductor, the 4th N-type metal-oxide-semiconductor, the 5th N-type metal-oxide-semiconductor, the 6th N-type metal-oxide-semiconductor, 3rd resistor and the 4th resistance
Ratio control RC charge and discharge network output signal overturning level point, and export low and high level signal and be given to PD control module
First input end；Hysteresis comparator circuit connects in the following manner: one end of 3rd resistor and the output end of RC charge and discharge electric network
Be connected, one end of the other end of 3rd resistor and the 4th resistance, the grid of the first p-type metal-oxide-semiconductor, the second p-type metal-oxide-semiconductor grid
Pole, the grid of third p-type metal-oxide-semiconductor, the grid of the first N-type metal-oxide-semiconductor, the grid of the second N-type metal-oxide-semiconductor, third N-type metal-oxide-semiconductor grid
Pole is connected, and the source electrode of the first p-type metal-oxide-semiconductor is controlled to a power supply, the drain electrode of the first p-type metal-oxide-semiconductor and the source of the second p-type metal-oxide-semiconductor
Pole is connected, and the drain electrode of the second p-type metal-oxide-semiconductor is connected with the source electrode of third p-type metal-oxide-semiconductor, the drain electrode of third p-type metal-oxide-semiconductor and the
The drain electrode of one N-type metal-oxide-semiconductor, the grid of the 4th p-type metal-oxide-semiconductor, the grid of the 5th p-type metal-oxide-semiconductor, the grid of the 6th p-type metal-oxide-semiconductor are connected
It connects, the source electrode of the first N-type metal-oxide-semiconductor is connected with the drain electrode of the second N-type metal-oxide-semiconductor, the source electrode and third N-type of the second N-type metal-oxide-semiconductor
The drain electrode of metal-oxide-semiconductor is connected, and the drain electrode of third N-type metal-oxide-semiconductor is connected to the ground, and the source electrode of the 4th p-type metal-oxide-semiconductor is connected with power supply
It connects, the drain electrode of the 4th p-type metal-oxide-semiconductor is connected with the source electrode of the 5th p-type metal-oxide-semiconductor, the drain electrode and the 6th p-type of the 5th p-type metal-oxide-semiconductor
The source electrode of metal-oxide-semiconductor is connected, drain electrode and the drain electrode of the 4th N-type metal-oxide-semiconductor, the input terminal phase of PD control module of the 6th p-type metal-oxide-semiconductor
Connection, the source electrode of the 4th N-type metal-oxide-semiconductor are connected with the drain electrode of the 5th N-type metal-oxide-semiconductor, the source electrode and the 6th N-type of the 5th N-type metal-oxide-semiconductor
The drain electrode of metal-oxide-semiconductor is connected, and the source electrode of the 6th N-type metal-oxide-semiconductor is connected to the ground.
Further, the PD control module includes the 7th to the tenth p-type metal-oxide-semiconductor, the 7th to the 8th N-type metal-oxide-semiconductor composition
NAND gate, whether worked by external signal PD control modular circuit；PD control modular circuit connects in the following manner: the 7th P
The grid of type metal-oxide-semiconductor is connected with the grid of the 8th p-type metal-oxide-semiconductor, the grid of the 7th N-type metal-oxide-semiconductor, the output end of hysteresis comparator
It connects, the source electrode of the 7th p-type metal-oxide-semiconductor is controlled to a power supply, and the drain electrode of the 7th p-type metal-oxide-semiconductor is connected with the source electrode of the 8th p-type metal-oxide-semiconductor
It connects, grid and the grid of the tenth p-type metal-oxide-semiconductor, the grid of the 8th N-type metal-oxide-semiconductor, the external control signal PD phase of the 9th p-type metal-oxide-semiconductor
Connection, the source electrode of the 9th p-type metal-oxide-semiconductor are controlled to a power supply, the drain electrode and the source electrode phase of the tenth p-type metal-oxide-semiconductor of the 9th p-type metal-oxide-semiconductor
Connection, the 8th p-type metal-oxide-semiconductor drain electrode with the drain electrode of the tenth p-type metal-oxide-semiconductor, the drain electrode of the 7th N-type metal-oxide-semiconductor, buffer input terminal
It is connected, the source electrode of the 7th N-type metal-oxide-semiconductor is connected with the drain electrode of the 8th N-type metal-oxide-semiconductor, source electrode and the ground phase of the 8th N-type metal-oxide-semiconductor
Connection.
Further, the buffer contains the 11st to the 14th p-type metal-oxide-semiconductor, the 9th to the 12nd N-type metal-oxide-semiconductor group
At shaping of the buffer to the output end waveform signal to PD control module, and to the charge and discharge time of RC charge and discharge electric network
It is controlled；Buffer circuits connect in the following manner: the grid of the grid of the 11st p-type metal-oxide-semiconductor and the 12nd p-type metal-oxide-semiconductor,
Grid, the grid of the tenth N-type metal-oxide-semiconductor, the output end of PD control module of 9th N-type metal-oxide-semiconductor are connected, the 11st p-type metal-oxide-semiconductor
Source electrode be controlled to a power supply, the drain electrode of the 11st p-type metal-oxide-semiconductor is connected with the source electrode of the 12nd p-type metal-oxide-semiconductor, the 12nd p-type
The drain electrode of metal-oxide-semiconductor and the drain electrode of the 9th N-type metal-oxide-semiconductor, the grid of the 13rd p-type metal-oxide-semiconductor, the grid of the 14th p-type metal-oxide-semiconductor, the
The other end of the second resistance of the grid of 11 N-type metal-oxide-semiconductors, the grid of the 12nd N-type metal-oxide-semiconductor, RC charge and discharge electric network is connected,
The source electrode of 9th N-type metal-oxide-semiconductor is connected with the drain electrode of the tenth N-type metal-oxide-semiconductor, and the source electrode of the tenth N-type metal-oxide-semiconductor is connected to the ground, the
The source electrode of 13 p-type metal-oxide-semiconductors is controlled to a power supply, and the drain electrode of the 13rd p-type metal-oxide-semiconductor is connected with the source electrode of the 14th p-type metal-oxide-semiconductor
It connects, the drain electrode of the 14th p-type metal-oxide-semiconductor is connected with the input terminal of the drain electrode of the 11st N-type metal-oxide-semiconductor, two divided-frequency, the 11st N-type
The source electrode of metal-oxide-semiconductor is connected with the drain electrode of the 12nd N-type metal-oxide-semiconductor, and the source electrode of the 12nd N-type metal-oxide-semiconductor is connected to the ground.
Further, the two divided-frequency includes first liang of input nand gate, second liang of input nand gate, first to fourth biography
Defeated door, third to hex inverter carry out two divided-frequency, the frequency of output duty cycle 50% to the output end frequency signal of buffer
Signal；Frequency-halving circuit connects in the following manner: one end of the first input end of first liang of input nand gate and the first transmission gate,
One end of second transmission gate is connected, and the second input terminal of first liang of input nand gate is connected with external control signal RESET,
The output end of first liang of input nand gate is connected with one end of the input terminal of third phase inverter, third transmission gate, third reverse phase
The output end of device is connected with the other end of the first transmission gate, one end of the other end of third transmission gate and the 4th transmission gate,
The input terminal of four phase inverters is connected, the first input end of the output end of the 4th phase inverter and second liang of input nand gate, the 5th
The input terminal of phase inverter is connected, and the second input terminal of second liang of input nand gate is connected with external control signal RESET, the
The output end of two liang of input nand gates is connected with the other end of the 4th transmission gate, the output end of the 5th phase inverter and the second transmission
The other end of door, the output end of two divided-frequency (5) are connected, the p-type of the grid of the N-type MOS of the first transmission gate, the second transmission gate
The grid of MOS, the grid of the N-type MOS of third transmission gate, the 4th transmission gate p-type MOS grid, hex inverter input
End, buffer (4) output end be connected, the grid of the p-type MOS of the first transmission gate, the N-type MOS of the second transmission gate grid,
The grid of p-type MOS, the grid of N-type MOS of the 4th transmission gate, the output end of hex inverter of third transmission gate are connected.
Compared with prior art, the present invention have the effect that (1) present invention in using improved RC charge and discharge electric network
It is improved in temperature-compensating and power supply sensitivity；(2) hysteresis comparator in the present invention, PD control module, buffering
Device uses Self-cascading structure, reduces leakage current when circuit shutdown；(3) circuit size is small.
Detailed description of the invention
Fig. 1 is the basic framework figure of relaxation oscillator circuit in the present embodiment；
Fig. 2 is the circuit structure diagram of relaxation oscillator circuit in the present embodiment；
Fig. 3 is the circuit diagram of RC charge and discharge electric network in the present embodiment；
Fig. 4 is the signal timing diagram of relaxation oscillator circuit in the present embodiment；
Fig. 5 is the simulation data figure of relaxation oscillator circuit in the present embodiment.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to implementation of the invention
Example describes in detail.
The CMOS relaxation oscillator circuit of one of the present embodiment temperature-compensating, general frame figure is as shown in Figure 1, packet
Include RC charge and discharge electric network 1, hysteresis comparator 2, PD control module 3, buffer 4, two divided-frequency 5；Wherein, RC charge and discharge electric network includes
First resistor R1, second resistance R2, capacitor C, buffer 4 include the first phase inverter INV1, the second phase inverter INV2；First resistor
One end of R1 is connected with the input terminal of the output end of PD control module 3, buffer 4, the other end and capacitor of first resistor R1
C, the input terminal of hysteresis comparator 2 is connected, and one end of second resistance R2 is connected with capacitor C, the other end of second resistance R2
With the input terminal phase of the input terminal of the output end of the first phase inverter INV1 of buffer 4 and the second phase inverter INV2, two divided-frequency 5
Connection；The output end of hysteresis comparator 2 is connected with the first input end of PD control module 3；The output end of PD control module 3 with
The input terminal of buffer 4 is connected with each other, and the second input terminal of PD control module 3 is connected with external control signal PD；Buffer 4
Output end be connected with the input terminal of two divided-frequency 5；It is the hysteresis comparator 2, PD control module 3, all in buffer 4
Metal-oxide-semiconductor is connected using cascade system.
First resistor R1 is that have p-type resistance (non-silicidated), the N-type polycrystalline silicon resistance of low negative temperature coefficient (non-
Silication) or high resistance polysilicon resistance, second resistance R2 is that have low negative temperature coefficient p-type resistance (non-silicidated) or tool
There is the diffusion resistance of positive temperature coefficient, is influenced by temperature with reducing the charge and discharge time.
Particular circuit configurations figure such as Fig. 2 in embodiment.Capacitor is by zero capacitance C0, first capacitor C1, first switch
S1, the second capacitor C2, second switch S2, third capacitor C3, third switch S3, the 4th capacitor C4, the 4th switch S4 composition 4
Capacitor trims array, first resistor R1 and the one end zero capacitance C0, one end of first switch S1, one end of second switch S2,
One end of three switch S3, one end of the 4th switch S4, the input terminal of hysteresis comparator are connected, the other end of first switch S1 with
One end of first capacitor C1 is connected, and the other end of second switch S2 is connected with one end of the second capacitor C2, third switch S3
The other end be connected with one end of third capacitor C3, the other end of the 4th switch S4 is connected with one end of the 4th capacitor C4,
The zero capacitance C0 other end and the other end of first capacitor C1, the other end of the second capacitor C2, the other end of third capacitor C3, the
The other end of four capacitor C4, one end of second resistance R2 are connected.
The charge and discharge electric network that first resistor R1, second resistance R2, the 0th to the 4th capacitor form is relative to traditional RC net
Network increases a zero point, and increased step, which is rung, will do it temperature-compensating, zero capacitance C0, first capacitor C1, first switch S1,
Second capacitor C2, second switch S2, third capacitor C3, third switch S3, the 4th capacitor C4, the 4th switch S4 form 4 capacitors
Array is trimmed as trimming to technique change, trims rear frequency variation within ± 6%.
As shown in figure 3, the transfer function of RC charge and discharge electric network are as follows:
As t=0, the amplitude of step isTime constant later is (R2+R1) C, when the temperature increases, rank
Saltus degree reduces, and time constant increases, so the whole charge and discharge time keeps constant.
The hysteresis comparator contains 3rd resistor R3, the 4th resistance R4, the first p-type metal-oxide-semiconductor PM1, the second p-type metal-oxide-semiconductor
PM2, third p-type metal-oxide-semiconductor PM3, the 4th p-type metal-oxide-semiconductor PM4, the 5th p-type metal-oxide-semiconductor PM5, the 6th p-type metal-oxide-semiconductor PM6, the first N-type
Metal-oxide-semiconductor NM1, the second N-type metal-oxide-semiconductor NM2, third N-type metal-oxide-semiconductor NM3, the 4th N-type metal-oxide-semiconductor NM4, the 5th N-type metal-oxide-semiconductor NM5, the 6th
The overturning level point of the Ratio control RC charge and discharge network output signal of N-type metal-oxide-semiconductor NM6,3rd resistor R3 and the 4th resistance R4,
And export the first input end that low and high level signal is given to PD control module.
As shown in Fig. 2, the intermediate level point of hysteresis comparator p-type metal-oxide-semiconductor and N-type MOS are set as in the present embodiment
0.5VDD, R4=2 × R3, then the high tumble level point VH of hysteresis comparator and low overturning level point VL be respectively 0.75VDD and
0.25VDD。
Function of the RC charge and discharge electric network in time-domain are as follows:
0.75VDD is substituted into obtain:
T obtains temperature T derivation:
Wherein, TC1, TC2, R1nom, R2nomIt is the temperature coefficient of the temperature coefficient of R1, R2, the resistance of R1 at room temperature respectively
Value, the resistance value of R2 at room temperature.In the case where knowing R1 and R2 temperature coefficient, its resistance value can be respectively obtained by formula.
Simulation result shown in fig. 5 can be brought by making appropriate choice to the resistance value of R1 and R2, can from figure
Out, under Typical process conditions, the rate-adaptive pacemaker of relaxation oscillator circuit is insensitive to the variation of temperature.As shown in figure 5, temperature
Coefficient is about 40ppm/ DEG C, can be calculated according to the following formula:
TCFOUT=(1.2133-1.2045)/1.21/190 × 1000000=38.3ppm/ DEG C of ≈ 40ppm/ DEG C.
Hysteresis comparator circuit connects in the following manner: the output end phase of one end of 3rd resistor R3 and RC charge and discharge electric network
Connection, the other end of 3rd resistor R3 and one end of the 4th resistance R4, the grid of the first p-type metal-oxide-semiconductor PM1, the second p-type metal-oxide-semiconductor
The grid of PM2, the grid of third p-type metal-oxide-semiconductor PM3, the grid of the first N-type metal-oxide-semiconductor NM1, the second N-type metal-oxide-semiconductor NM2 grid,
The grid of third N-type metal-oxide-semiconductor NM3 is connected, and the source electrode of the first p-type metal-oxide-semiconductor PM1 is controlled to a power supply, the first p-type metal-oxide-semiconductor PM1
Drain electrode be connected with the source electrode of the second p-type metal-oxide-semiconductor PM2, the drain electrode of the second p-type metal-oxide-semiconductor PM2 and third p-type metal-oxide-semiconductor PM3's
Source electrode is connected, drain electrode and the drain electrode of the first N-type metal-oxide-semiconductor NM1, the grid of the 4th p-type metal-oxide-semiconductor PM4 of third p-type metal-oxide-semiconductor PM3
Pole, the grid of the 5th p-type metal-oxide-semiconductor PM5, the 6th p-type metal-oxide-semiconductor PM6 grid be connected, the source electrode of the first N-type metal-oxide-semiconductor NM1 with
The drain electrode of second N-type metal-oxide-semiconductor NM2 is connected, and the source electrode of the second N-type metal-oxide-semiconductor NM2 is connected with the drain electrode of third N-type metal-oxide-semiconductor NM3
It connects, the drain electrode of third N-type metal-oxide-semiconductor NM3 is connected to the ground, and the source electrode of the 4th p-type metal-oxide-semiconductor PM4 is controlled to a power supply, the 4th p-type
The drain electrode of metal-oxide-semiconductor PM4 is connected with the source electrode of the 5th p-type metal-oxide-semiconductor PM5, the drain electrode of the 5th p-type metal-oxide-semiconductor PM5 and the 6th p-type MOS
The source electrode of pipe PM6 is connected, the drain electrode of the 6th p-type metal-oxide-semiconductor PM6 and the drain electrode of the 4th N-type metal-oxide-semiconductor NM4, PD control module it is defeated
Enter end to be connected, the source electrode of the 4th N-type metal-oxide-semiconductor NM4 is connected with the drain electrode of the 5th N-type metal-oxide-semiconductor NM5, the 5th N-type metal-oxide-semiconductor NM5
Source electrode be connected with the drain electrode of the 6th N-type metal-oxide-semiconductor NM6, the source electrode of the 6th N-type metal-oxide-semiconductor NM6 is connected to the ground.
As shown in Fig. 2, the PD control module includes the 7th to the tenth p-type metal-oxide-semiconductor, the 7th to the 8th N-type metal-oxide-semiconductor composition
NAND gate, whether worked by external signal PD control modular circuit；PD control modular circuit connects in the following manner: the 7th P
The grid of type metal-oxide-semiconductor is connected with the grid of the 8th p-type metal-oxide-semiconductor, the grid of the 7th N-type metal-oxide-semiconductor, the output end of hysteresis comparator
It connects, the source electrode of the 7th p-type metal-oxide-semiconductor is controlled to a power supply, and the drain electrode of the 7th p-type metal-oxide-semiconductor is connected with the source electrode of the 8th p-type metal-oxide-semiconductor
It connects, grid and the grid of the tenth p-type metal-oxide-semiconductor, the grid of the 8th N-type metal-oxide-semiconductor, the external control signal PD phase of the 9th p-type metal-oxide-semiconductor
Connection, the source electrode of the 9th p-type metal-oxide-semiconductor are controlled to a power supply, the drain electrode and the source electrode phase of the tenth p-type metal-oxide-semiconductor of the 9th p-type metal-oxide-semiconductor
Connection, the 8th p-type metal-oxide-semiconductor drain electrode with the drain electrode of the tenth p-type metal-oxide-semiconductor, the drain electrode of the 7th N-type metal-oxide-semiconductor, buffer input terminal
It is connected, the source electrode of the 7th N-type metal-oxide-semiconductor is connected with the drain electrode of the 8th N-type metal-oxide-semiconductor, source electrode and the ground phase of the 8th N-type metal-oxide-semiconductor
Connection.
As shown in Fig. 2, the buffer contains the 11st to the 14th p-type metal-oxide-semiconductor, the 9th to the 12nd N-type metal-oxide-semiconductor group
At shaping of the buffer to the output end waveform signal to PD control module, and to the charge and discharge time of RC charge and discharge electric network
It is controlled；Buffer circuits connect in the following manner: the grid of the grid of the 11st p-type metal-oxide-semiconductor and the 12nd p-type metal-oxide-semiconductor,
Grid, the grid of the tenth N-type metal-oxide-semiconductor, the output end of PD control module of 9th N-type metal-oxide-semiconductor are connected, the 11st p-type metal-oxide-semiconductor
Source electrode be controlled to a power supply, the drain electrode of the 11st p-type metal-oxide-semiconductor is connected with the source electrode of the 12nd p-type metal-oxide-semiconductor, the 12nd p-type
The drain electrode of metal-oxide-semiconductor and the drain electrode of the 9th N-type metal-oxide-semiconductor, the grid of the 13rd p-type metal-oxide-semiconductor, the grid of the 14th p-type metal-oxide-semiconductor, the
The grid of 11 N-type metal-oxide-semiconductors, the grid of the 12nd N-type metal-oxide-semiconductor, RC charge and discharge electric network second resistance R2 the other end be connected
It connecing, the source electrode of the 9th N-type metal-oxide-semiconductor is connected with the drain electrode of the tenth N-type metal-oxide-semiconductor, and the source electrode of the tenth N-type metal-oxide-semiconductor is connected to the ground,
The source electrode of 13rd p-type metal-oxide-semiconductor is controlled to a power supply, the drain electrode and the source electrode phase of the 14th p-type metal-oxide-semiconductor of the 13rd p-type metal-oxide-semiconductor
Connection, the drain electrode of the 14th p-type metal-oxide-semiconductor are connected with the input terminal of the drain electrode of the 11st N-type metal-oxide-semiconductor, two divided-frequency, the 11st N
The source electrode of type metal-oxide-semiconductor is connected with the drain electrode of the 12nd N-type metal-oxide-semiconductor, and the source electrode of the 12nd N-type metal-oxide-semiconductor is connected to the ground.
As shown in Fig. 2, the two divided-frequency includes first liang of input nand gate, second liang of input nand gate, first to fourth
Transmission gate, third to hex inverter carry out two divided-frequency, the frequency of output duty cycle 50% to the output end frequency signal of buffer
Rate signal；Fig. 4 shows the signal timing diagram of relaxation oscillator circuit in the present embodiment.
Frequency-halving circuit connects in the following manner: the one of the first input end of first liang of input nand gate and the first transmission gate
End, the second transmission gate one end be connected, the second input terminal of first liang of input nand gate is connected with external control signal RESET
It connects, the output end of first liang of input nand gate is connected with one end of the input terminal of third phase inverter, third transmission gate, and third is anti-
The output end of phase device is connected with the other end of the first transmission gate, one end of the other end of third transmission gate and the 4th transmission gate,
The input terminal of 4th phase inverter is connected, the first input end of the output end of the 4th phase inverter and second liang of input nand gate,
The input terminal of five phase inverters is connected, and the second input terminal of second liang of input nand gate is connected with external control signal RESET,
The output end of second liang of input nand gate is connected with the other end of the 4th transmission gate, and the output end of the 5th phase inverter and second passes
The other end of defeated door, the output end of two divided-frequency 5 are connected, the p-type of the grid of the N-type MOS of the first transmission gate, the second transmission gate
The grid of MOS, the grid of the N-type MOS of third transmission gate, the 4th transmission gate p-type MOS grid, hex inverter input
End, buffer 4 output end be connected, the grid of the p-type MOS of the first transmission gate, the grid of the N-type MOS of the second transmission gate, the
The grid of p-type MOS, the grid of N-type MOS of the 4th transmission gate, the output end of hex inverter of three transmission gates are connected.
The content being not described in detail in this specification belongs to the prior art well known to professional and technical personnel in the field.
Above embodiments are only a preferred embodiment of the present invention, but simultaneously all circuit set-up modes of non-present invention
All, all equivalents done within spirit of the invention range all will be within the scope of the present invention.
Claims (7)
1. a kind of CMOS relaxation oscillator circuit of temperature-compensating, it is characterised in that: the circuit includes RC charge and discharge electric network
(1), hysteresis comparator (2), PD control module (3), buffer (4), two divided-frequency (5)；Wherein, RC charge and discharge electric network (1) includes
First resistor, second resistance, capacitor, buffer (4) include the first phase inverter, the second phase inverter；One end of first resistor and PD
The output end of control module (3), the input terminal of buffer (4) are connected, the other end and capacitor, hysteresis comparator of first resistor
(2) input terminal is connected, and one end of second resistance is connected with capacitor, and the of the other end of second resistance and buffer (4)
The input terminal of the output end of one phase inverter and the second phase inverter, two divided-frequency (5) input terminal be connected；Hysteresis comparator (2)
Output end be connected with the first input end of PD control module (3)；The output end of PD control module (3) and buffer (4)
Input terminal is connected with each other, and the second input terminal of PD control module (3) is connected with external control signal PD；Buffer (4) it is defeated
Outlet is connected with the input terminal of two divided-frequency (5)；The hysteresis comparator (2), PD control module (3), the institute in buffer (4)
There is metal-oxide-semiconductor to connect using cascade system.
2. a kind of CMOS relaxation oscillator circuit of temperature-compensating as described in claim 1, it is characterised in that: first resistor is
P-type resistance (non-silicidated), N-type polycrystalline silicon resistance (non-silicidated) or high resistance polysilicon electricity with low negative temperature coefficient
Resistance, second resistance are that have low negative temperature coefficient p-type resistance (non-silicidated) or the diffusion electricity with positive temperature coefficient
Resistance.
3. a kind of CMOS relaxation oscillator circuit of temperature-compensating as described in claim 1, it is characterised in that: capacitor is by the
Zero capacitance, first capacitor, first switch, the second capacitor, second switch, third capacitor, third switch, the 4th capacitor, the 4th open
4 capacitors for closing composition trim array, first resistor and zero capacitance one end, one end of first switch, second switch one end,
Third switch one end, the 4th switch one end, hysteresis comparator (2) input terminal be connected, the other end of first switch with
One end of first capacitor is connected, and the other end of second switch is connected with one end of the second capacitor, the other end of third switch
It is connected with one end of third capacitor, the other end of the 4th switch is connected with one end of the 4th capacitor, the zero capacitance other end
With the other end of first capacitor, the other end of the second capacitor, the other end of third capacitor, the other end of the 4th capacitor, the second electricity
One end of resistance is connected.
4. a kind of CMOS relaxation oscillator circuit of temperature-compensating as described in claim 1, it is characterised in that: the sluggishness ratio
Contain 3rd resistor, the 4th resistance, the first p-type metal-oxide-semiconductor, the second p-type metal-oxide-semiconductor, third p-type metal-oxide-semiconductor, the 4th p-type compared with device (2)
Metal-oxide-semiconductor, the 5th p-type metal-oxide-semiconductor, the 6th p-type metal-oxide-semiconductor, the first N-type metal-oxide-semiconductor, the second N-type metal-oxide-semiconductor, third N-type metal-oxide-semiconductor, the 4th N
Type metal-oxide-semiconductor, the 5th N-type metal-oxide-semiconductor, the 6th N-type metal-oxide-semiconductor, the Ratio control RC charge and discharge electric network (1) of 3rd resistor and the 4th resistance
The overturning level point of output signal, and export the first input end that low and high level signal is given to PD control module (3)；Sluggishness is relatively
Device (2) circuit connects in the following manner: one end of 3rd resistor is connected with the output end of RC charge and discharge electric network (1), third electricity
One end of the other end of resistance and the 4th resistance, the grid of the first p-type metal-oxide-semiconductor, the grid of the second p-type metal-oxide-semiconductor, third p-type metal-oxide-semiconductor
Grid, the grid of the first N-type metal-oxide-semiconductor, the grid of the second N-type metal-oxide-semiconductor, third N-type metal-oxide-semiconductor grid be connected, the first p-type
The source electrode of metal-oxide-semiconductor is controlled to a power supply, and the drain electrode of the first p-type metal-oxide-semiconductor is connected with the source electrode of the second p-type metal-oxide-semiconductor, the second p-type
The drain electrode of metal-oxide-semiconductor is connected with the source electrode of third p-type metal-oxide-semiconductor, the drain electrode of third p-type metal-oxide-semiconductor to drain with the first N-type metal-oxide-semiconductor,
Grid, the grid of the 5th p-type metal-oxide-semiconductor, the grid of the 6th p-type metal-oxide-semiconductor of 4th p-type metal-oxide-semiconductor are connected, the first N-type metal-oxide-semiconductor
Source electrode is connected with the drain electrode of the second N-type metal-oxide-semiconductor, and the source electrode of the second N-type metal-oxide-semiconductor is connected with the drain electrode of third N-type metal-oxide-semiconductor,
The drain electrode of third N-type metal-oxide-semiconductor is connected to the ground, and the source electrode of the 4th p-type metal-oxide-semiconductor is controlled to a power supply, the leakage of the 4th p-type metal-oxide-semiconductor
Pole is connected with the source electrode of the 5th p-type metal-oxide-semiconductor, and the drain electrode of the 5th p-type metal-oxide-semiconductor is connected with the source electrode of the 6th p-type metal-oxide-semiconductor, the
The drain electrode of six p-type metal-oxide-semiconductors is connected with the input terminal of the drain electrode of the 4th N-type metal-oxide-semiconductor, PD control module (3), the 4th N-type metal-oxide-semiconductor
Source electrode be connected with the drain electrode of the 5th N-type metal-oxide-semiconductor, the source electrode of the 5th N-type metal-oxide-semiconductor is connected with the drain electrode of the 6th N-type metal-oxide-semiconductor
It connects, the source electrode of the 6th N-type metal-oxide-semiconductor is connected to the ground.
5. a kind of CMOS relaxation oscillator circuit of temperature-compensating as described in claim 1, it is characterised in that: the PD control
Module (3) includes the NAND gate of the 7th to the tenth p-type metal-oxide-semiconductor, the 7th to the 8th N-type metal-oxide-semiconductor composition, by external signal PD control
Whether modular circuit works；PD control module (3) circuit connects in the following manner: the grid and the 8th p-type of the 7th p-type metal-oxide-semiconductor
The grid of metal-oxide-semiconductor, the grid of the 7th N-type metal-oxide-semiconductor, hysteresis comparator (2) output end be connected, the source electrode of the 7th p-type metal-oxide-semiconductor
It is controlled to a power supply, the drain electrode of the 7th p-type metal-oxide-semiconductor is connected with the source electrode of the 8th p-type metal-oxide-semiconductor, the grid of the 9th p-type metal-oxide-semiconductor
It is connected with grid, the external control signal PD of the grid of the tenth p-type metal-oxide-semiconductor, the 8th N-type metal-oxide-semiconductor, the source of the 9th p-type metal-oxide-semiconductor
Pole is controlled to a power supply, and the drain electrode of the 9th p-type metal-oxide-semiconductor is connected with the source electrode of the tenth p-type metal-oxide-semiconductor, the leakage of the 8th p-type metal-oxide-semiconductor
Pole is connected with the input terminal of the drain electrode of the tenth p-type metal-oxide-semiconductor, the drain electrode of the 7th N-type metal-oxide-semiconductor, buffer (4), the 7th N-type MOS
The source electrode of pipe is connected with the drain electrode of the 8th N-type metal-oxide-semiconductor, and the source electrode of the 8th N-type metal-oxide-semiconductor is connected to the ground.
6. a kind of CMOS relaxation oscillator circuit of temperature-compensating as described in claim 1, it is characterised in that: the buffer
(4) contain the 11st to the 14th p-type metal-oxide-semiconductor, the buffer of the 9th to the 12nd N-type metal-oxide-semiconductor composition is to PD control mould
The shaping of the output end waveform signal of block (3), and the charge and discharge time of RC charge and discharge electric network (1) is controlled；Buffer (4)
Circuit connects in the following manner: the grid of the grid of the 11st p-type metal-oxide-semiconductor and the 12nd p-type metal-oxide-semiconductor, the 9th N-type metal-oxide-semiconductor
Grid, the grid of the tenth N-type metal-oxide-semiconductor, PD control module (3) output end be connected, the source electrode of the 11st p-type metal-oxide-semiconductor and electricity
Source is connected, and the drain electrode of the 11st p-type metal-oxide-semiconductor is connected with the source electrode of the 12nd p-type metal-oxide-semiconductor, the leakage of the 12nd p-type metal-oxide-semiconductor
Pole and the drain electrode of the 9th N-type metal-oxide-semiconductor, the grid of the 13rd p-type metal-oxide-semiconductor, the 14th p-type metal-oxide-semiconductor grid, the 11st N-type MOS
The other end of the second resistance of the grid of pipe, the grid of the 12nd N-type metal-oxide-semiconductor, RC charge and discharge electric network (1) is connected, the 9th N-type
The source electrode of metal-oxide-semiconductor is connected with the drain electrode of the tenth N-type metal-oxide-semiconductor, and the source electrode of the tenth N-type metal-oxide-semiconductor is connected to the ground, the 13rd p-type
The source electrode of metal-oxide-semiconductor is controlled to a power supply, and the drain electrode of the 13rd p-type metal-oxide-semiconductor is connected with the source electrode of the 14th p-type metal-oxide-semiconductor, and the tenth
The drain electrode of four p-type metal-oxide-semiconductors is connected with the input terminal of the drain electrode of the 11st N-type metal-oxide-semiconductor, two divided-frequency (5), the 11st N-type metal-oxide-semiconductor
Source electrode be connected with the drain electrode of the 12nd N-type metal-oxide-semiconductor, the source electrode of the 12nd N-type metal-oxide-semiconductor is connected to the ground.
7. a kind of CMOS relaxation oscillator circuit of temperature-compensating as described in claim 1, it is characterised in that: the two divided-frequency
(5) right including first liang of input nand gate, second liang of input nand gate, first to fourth transmission gate, third to hex inverter
The output end frequency signal of buffer (4) carries out two divided-frequency, the frequency signal of output duty cycle 50%；Two divided-frequency (5) circuit press with
Under type connection: the first input end of first liang of input nand gate and one end of the first transmission gate, one end phase of the second transmission gate
Connection, the second input terminal of first liang of input nand gate is connected with external control signal RESET, first liang of input nand gate
Output end is connected with one end of the input terminal of third phase inverter, third transmission gate, and the output end of third phase inverter and first passes
The other end of defeated door is connected, the other end of third transmission gate and one end of the 4th transmission gate, the input terminal phase of the 4th phase inverter
Connection, the output end of the 4th phase inverter are connected with the input terminal of the first input end of second liang of input nand gate, the 5th phase inverter
Connect, the second input terminal of second liang of input nand gate is connected with external control signal RESET, second liang of input nand gate it is defeated
Outlet is connected with the other end of the 4th transmission gate, the output end of the 5th phase inverter and the other end, the two divided-frequency of the second transmission gate
(5) output end is connected, the grid of the N-type MOS of the first transmission gate, the grid of the p-type MOS of the second transmission gate, third transmission
The output of the grid of N-type MOS, the grid of p-type MOS of the 4th transmission gate, the input terminal of hex inverter, buffer (4) of door
End is connected, the grid of the p-type MOS of the first transmission gate, the grid of the N-type MOS of the second transmission gate, third transmission gate p-type MOS
Grid, the 4th transmission gate the grid of N-type MOS, the output end of hex inverter be connected.
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