CN109713044B - Thin film transistor, manufacturing method and display panel - Google Patents
Thin film transistor, manufacturing method and display panel Download PDFInfo
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- CN109713044B CN109713044B CN201811587013.8A CN201811587013A CN109713044B CN 109713044 B CN109713044 B CN 109713044B CN 201811587013 A CN201811587013 A CN 201811587013A CN 109713044 B CN109713044 B CN 109713044B
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Abstract
The invention discloses a thin film transistor, a manufacturing method thereof and a display panel. The thin film transistor comprises a substrate, a first metal layer, a first insulating layer, an active layer, a doping layer and a second metal layer, wherein the first metal layer is arranged on the substrate; the first insulating layer is arranged on the first metal layer; the active layer is disposed on the first insulating layer; the doping layer is arranged on the active layer; the second metal layer is arranged on the doped layer; the doping layers comprise sub-doping layers with the number of N, the number of N is an odd number larger than or equal to three, the sub-doping layers are arranged in a stacked mode, the sub-doping layer in the middle is used as a symmetry axis, and the doping concentrations of the sub-doping layers corresponding to the two sides of the symmetry axis are equal. In the sub-doping layers of the odd layers which are more than or equal to three, the doping layer with the symmetrical structure has the best leakage reduction effect.
Description
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor, a manufacturing method and a display panel.
Background
A Thin Film Transistor (TFT) may include a field effect transistor manufactured using a semiconductor thin film formed on an insulating support substrate. Like other field effect transistors, the TFT has three terminal gates, drains, and sources, and is used to perform a switching operation by adjusting a voltage applied to the gate to turn on or off a current flowing between the source and the drain. TFTs may be used in sensors, memory devices, optical devices, as switching units of flat panel display devices and as driving units of flat panel display devices.
The TFT may generate a large leakage current, which affects the display effect.
Disclosure of Invention
The invention aims to provide a thin film transistor for reducing TFT electric leakage, a manufacturing method thereof and a display panel.
The invention discloses a thin film transistor, which comprises a substrate, a first metal layer, a first insulating layer, an active layer, a doping layer and a second metal layer, wherein the first metal layer is arranged on the substrate; the first insulating layer is arranged on the first metal layer; the active layer is disposed on the first insulating layer; the doping layer is arranged on the active layer; the second metal layer is arranged on the doped layer; the doping layers comprise sub-doping layers with the number of N, the number of N is an odd number larger than or equal to three, the sub-doping layers are arranged in a stacked mode, the sub-doping layer in the middle is used as a symmetry axis, and the doping concentrations of the sub-doping layers corresponding to the two sides of the symmetry axis are equal.
Optionally, the doping substances of the doping layer are phosphine and silane, and the doping concentration is a gas flow ratio of the phosphine to the silane.
Optionally, the gas flow ratio of phosphine to silane is between 0.32 and 4.1.
Optionally, the doped layers include a first sub-doped layer, a second sub-doped layer and a third sub-doped layer, the first sub-doped layer is disposed on the active layer, the second sub-doped layer is disposed on the first sub-doped layer, the third sub-doped layer is disposed on the second sub-doped layer, the second metal layer is disposed on the third sub-doped layer, and the doping concentrations of the first sub-doped layer and the third sub-doped layer are equal.
Optionally, the doping concentrations include a first doping concentration and a second doping concentration, the doping concentrations of the first sub-doping layer and the third sub-doping layer are the first doping concentration, and the doping concentration of the second sub-doping layer is the second doping concentration.
Optionally, the doped layers include a first sub-doped layer, a second sub-doped layer, a third sub-doped layer, a fourth sub-doped layer, and a fifth sub-doped layer, the first sub-doped layer is disposed on the active layer, the second sub-doped layer is disposed on the first sub-doped layer, the third sub-doped layer is disposed on the second sub-doped layer, the fourth sub-doped layer is disposed on the third sub-doped layer, the fifth sub-doped layer is disposed on the fourth sub-doped layer, the second metal layer is disposed on the fifth sub-doped layer, the doping concentrations of the first sub-doped layer and the fifth sub-doped layer are equal, and the doping concentrations of the second sub-doped layer and the fourth sub-doped layer are equal.
Optionally, the doping concentration of the sub-doping layers corresponding to the two sides of the symmetry axis is distributed uniformly.
The invention also discloses a manufacturing method of the thin film transistor, which comprises the following steps:
depositing a first metal layer on a substrate;
depositing a first insulating layer on the first metal layer;
depositing an active layer on the first insulating layer;
depositing a doping layer on the active layer; and
depositing a second metal layer on the doped layer;
the doping layers comprise N sub-doping layers, N is an odd number larger than or equal to three, the sub-doping layers are arranged in a stacked mode, the middle sub-doping layer is taken as a symmetry axis, and the doping concentrations of the sub-doping layers corresponding to the two sides of the symmetry axis are equal.
Optionally, the step of depositing a doping layer on the active layer includes:
controlling the gas flow ratio of phosphine and silane between 0.32 and 4.1;
and depositing phosphine and silane on the active layer by using a chemical vapor deposition method to form the doping layer.
The invention also discloses a display panel comprising the thin film transistor.
For the scheme that the doping layer is of an asymmetric structure, the sub-doping layer of the middle layer is taken as a symmetry axis, the doping concentrations of the sub-doping layers corresponding to two sides of the symmetry axis are equal, and the doping layer is called as a symmetric structure; through experimental comparison, the leakage reduction effect of the symmetrical structure is the best in the odd-numbered doped layers more than or equal to three.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
FIG. 1 is a schematic diagram of an exemplary display panel of the present invention;
FIG. 2 is a schematic diagram of an exemplary display panel of the present invention after burn-in aging;
FIG. 3 is a schematic illustration of an exemplary normal image display of the present invention;
FIG. 4 is a schematic illustration of an exemplary image sticking highlight of the present invention;
FIG. 5 is a schematic illustration of an exemplary doped layer of the present invention in a single layer structure;
FIG. 6 is a schematic diagram of an exemplary doped layer of the present invention in a two-layer configuration;
FIG. 7 is a schematic diagram of a four-layer structure of an exemplary doped layer of the present invention;
FIG. 8 is a schematic diagram of the leakage current magnitude of different doped layer structures under a-6V gate voltage for a TFT according to one embodiment of the present invention;
FIG. 9 is a schematic diagram of a three-layer symmetric structure of a doped layer according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a five-layer symmetric structure of a doped layer according to an embodiment of the invention;
fig. 11 is a schematic diagram of a method for fabricating a thin film transistor according to an embodiment of the invention;
FIG. 12 is a schematic illustration of a step of depositing a doped layer on an active layer in accordance with an embodiment of the present invention;
FIG. 13 is a schematic representation of a TFT cross-sectional energy band of a doped layer with a gate voltage of 0 volts in accordance with an embodiment of the present invention;
FIG. 14 is a schematic representation of a cross-sectional energy band of a doped layer TFT with a gate voltage less than 0V in accordance with an embodiment of the present invention;
FIG. 15 is a schematic diagram of the TFT cross-sectional energy band of a three-layer symmetric doped layer with a gate voltage of 0V in accordance with an embodiment of the present invention;
FIG. 16 is a schematic diagram of the cross-sectional energy band of a three-layer symmetric doped TFT with a gate voltage less than 0V in accordance with an embodiment of the present invention;
FIG. 17 is a schematic representation of a cross-sectional energy band of a four-doped layer TFT with a gate voltage less than 0V in accordance with an embodiment of the present invention;
FIG. 18 is a schematic diagram of a band broken line for a doped layer TFT with a gate voltage less than 0V in accordance with an embodiment of the present invention;
FIG. 19 is a schematic diagram of the band broken lines of a tri-doped TFT with a gate voltage less than 0V in accordance with one embodiment of the present invention;
FIG. 20 is a schematic diagram of the four doped layer TFT band break lines with a gate voltage less than 0V in accordance with one embodiment of the present invention;
fig. 21 is a schematic diagram of a display panel according to an embodiment of the invention.
100, a display panel; 200. a thin film transistor; 210. a substrate; 220. a first metal layer; 230. a first insulating layer; 240. an active layer; 250. doping layer; 251. a first sub-doped layer; 252. a second sub-doped layer; 253. a third sub-doped layer; 254. a fourth sub-doped layer; 255. a fifth sub-doped layer; 260. a second metal layer; 261. a source electrode; 262. a drain electrode; 270. a channel.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
As shown in fig. 1 to 7, a Back Channel Etching (BCE) structure is generally used in the amorphous silicon thin film transistor 200(TFT) process, and the structure has low cost and simple process; but the TFT leakage is large due to poor interface state of the back channel etch. The 4 masks are easy to generate larger tails due to the special etching process, and are more likely to cause image residue of the display panel.
The invention will be further elucidated with reference to the drawings and alternative embodiments.
As shown in fig. 8 to 10, an embodiment of the present invention discloses a thin film transistor 200, which includes a substrate 210, a first metal layer 220, a first insulating layer 230, an active layer 240, a doped layer 250, and a second metal layer 260, wherein the first metal layer 220 is disposed on the substrate 210; a first insulating layer 230 is disposed on the first metal layer 220; the active layer 240 is disposed on the first insulating layer 230; the doping layer 250 is disposed on the active layer 240; the second metal layer 260 is disposed on the doped layer 250; the doping layer 250 includes N sub-doping layers, where N is an odd number greater than or equal to three, the sub-doping layers are stacked, the middle sub-doping layer is used as a symmetry axis, and the doping concentrations of the sub-doping layers corresponding to both sides of the symmetry axis are equal.
The sub-doping layer of the middle layer is taken as a symmetry axis, the doping concentrations of the corresponding sub-doping layers at two sides of the symmetry axis are equal, and the doping layer 250 is called as a symmetric structure; if the doping concentrations of the sub-doping layers corresponding to the two sides of the symmetry axis are not equal, the structure of the doping layer 250 is called an asymmetric structure. FIG. 8 and Table 1.1 show the comparison of leakage current of the doped layer 250 with three-layer structure and the doped layers 250 with single-layer and four-layer structure, where the ordinate is the magnitude of leakage current under-6V of gate voltage, the abscissa is the number and concentration of sub-doped layers, the points on the curve correspond to the leakage current values under-6V of the doped layers 250 with different structures on the abscissa, respectively, where the point A corresponds to the structure of the single-layer doped layer 250, the point B corresponds to the structure of the four-layer doped layer 250, the point C/D/E corresponds to the structure of the three-layer doped layer 250, the point D corresponds to N +/AH/N + as a symmetric structure, the point C corresponds to N-/AH/N + as an asymmetric structure, the point E corresponds to N-/N/N + as another asymmetric structure, and the doping concentrations of the layers are sequentially increased. From data analysis in the figure, it can be known that the higher the number of doped layers 250 is, the smaller the leakage current is, and in the same three-layer structure, the leakage current corresponding to point D is the smallest and very close to the value of point B. By contrast, the leakage reduction effect of the symmetric structure is the best in the odd-numbered layer of the doped layer 250 of three or more. The three-layer structure of the doped layer 250 is taken as an example for illustration, and the other layers of the doped layer 250 also conform to the rule, and are not described herein again.
TABLE 1.1
In one embodiment, the doping materials of the doped layer 250 are phosphine and silane, and the doping concentration is the gas flow ratio of phosphine to silane.
When the active layer 240 is directly in contact with the second metal layer 260, the resistance at the contact surface is high, and in order to reduce the resistance, Phosphine (PH) is used on the surface of the active layer 2403) And Silane (SiH)4) Deposition to form the N-type doped layer 250, the formation of the N-type doped layer 250 requires the provision of pentavalent atoms, such as phosphorus atoms, to dope the layer250 can provide more electrons and reduce contact resistance, while the gas flow ratio of phosphine to silane is called the doping concentration, with higher doping concentrations having a higher phosphine fraction.
In one embodiment, the phosphine to silane gas flow ratio is between 0.32 and 4.1, the doped layer 250 has a thickness greater than 400 angstroms, and the sub-doped layer has a uniform doping concentration profile per layer.
The good film quality is obtained, the electric leakage can be further reduced by increasing the film thickness of the doping layer 250, the doping concentration of the sub-doping layer is uniformly distributed, the symmetrical effect of the concentration of the sub-doping layer can be improved, and the effect of reducing the leakage current is improved.
Fig. 9 shows three layers of doped layers of symmetrical structure. The doping layers 250 include a first sub-doping layer 251, a second sub-doping layer 252, and a third sub-doping layer 253, the first sub-doping layer 251 is disposed on the active layer 240, the second sub-doping layer 252 is disposed on the first sub-doping layer 251, the third sub-doping layer 253 is disposed on the second sub-doping layer 252, the second metal layer 260 is disposed on the third sub-doping layer 253, and the first sub-doping layer 251 and the third sub-doping layer 253 have the same doping concentration.
In the three-layer symmetrical structure, the doping concentrations of the first sub-doping layer 251 and the third sub-doping layer 253 are equal, the doping concentration of the second sub-doping layer 252 is greater than or less than the doping concentration of the first sub-doping layer 251, or the doping concentration of the second sub-doping layer 252 is 0, that is, the second sub-doping layer is not doped, a potential barrier is formed on the contact surface of the first sub-doping layer 251 and the larger the potential barrier, the less easily leakage electrons pass through the potential barrier.
In one embodiment, in the symmetric structure with three sub-doped layers, the doping concentrations include a first doping concentration N + and a second doping concentration AH, and the doping concentrations of the first sub-doped layer 251 and the third sub-doped layer 253 are N +, the doping concentration of the second sub-doped layer 252 is AH, and the value of AH is equal to 0.
In the three sub-doping layers, the leakage reduction effect by comparing the symmetric structure is better than that of the asymmetric structure, wherein the doping layer 250 with the doping concentration of AH is an amorphous silicon layer, and a larger potential barrier can be generated between the amorphous silicon layer and the doping layer 250, so that the leakage reduction effect is enhanced.
Taking the three-layer symmetrical structure of the doping layer 250 as an example, the doping concentrations of the sub-doping layers are arranged as follows, the doping concentrations further include a third doping concentration N and a fourth doping concentration N-, the numerical value and magnitude relationship of the doping concentrations are N + > N- > AH, the doping concentrations of the first sub-doping layer 251 and the third sub-doping layer 253 are N +, and the doping concentration of the second sub-doping layer 252 is N; optionally, the doping concentration of the first sub-doping layer 251 and the third sub-doping layer 253 is N —, and the doping concentration of the second sub-doping layer 252 is AH; optionally, the doping concentrations of the first sub-doping layer 251 and the third sub-doping layer 253 are N, and the doping concentration of the second sub-doping layer 252 is AH; optionally, the doping concentrations of the first sub-doping layer 251 and the third sub-doping layer 253 are N-, and the doping concentration of the second sub-doping layer 252 is N.
Fig. 10 shows five layers of doped layers in a symmetrical configuration. The doping layers 250 include a first sub-doping layer 251, a second sub-doping layer 252, a third sub-doping layer 253, a fourth sub-doping layer 254, and a fifth sub-doping layer 255, the first sub-doping layer 251 is disposed on the active layer 240, the second sub-doping layer 252 is disposed on the first sub-doping layer 251, the third sub-doping layer 253 is disposed on the second sub-doping layer 252, the fourth sub-doping layer 254 is disposed on the third sub-doping layer 253, the fifth sub-doping layer 255 is disposed on the fourth sub-doping layer 254, the second metal layer 260 is disposed on the fifth sub-doping layer 255, the first sub-doping layer 251 and the fifth sub-doping layer 255 have the same doping concentration, and the second sub-doping layer 252 and the fourth sub-doping layer 254 have the same doping concentration.
The N represents the sub-doping layer as one layer, the N-/AH/N +, N +/AH/N + and N-/N/N + represent the sub-doping layers as three layers, the N-/N +/N + + represent the sub-doping layers as four layers, the sub-doping layer as one layer has the largest leakage current, the sub-doping layer as the second of the three layers has the smallest leakage current of the four layers, and the distribution of the four sub-doping layers is not a symmetrical structure.
Taking the five-layer symmetric structure of the doping layer 250 as an example, the doping concentrations of the sub-doping layers are arranged as follows, the doping concentrations further include a fifth doping concentration N + + and a sixth doping concentration N- -, the numerical value and magnitude relationship of the doping concentrations are N + + > N- - > AH, the doping concentrations of the first sub-doping layer 251 and the fifth sub-doping layer 255 are N- -, the doping concentrations of the second sub-doping layer 252 and the fourth sub-doping layer 254 are N- -, and the doping concentration of the third sub-doping layer 253 is AH; optionally, the doping concentrations of the first sub-doping layer 251 and the fifth sub-doping layer 255 are N +, the doping concentrations of the second sub-doping layer 252 and the fourth sub-doping layer 254 are N + +, and the doping concentration of the third sub-doping layer 253 is AH; optionally, the doping concentration of the first sub-doping layer 251 and the fifth sub-doping layer 255 is N-, the doping concentration of the second sub-doping layer 252 and the fourth sub-doping layer 254 is N-, and the doping concentration of the third sub-doping layer 253 is N; optionally, the doping concentrations of the first sub-doping layer 251 and the fifth sub-doping layer 255 are N +, the doping concentrations of the second sub-doping layer 252 and the fourth sub-doping layer 254 are N + +, and the doping concentration of the third sub-doping layer 253 is N; optionally, the doping concentration of the first sub-doping layer 251 and the fifth sub-doping layer 255 is N-, the doping concentration of the second sub-doping layer 252 and the fourth sub-doping layer 254 is N-, and the doping concentration of the third sub-doping layer 253 is AH; optionally, the doping concentrations of the first sub-doping layer 251 and the fifth sub-doping layer 255 are N + +, the doping concentrations of the second sub-doping layer 252 and the fourth sub-doping layer 254 are N +, and the doping concentration of the third sub-doping layer 253 is AH; optionally, the doping concentration of the first sub-doping layer 251 and the fifth sub-doping layer 255 is N-, the doping concentration of the second sub-doping layer 252 and the fourth sub-doping layer 254 is N-, and the doping concentration of the third sub-doping layer 253 is N; optionally, the doping concentrations of the first sub-doping layer 251 and the fifth sub-doping layer 255 are N + +, the doping concentrations of the second sub-doping layer 252 and the fourth sub-doping layer 254 are N +, and the doping concentration of the third sub-doping layer 253 is N.
In one embodiment, the active layer 240 includes amorphous silicon, the thin film transistor 200 includes a channel 270, the first metal layer 220 includes a gate, the channel 270 divides the second metal layer 260 into two parts, a source electrode 261 and a drain electrode 262 are formed, the channel 270 divides the doped layer 250 into two parts, and the source electrode 261 and the drain electrode 262 are respectively disposed on the doped layer 250 divided into two parts.
The amorphous silicon may be prepared by glow discharge decomposition of silane, the channel 270 is formed by etching, the channel 270 separates the second metal layer 260 into two parts forming the source and drain poles, and a gate voltage induces the channel 270 in the amorphous silicon and conducts under source and drain bias.
As shown in fig. 11, an embodiment of the present application discloses a method for manufacturing a thin film transistor, which includes the steps of:
s111, depositing a first metal layer on the substrate;
s112, depositing a first insulating layer on the first metal layer;
s113, depositing an active layer on the first insulating layer;
s114, depositing a doping layer on the active layer; and
s115, depositing a second metal layer on the doped layer;
the doping layers comprise N sub-doping layers, N is an odd number larger than or equal to three, the sub-doping layers are arranged in a stacked mode, the middle sub-doping layer is used as a symmetry axis, and the doping concentrations of the sub-doping layers corresponding to the two sides of the symmetry axis are equal.
The method comprises the steps of depositing a first metal layer on a substrate to form a grid electrode, providing a grid voltage, depositing an insulating protection layer on the grid electrode to isolate the grid electrode, depositing an active layer on the first insulating layer, wherein the active layer is a semiconductor amorphous silicon layer and provides carrier conduction current for a thin film transistor, the second metal layer forms a source electrode and a drain electrode, and a doping layer is arranged between the second metal layer and the active layer to reduce contact resistance between the active layer and the second metal layer.
As shown in fig. 12, the step of depositing the doping layer on the active layer includes:
s121, controlling the gas flow ratio of phosphine to silane to be between 0.32 and 4.1;
and S122, depositing phosphine and silane on the active layer by using a chemical vapor deposition method to form the doping layer.
The gas flow ratio of phosphine and silane is called doping concentration, and no matter the symmetrical structure of several sub-doping layers, the concentration range of the sub-doping layer in each layer is between 0.32 and 4.1, so that better film quality can be obtained, and electric leakage can be reduced.
The fermi levels of any two contacting solids must be equal, when the two materials are in contact, electrons will flow from the high fermi level material to the low fermi level material to equilibrium, the fermi level of the doped layer 250 is higher than that of the amorphous silicon layer, at their interface, electrons will flow from the doped layer 250 to the amorphous silicon layer, and near the interface, the doped layer 250 side will be positive and the amorphous silicon layer side will be negative, so an electric field will be formed near the interface, this field will be called the barrier region, the energy required to pass through the barrier region will be called the barrier, the larger the barrier the smaller the leakage,
fig. 13 is a TFT cross-sectional energy band diagram with a gate voltage of 0 v, fig. 14 is a TFT cross-sectional energy band diagram with a gate voltage of less than 0 v, fig. 18 is a TFT energy band line diagram with a gate voltage of less than 0 v, and the doped layer 250 in fig. 13, 14 and 18 is a layer with a doping concentration of N; FIG. 15 is a TFT cross-sectional energy band diagram with a gate voltage of 0V, FIG. 16 is a TFT cross-sectional energy band diagram with a gate voltage of less than 0V, FIG. 19 is a TFT energy band line diagram with a gate voltage of less than 0V, and the doped layers 250 in FIGS. 15, 16 and 19 are all three layers with a doping concentration profile of N +/AH/N +; FIG. 17 is a cross-sectional energy band diagram of a TFT having a gate voltage of less than 0V, FIG. 19 is a line graph of the energy band of the TFT having a gate voltage of less than 0V, and the doping layer 250 in FIGS. 17 and 19 is four-layered and has a doping concentration profile of N + +/N +/N-/N- -.
Where Ec is a relatively high energy state in the band system, electrons greater than or equal to this energy state will be unbound by a single atom in the material, thereby forming leakage, Ev is a relatively low energy state in the band system, and electrons less than or equal to this energy state are bound by a single atom in the material; ef is the average energy of all electrons in this band system; in the doped layer 250 and the amorphous silicon, the energy state of electron stability can only be more than or equal to Ec or less than or equal to Ev, the energy state between Ec and Ev is unstable, Eb is the barrier energy barrier in the energy band system, i.e. the barrier which electrons need to pass through to form an unstable state, the larger the barrier is, the more difficult the electrons need to pass through, the smaller the leakage current is formed, so the larger Eb is, the smaller the leakage current is in the TFT.
As shown in fig. 21, as another embodiment of the present invention, a display panel 100 including the thin film transistor 200 according to any of the above embodiments is disclosed.
It should be noted that, the limitations of the steps involved in the present disclosure are not considered to limit the order of the steps without affecting the implementation of the specific embodiments, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all should be considered to belong to the protection scope of the present disclosure.
The technical solution of the present invention can be widely applied to various display panels, such as a Twisted Nematic (TN) display panel, an In-Plane Switching (IPS) display panel, a Vertical Alignment (VA) display panel, and a Multi-Domain Vertical Alignment (MVA) display panel, and of course, other types of display panels, such as an Organic Light-Emitting Diode (OLED) display panel, can be applied to the above solution.
The foregoing is a more detailed description of the invention in connection with specific alternative embodiments, and the practice of the invention should not be construed as limited to those descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (3)
1. A thin film transistor, comprising:
a substrate;
a first metal layer disposed on the substrate;
a first insulating layer disposed on the first metal layer;
an active layer disposed on the first insulating layer;
a doping layer disposed on the active layer; and
the second metal layer is arranged on the doping layer;
the doping layers comprise sub-doping layers, the sub-doping layers are arranged in a stacked mode, the middle sub-doping layer is taken as a symmetry axis, and the doping concentrations of the sub-doping layers corresponding to the two sides of the symmetry axis are equal; the doping concentration of the sub-doping layers corresponding to the two sides of the symmetry axis is distributed uniformly;
doping substances of the doping layer are phosphine and silane, and the doping concentration is the gas flow ratio of the phosphine to the silane; a gas flow ratio of the phosphine to the silane is between 0.32 and 4.1; the doped layers comprise a first sub-doped layer, a second sub-doped layer and a third sub-doped layer, the first sub-doped layer is arranged on the active layer, the second sub-doped layer is arranged on the first sub-doped layer, the third sub-doped layer is arranged on the second sub-doped layer, the second metal layer is arranged on the third sub-doped layer, and the doping concentration of the first sub-doped layer is equal to that of the third sub-doped layer; the doping concentration comprises a first doping concentration and a second doping concentration, the doping concentration of the first sub-doping layer and the doping concentration of the third sub-doping layer are the first doping concentration, and the doping concentration of the second sub-doping layer is the second doping concentration; the first doping concentration is less than the doping concentration of the second sub-doping layer.
2. A display panel comprising the thin film transistor according to claim 1.
3. A method for manufacturing a thin film transistor is characterized by comprising the following steps:
depositing a first metal layer on a substrate;
depositing a first insulating layer on the first metal layer;
depositing an active layer on the first insulating layer;
depositing a doping layer on the active layer; and
depositing a second metal layer on the doped layer;
the doping layers comprise sub-doping layers, the sub-doping layers are arranged in a stacked mode, the middle sub-doping layer is taken as a symmetry axis, and the doping concentrations of the sub-doping layers corresponding to the two sides of the symmetry axis are equal; the doping concentration of the sub-doping layers corresponding to the two sides of the symmetry axis is distributed uniformly;
the step of depositing a doped layer on the active layer comprises:
controlling the gas flow ratio of phosphine and silane between 0.32 and 4.1;
depositing phosphine and silane on the active layer by using a chemical vapor deposition method to form the doping layer; the doped layers comprise a first sub-doped layer, a second sub-doped layer and a third sub-doped layer, the first sub-doped layer is arranged on the active layer, the second sub-doped layer is arranged on the first sub-doped layer, the third sub-doped layer is arranged on the second sub-doped layer, the second metal layer is arranged on the third sub-doped layer, and the doping concentration of the first sub-doped layer is equal to that of the third sub-doped layer; the doping concentration comprises a first doping concentration and a second doping concentration, the doping concentration of the first sub-doping layer and the doping concentration of the third sub-doping layer are the first doping concentration, and the doping concentration of the second sub-doping layer is the second doping concentration; the first doping concentration is less than the doping concentration of the second sub-doping layer.
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| CN201811587013.8A CN109713044B (en) | 2018-12-25 | 2018-12-25 | Thin film transistor, manufacturing method and display panel |
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| CN201811587013.8A CN109713044B (en) | 2018-12-25 | 2018-12-25 | Thin film transistor, manufacturing method and display panel |
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| CN109713044B true CN109713044B (en) | 2021-04-13 |
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