CN109713044A - A kind of thin film transistor (TFT) and production method and display panel - Google Patents
A kind of thin film transistor (TFT) and production method and display panel Download PDFInfo
- Publication number
- CN109713044A CN109713044A CN201811587013.8A CN201811587013A CN109713044A CN 109713044 A CN109713044 A CN 109713044A CN 201811587013 A CN201811587013 A CN 201811587013A CN 109713044 A CN109713044 A CN 109713044A
- Authority
- CN
- China
- Prior art keywords
- doped layer
- sub
- layer
- doping concentration
- doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention discloses a kind of thin film transistor (TFT) and production method and display panels.Thin film transistor (TFT) includes substrate, the first metal layer, the first insulating layer, active layer, doped layer and second metal layer, wherein the first metal layer setting is over the substrate；First insulating layer is arranged on the first metal layer；The active layer setting is on the first insulating layer；The doped layer setting is on the active layer；The second metal layer is arranged on the doped layer；The doped layer includes the sub- doped layer that quantity is N, and the N is the odd number more than or equal to three, and the sub- doped layer is stacked, and using intermediate sub- doped layer as symmetry axis, the corresponding sub- doped layer doping concentration in symmetry axis two sides is equal.In the sub- doped layer of the odd-level more than or equal to three, the doped layer drop electric leakage effect of symmetrical structure is best.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of thin film transistor (TFT) and production method and display panels.
Background technique
Thin film transistor (TFT) (TFT) may include the field-effect manufactured using the semiconductive thin film being formed in insulating supporting substrate
Transistor.As other field effect transistors, there are three end grid, drain electrode and source electrodes for TFT tool, are applied to grid by adjusting
Voltage switch operation is executed using TFT with electric current that on or off flows between source electrode and drain electrode.TFT can be used in
Sensor, memory device, in optical device, the switch unit as panel display apparatus and the driving as panel display apparatus
Unit.
TFT can generate biggish leakage current, influence display effect.
Summary of the invention
The object of the present invention is to provide a kind of a kind of thin film transistor (TFT) of reduction TFT electric leakage and production method and display surfaces
Plate.
The invention discloses a kind of thin film transistor (TFT)s, including substrate, the first metal layer, the first insulating layer, active layer, doping
Layer and second metal layer, wherein the first metal layer setting is over the substrate；First insulating layer setting is described the
On one metal layer；The active layer setting is on the first insulating layer；The doped layer setting is on the active layer；It is described
Second metal layer is arranged on the doped layer；The doped layer includes the sub- doped layer that quantity is N, and the N is to be greater than or wait
In three odd number, the sub- doped layer is stacked, using intermediate sub- doped layer as symmetry axis, the corresponding son in symmetry axis two sides
Doped layer doping concentration is equal.
Optionally, the dopant of the doped layer be hydrogen phosphide and silane, the doping concentration be the hydrogen phosphide with
The gas flow ratio of the silane.
Optionally, the gas flow ratio of the hydrogen phosphide and the silane is between 0.32 to 4.1.
Optionally, the doped layer include the first sub- doped layer, the second sub- doped layer and the sub- doped layer of third, described first
On the active layer, the second sub- doped layer is arranged on the described first sub- doped layer, the third for sub- doped layer setting
Sub- doped layer is arranged on the described second sub- doped layer, and the second metal layer is arranged on the sub- doped layer of the third, described
First sub- doped layer is equal with the sub- doped layer doping concentration of the third.
Optionally, the doping concentration include the first doping concentration and the second doping concentration, the first sub- doped layer with
The doping concentration of the sub- doped layer of third is the first doping concentration, and the doping concentration of the second sub- doped layer is the second doping
Concentration.
Optionally, the doped layer is mixed including the first sub- doped layer, the second sub- doped layer, the sub- doped layer of third, the 4th son
Diamicton and the 5th sub- doped layer, on the active layer, the second sub- doped layer setting exists for the first sub- doped layer setting
On the first sub- doped layer, the sub- doped layer of third is arranged on the described second sub- doped layer, the 4th sub- doped layer
It is arranged on the sub- doped layer of the third, the 5th sub- doped layer is arranged on the 4th sub- doped layer, second gold medal
Belonging to layer to be arranged on the 5th sub- doped layer, the first sub- doped layer is equal with the described 5th sub- doped layer doping concentration,
The second sub- doped layer is equal with the described 4th sub- doped layer doping concentration.
Optionally, the corresponding sub- doped layer doping concentration distribution in the symmetry axis two sides is uniform.
The invention also discloses a kind of production method of thin film transistor (TFT), step includes:
The first metal layer is deposited on substrate；
The first insulating layer is deposited on the first metal layer；
Active layer is deposited on the first insulating layer；
Doped layer is deposited on active layer；And
The depositing second metal layer on doped layer；
Wherein, doped layer includes the sub- doped layer that quantity is N, and the N is the odd number more than or equal to three, the sub- doping
Layer stackup setting, using intermediate sub- doped layer as symmetry axis, the corresponding sub- doped layer doping concentration in symmetry axis two sides is equal.
Optionally, described to include: the step of depositing doped layer on active layer
The gas flow ratio of control hydrogen phosphide and silane is between 0.32 to 4.1；
The doped layer on hydrogen phosphide and silane-deposited to active layer, will be formed with chemical vapour deposition technique.
The invention also discloses a kind of display panels, including thin film transistor (TFT) described above.
Relative to doped layer be unsymmetric structure scheme for, the application using the sub- doped layer of middle layer as symmetry axis,
The corresponding sub- doped layer doping concentration in symmetry axis two sides is equal, and this doped layer is known as symmetrical structure；By Experimental comparison,
In odd-level doped layer more than or equal to three, the drop electric leakage effect of symmetrical structure is best.
Detailed description of the invention
Included attached drawing is used to provide that a further understanding of the embodiments of the present application, and which constitute one of specification
Point, for illustrating presently filed embodiment, and with verbal description come together to illustrate the principle of the application.Under it should be evident that
Attached drawing in the description of face is only some embodiments of the present application, for those of ordinary skill in the art, is not paying wound
Under the premise of the property made is laborious, it is also possible to obtain other drawings based on these drawings.In the accompanying drawings:
Fig. 1 is a kind of schematic diagram of exemplary display panel of the present invention；
Fig. 2 is the schematic diagram after a kind of exemplary display panel image retention aging of the invention；
Fig. 3 is the schematic diagram that a kind of exemplary normal picture of the invention is shown；
Fig. 4 is a kind of schematic diagram of example images residual bright spot of the invention；
Fig. 5 is the schematic diagram that a kind of exemplary doped layer of the invention is single layer structure；
Fig. 6 is the schematic diagram that a kind of exemplary doped layer of the invention is double-layer structure；
Fig. 7 is the schematic diagram that a kind of exemplary doped layer of the invention is four-layer structure；
Fig. 8 is a kind of leakage current of TFT different doped layer structures under -6V gate voltage of one embodiment of the invention
Schematic diagram；
Fig. 9 is that a kind of doped layer of one embodiment of the invention is the schematic diagram of three layers of symmetrical structure；
Figure 10 is that a kind of doped layer of one embodiment of the invention is the schematic diagram of five layers of symmetrical structure；
Figure 11 is a kind of schematic diagram of the production method of thin film transistor (TFT) of one embodiment of the invention；
Figure 12 is a kind of schematic diagram the step of depositing doped layer on active layer of one embodiment of the invention；
Figure 13 is the cross section the TFT energy band for one layer of doped layer that a kind of gate voltage of one embodiment of the invention is 0 volt
Schematic diagram；
Figure 14 is a kind of one layer doped layer TFT cross section energy band of the gate voltage of one embodiment of the invention less than 0 volt
Schematic diagram；
Figure 15 is that the TFT of the doped layer for three layers of symmetrical structure that a kind of gate voltage of one embodiment of the invention is 0 volt is horizontal
The schematic diagram of section energy band；
Figure 16 is that a kind of doped layer TFT of three layer symmetrical structure of the gate voltage of one embodiment of the invention less than 0 volt is horizontal
The schematic diagram of section energy band；
Figure 17 is a kind of four layer doped layer TFT cross section energy band of the gate voltage of one embodiment of the invention less than 0 volt
Schematic diagram；
Figure 18 is a kind of one layer doped layer TFT energy band broken line signal of the gate voltage of one embodiment of the invention less than 0 volt
Figure；
Figure 19 is a kind of three layer doped layer TFT energy band broken line signal of the gate voltage of one embodiment of the invention less than 0 volt
Figure；
Figure 20 is a kind of four layer doped layer TFT energy band broken line signal of the gate voltage of one embodiment of the invention less than 0 volt
Figure；
Figure 21 is a kind of schematic diagram of display panel of one embodiment of the invention.
Wherein, 100, display panel；200, thin film transistor (TFT)；210, substrate；220, the first metal layer；230, the first insulation
Layer；240, active layer；250, doped layer；251, the first sub- doped layer；252, the second sub- doped layer；253, the sub- doped layer of third；
254, the 4th sub- doped layer；255, the 5th sub- doped layer；260, second metal layer；261, source electrode；262, it drains；270, channel.
Specific embodiment
It is to be appreciated that term used herein above, disclosed specific structure and function details, it is only for description
Specific embodiment is representative, but the application can be implemented by many alternative forms, be not construed as only
It is limited to the embodiments set forth herein.
In the description of the present application, term " first ", " second " are used for description purposes only, and it is opposite to should not be understood as instruction
Importance, or implicitly indicate the quantity of indicated technical characteristic.As a result, unless otherwise indicated, " first ", " are defined
Two " feature can explicitly or implicitly include one or more of the features；The meaning of " plurality " is two or two
More than.Term " includes " and its any deformation, mean and non-exclusive include, it is understood that there may be or addition is one or more that other are special
Sign, integer, step, operation, unit, component and/or combination thereof.
In addition, "center", " transverse direction ", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner",
The term of the orientation or positional relationship of the instructions such as "outside" is that orientation or relative positional relationship based on the figure describe, only
Be that the application simplifies description for ease of description, rather than indicate signified device or element must have a particular orientation,
It is constructed and operated in a specific orientation, therefore should not be understood as the limitation to the application.
Furthermore unless specifically defined or limited otherwise, term " installation ", " connected ", " connection " shall be understood in a broad sense, example
Such as it may be fixed connection or may be dismantle connection, or integral connection；It can be mechanical connection, be also possible to be electrically connected
It connects；It can be directly connected, it can also indirectly connected through an intermediary or the connection inside two elements.For ability
For the those of ordinary skill in domain, the concrete meaning of above-mentioned term in this application can be understood as the case may be.
As shown in Figures 1 to 7, amorphous silicon film transistor 200 (TFT) processing procedure generallys use back channel etching (Back
Channel Etching, BCE) type structure, the infrastructure cost is low and simple process；But due to the interface shape of back channel etching
State is poor, and TFT electric leakage is larger.And 4 light shields are easy to produce biggish tail portion, more easily cause aobvious because of special etch process
Show that panel image remains.
Below with reference to the accompanying drawings the invention will be further described with optional embodiment.
As shown in Fig. 8 to Figure 10, the embodiment of the invention discloses a kind of thin film transistor (TFT)s 200, including substrate 210, first
Metal layer 220, the first insulating layer 230, active layer 240, doped layer 250 and second metal layer 260, wherein the first metal layer 220
It is arranged on substrate 210；First insulating layer 230 is arranged on the first metal layer 220；Active layer 240 is arranged in the first insulating layer
On 230；Doped layer 250 is arranged on active layer 240；Second metal layer 260 is arranged on doped layer 250；Doped layer 250 includes
Quantity is the sub- doped layer of N, and N is the odd number more than or equal to three, and sub- doped layer is stacked, and is pair with intermediate sub- doped layer
Claim axis, the corresponding sub- doped layer doping concentration in symmetry axis two sides is equal.
Using the sub- doped layer of middle layer as symmetry axis, the corresponding sub- doped layer doping concentration in symmetry axis two sides is equal, this
Kind doped layer 250 is known as symmetrical structure；If the corresponding sub- doped layer doping concentration in symmetry axis two sides is unequal, this doping
250 structure of layer are known as unsymmetric structure.Fig. 8 and table 1.1 are the doped layer 250, Yi Jidan of the three-decker of different levels of doping
Layer and the leakage current of doped layer 250 of four-layer structure compare, in figure ordinate be grid voltage in -6V leakage current it is big
Small, abscissa is the number of plies and concentration of sub- doped layer, and the point on curve respectively corresponds the different structure doped layer 250 of abscissa
Leakage current value at -6V, wherein A point corresponds to 250 structure of single layer doped layer, corresponding four layers of 250 structure of doped layer of B point, C/D/E
Corresponding three layers of 250 structure of doped layer, the corresponding N+/AH/N+ of D point are symmetrical structure, and the N-/AH/N+ of C point is unsymmetric structure, E
The corresponding N-/N/N+ of point is another unsymmetric structure, and the doping concentration of each layer is incremented by successively or successively decreases.Data are analyzed from figure
It is known that the number of plies of doped layer 250 is higher, leakage current is smaller, and is all three-decker, and the corresponding leakage current of D point is minimum, and
It is in close proximity to the numerical value of B point.By comparison, in the odd-level doped layer 250 more than or equal to three, the drop of symmetrical structure is leaked electricity
Effect is best.Above-mentioned to be illustrated by taking the doped layer 250 of three-decker as an example, the doped layer 250 of other numbers of plies also complies with this
Rule, details are not described herein.
Table 1.1
In one embodiment, the dopant of doped layer 250 is hydrogen phosphide and silane, and doping concentration is hydrogen phosphide and silane
Gas flow ratio.
, can be very high in the impedance of contact surface if active layer 240 is directly contacted with second metal layer 260, it is hindered to reduce
It is anti-, hydrogen phosphide (PH is used on the surface of active layer 2403) and silane (SiH4) deposition form n-type doping layer 250, n-type doping layer
250 formation needs to provide pentavalent atom, such as phosphorus atoms, and such doped layer 250 can provide more electronics, reduces contact resistance
It is anti-, and the gas flow ratio of hydrogen phosphide and silane is known as doping concentration, doping concentration is bigger, and hydrogen phosphide occupation ratio is more.
In one embodiment, the gas flow ratio of hydrogen phosphide and silane is between 0.32 to 4.1, the thickness of doped layer 250
Greater than 400 Ethylmercurichlorendimides, every layer of sub- doped layer doping concentration distribution is uniform.
Preferable film quality is obtained, the film thickness for improving doped layer 250 can also further decrease electric leakage, and the doping of sub- doped layer is dense
Degree is evenly distributed, and the symmetrical effect of sub- doped layer concentration can be improved, to improve leak reducing effect.
Fig. 9 show the doped layer of three layers of symmetrical structure.Doped layer 250 includes first sub- the 251, second son of doped layer doping
Layer 252 and the sub- doped layer 253 of third, the first sub- doped layer 251 are arranged on active layer 240, and the second sub- setting of doped layer 252 exists
On first sub- doped layer 251, the sub- doped layer 253 of third is arranged on the second sub- doped layer 252, and the setting of second metal layer 260 exists
On the sub- doped layer 253 of third, the first sub- doped layer 251 is equal with sub- 253 doping concentration of doped layer of third.
In three layers of symmetrical structure, the first sub- doped layer 251 is equal with sub- 253 doping concentration of doped layer of third, the second son
The doping concentration of doped layer 252 is more than or less than the first doping concentration of sub- doped layer 251 or mixing for the second sub- doped layer 252
Miscellaneous concentration is 0, that is, is undoped, and will form a potential barrier on their contact surface, and potential barrier is bigger, and electric leakage electronics is not allowed more
Easily pass through.
In one embodiment, in the symmetrical structure that sub- doped layer is three layers, doping concentration includes the first doping concentration N+
It is N+, the second son doping in the doping concentration of the first sub- doped layer 251 and the sub- doped layer 253 of third with the second doping concentration AH
The doping concentration of layer 252 is AH, and the numerical value of AH is equal to 0.
In three straton doped layers, drop electric leakage effect of the electric leakage effect than unsymmetric structure is dropped by comparison symmetrical structure
Good, it is exactly amorphous silicon layer that wherein doping concentration, which is the doped layer 250 of AH, can be generated between amorphous silicon layer and doped layer 250 larger
Potential barrier, thus reinforce drop electric leakage effect.
By taking 250 3 layers of doped layer of symmetrical structure as an example, there are also following arrangements for sub- doped layer doping concentration, and doping concentration is also
Including third doping concentration N and the 4th doping concentration N-, doping concentration numerical values recited relationship is N+ > N > N- > AH, the first son doping
The doping concentration of layer 251 and the sub- doped layer 253 of third is N+, and the doping concentration of the second sub- doped layer 252 is N；Optionally, first
The doping concentration of sub- doped layer 251 and the sub- doped layer 253 of third is N-, and the doping concentration of the second sub- doped layer 252 is AH；It is optional
, the doping concentration of the first sub- doped layer 251 and the sub- doped layer 253 of third is N, and the doping concentration of the second sub- doped layer 252 is
AH；Optionally, the doping concentration of the first sub- doped layer 251 and the sub- doped layer 253 of third is N-, and the second sub- doped layer 252 is mixed
Miscellaneous concentration is N.
Figure 10 show the doped layer of five layers of symmetrical structure.Doped layer 250 is mixed including the first sub- doped layer 251, the second son
The sub- doped layer 253 of diamicton 252, third, the 4th sub- doped layer 254 and the 5th sub- doped layer 255, the first sub- doped layer 251 are arranged
On active layer 240, the second sub- doped layer 252 is arranged on the first sub- doped layer 251, and the sub- setting of doped layer 253 of third is the
On two sub- doped layers 252, the 4th sub- doped layer 254 is arranged on the sub- doped layer 253 of third, and the 5th sub- setting of doped layer 255 exists
On 4th sub- doped layer 254, second metal layer 260 is arranged on the 5th sub- doped layer 255, the first sub- doped layer 251 and the 5th
Sub- 255 doping concentration of doped layer is equal, and the second sub- doped layer 252 is equal with the 4th sub- 254 doping concentration of doped layer.
It is one layer that N, which represents sub- doped layer, and it is three layers that N-/AH/N+, N+/AH/N+ and N-/N/N+, which represent sub- doped layer, N--/
It is four layers that N-/N+/N++, which represents sub- doped layer, and the electric leakage that sub- doped layer is one layer is maximum, and sub- doped layer is three layers secondly, son
The electric leakage that doped layer is four layers is minimum, and the distribution of four layers of sub- doped layer is not symmetrical structure, but four layers of sub- doped layer
The electric leakage but than three layers of symmetrical structure N+/AH/N+ of leaking electricity is small, although their electric leakage size is very close to but can explanation
The number of plies of sub- doped layer is more, and drop electric leakage effect is better, so the symmetrical structure drop electric leakage effect that sub- doped layer is five layers is better than three
The symmetrical structure drop electric leakage effect of layer.
By taking 250 5 layers of doped layer of symmetrical structure as an example, there are also following arrangements for sub- doped layer doping concentration, and doping concentration is also
Including the 5th doping concentration N++ and the 6th doping concentration N--, doping concentration numerical values recited relationship be N++ > N+ > N > N- > N-- >
The doping concentration of AH, the first sub- doped layer 251 and the 5th sub- doped layer 255 is N--, and the second sub- doped layer 252 is mixed with the 4th son
The doping concentration of diamicton 254 is N-, and the doping concentration of the sub- doped layer 253 of third is AH；Optionally, the first sub- doped layer 251 with
The doping concentration of 5th sub- doped layer 255 is N+, and the doping concentration of the second sub- doped layer 252 and the 4th sub- doped layer 254 is N+
+, the doping concentration of the sub- doped layer 253 of third is AH；Optionally, the doping of the first sub- doped layer 251 and the 5th sub- doped layer 255
Concentration is N--, and the doping concentration of the second sub- doped layer 252 and the 4th sub- doped layer 254 is N-, and the sub- doped layer 253 of third is mixed
Miscellaneous concentration is N；Optionally, the doping concentration of the first sub- doped layer 251 and the 5th sub- doped layer 255 is N+, the second sub- doped layer
252 and the 4th the doping concentration of sub- doped layer 254 be N++, the doping concentration of the sub- doped layer 253 of third is N；Optionally, first
The doping concentration of sub- doped layer 251 and the 5th sub- doped layer 255 is N-, the second sub- doped layer 252 and the 4th sub- doped layer 254
Doping concentration is N--, and the doping concentration of the sub- doped layer 253 of third is AH；Optionally, the first sub- doped layer 251 is mixed with the 5th son
The doping concentration of diamicton 255 is N++, and the doping concentration of the second sub- doped layer 252 and the 4th sub- doped layer 254 is N+, and third is sub
The doping concentration of doped layer 253 is AH；Optionally, the doping concentration of the first sub- doped layer 251 and the 5th sub- doped layer 255 is
The doping concentration of N-, the second sub- doped layer 252 and the 4th sub- doped layer 254 is N--, the doping concentration of the sub- doped layer 253 of third
For N；Optionally, the doping concentration of the first sub- doped layer 251 and the 5th sub- doped layer 255 is N++, the second sub- doped layer 252 with
The doping concentration of 4th sub- doped layer 254 is N+, and the doping concentration of the sub- doped layer 253 of third is N.
In one embodiment, active layer 240 includes amorphous silicon, and thin film transistor (TFT) 200 includes channel 270, the first metal layer
220 include grid, and second metal layer 260 is separated into two parts by channel 270, forms source electrode 261 and drain electrode 262, and channel 270 will
Doped layer 250 is separated into two parts, and source electrode 261 and drain electrode 262 are separately positioned on and are divided on two-part doped layer 250.
Amorphous silicon can be prepared by glow discharge decomposition silane, and channel 270 is formed by etching, and channel 270 will
Second metal layer 260 is separated into two parts, forms source, leakage the two poles of the earth, grid voltage induced channel 270 in amorphous silicon, and source,
It is conductive under drain bias.
As shown in figure 11, the embodiment of the present application discloses a kind of production method of thin film transistor (TFT), and step includes:
S111, the first metal layer is deposited on substrate；
S112, the first insulating layer is deposited on the first metal layer；
S113, active layer is deposited on the first insulating layer；
S114, doped layer is deposited on active layer；And
S115, the depositing second metal layer on doped layer；
Wherein, doped layer includes the sub- doped layer that quantity is N, and N is the odd number more than or equal to three, and sub- doping layer stackup is set
It sets, using intermediate sub- doped layer as symmetry axis, the corresponding sub- doped layer doping concentration in symmetry axis two sides is equal.
Deposition the first metal layer forms grid on substrate, can provide gate voltage, and one layer of insulation is deposited on grid and is protected
Gate isolation is deposited active layer by sheath on the first insulating layer, and it is film crystal that active layer, which is the amorphous silicon layer of semiconductor,
Pipe provide carrier conducting electric current, second metal layer formed source electrode and drain electrode, doped layer between second metal layer and active layer,
Reduce the contact impedance between active layer and second metal layer.
As shown in figure 12, include: the step of depositing doped layer on active layer
The gas flow ratio of S121, control hydrogen phosphide and silane are between 0.32 to 4.1；
S122, the doped layer will on hydrogen phosphide and silane-deposited to active layer, be formed with chemical vapour deposition technique.
The gas flow ratio of hydrogen phosphide and silane is known as doping concentration, no matter the symmetrical structure of a few straton doped layers, every layer
In sub- doped layer concentration range all between 0.32 to 4.1, can obtain preferable film quality, reduce electric leakage.
Any two be in contact solid fermi level must it is equal, when two kinds of materials are in contact, electronics will be from height
Fermi level material flows to low fermi level material until balance, and the fermi level of doped layer 250 is higher than the expense of amorphous silicon layer
Rice energy level, in their contact surface, electrons flow into amorphous silicon layer, 250 side of doped layer near contact surface from doped layer 250
In positive electricity, amorphous silicon layer side is in negative electricity, so being formed about a kind of electric field in contact surface, this electric field is known as barrier region, wears
It crosses energy required for barrier region and is known as potential barrier, the bigger electric leakage of potential barrier is smaller,
Figure 13 is the cross section the TFT energy band diagram that gate voltage is 0 volt, and Figure 14 is TFT cross section energy band of the gate voltage less than 0 volt
Figure, Figure 18 is TFT energy band line chart of the gate voltage less than 0 volt, and the doped layer 250 in Figure 13, Figure 14 and Figure 18 is all one layer, is mixed
Miscellaneous concentration is N；Figure 15 is the cross section the TFT energy band diagram that gate voltage is 0 volt, and Figure 16 is TFT cross section energy of the gate voltage less than 0 volt
Band figure, Figure 19 is TFT energy band line chart of the gate voltage less than 0 volt, and the doped layer 250 in Figure 15, Figure 16 and Figure 19 is all three layers,
Doping concentration distribution is N+/AH/N+；Figure 17 is TFT cross section energy band diagram of the gate voltage less than 0 volt, and Figure 19 is gate voltage less than 0
The TFT energy band line chart of volt, the doped layer 250 in Figure 17 and Figure 19 are four layers, doping concentration distribution N++/N+/N-/N--.
Wherein, Ec is a kind of energy state relatively high in this energy band system, more than or equal to this energy state
Electrons are detached from the constraint of single atom in material, to form electric leakage, Ev is then one kind relatively low in this energy band system
Energy state, the electronics less than or equal to this energy state are held by atom single in material；Ef is this energy
Average energy with electronics all in system；In doped layer 250 and amorphous silicon, the energy state of electronic stability can only be greater than etc.
In Ec, or be less than or equal to Ev, the energy state between Ec and Ev be it is unstable, Eb is the barrier energy in this energy band system
Barrier, that is, the barrier passed through required for unstable state is electronically formed, barrier is bigger, and electronics is more difficult to the leakage passed through, then formed
Electricity is just smaller, so Eb is bigger, leaks electricity in TFT smaller.
As shown in figure 21, as another embodiment of the present invention, a kind of display panel 100, including above-mentioned implementation are disclosed
The arbitrary thin film transistor (TFT) 200 of example.
It should be noted that the restriction for each step being related in this programme, in the premise for not influencing concrete scheme implementation
Under, it does not regard as being can be the step of making restriction to step sequencing, write on front what is first carried out, be also possible to
It executes, is possibly even performed simultaneously afterwards, as long as this programme can be implemented, all shall be regarded as belonging to protection model of the invention
It encloses.
Technical solution of the present invention can be widely applied to various display panels, such as twisted nematic (Twisted
Nematic, TN) display panel, plane conversion type (In-Plane Switching, IPS) display panel, vertical orientation type
(Vertical Alignment, VA) display panel, more quadrant vertical orientation type (Multi-Domain Vertical
Alignment, MVA) display panel, it is of course also possible to be other kinds of display panel, such as Organic Light Emitting Diode
(Organic Light-Emitting Diode, OLED) display panel, applicable above scheme.
The above content is specific optional embodiment is combined, further detailed description of the invention, cannot recognize
Fixed specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs,
Without departing from the inventive concept of the premise, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to the present invention
Protection scope.
Claims (10)
1. a kind of thin film transistor (TFT) characterized by comprising
Substrate；
The first metal layer, setting is over the substrate；
First insulating layer is arranged on the first metal layer；
Active layer, setting is on the first insulating layer；
Doped layer, setting is on the active layer；And
Second metal layer is arranged on the doped layer；
Wherein, the doped layer includes the sub- doped layer that quantity is N, and the N is the odd number more than or equal to three, the sub- doping
Layer stackup setting, using intermediate sub- doped layer as symmetry axis, the corresponding sub- doped layer doping concentration in symmetry axis two sides is equal.
2. a kind of thin film transistor (TFT) as described in claim 1, which is characterized in that the dopant of the doped layer is hydrogen phosphide
And silane, the doping concentration are the gas flow ratio of the hydrogen phosphide and the silane.
3. a kind of thin film transistor (TFT) as claimed in claim 2, which is characterized in that the gas stream of the hydrogen phosphide and the silane
Ratio is measured between 0.32 to 4.1.
4. a kind of thin film transistor (TFT) as described in claim 1, which is characterized in that the doped layer include the first sub- doped layer,
Second sub- doped layer and the sub- doped layer of third, on the active layer, second son adulterates for the first sub- doped layer setting
Layer is arranged on the described first sub- doped layer, and the sub- doped layer of third is arranged on the described second sub- doped layer, and described second
Metal layer is arranged on the sub- doped layer of the third, the first sub- doped layer and the sub- doped layer doping concentration phase of the third
Deng.
5. a kind of thin film transistor (TFT) as claimed in claim 4, which is characterized in that the doping concentration includes the first doping concentration
With the second doping concentration, the doping concentration of the first sub- doped layer and the sub- doped layer of the third is the first doping concentration, institute
The doping concentration for stating the second sub- doped layer is the second doping concentration.
6. a kind of thin film transistor (TFT) as described in claim 1, which is characterized in that the doped layer include the first sub- doped layer,
Second sub- doped layer, the sub- doped layer of third, the 4th sub- doped layer and the 5th sub- doped layer, the first sub- doped layer are arranged in institute
It states on active layer, the second sub- doped layer is arranged on the described first sub- doped layer, and the sub- doped layer of third is arranged in institute
It states on the second sub- doped layer, the 4th sub- doped layer is arranged on the sub- doped layer of the third, and the 5th sub- doped layer is set
It sets on the 4th sub- doped layer, the second metal layer is arranged on the 5th sub- doped layer, the first son doping
Layer, the second sub- doped layer and described fourth sub- doped layer doping concentration phase equal with the described 5th sub- doped layer doping concentration
Deng.
7. a kind of thin film transistor (TFT) as described in claim 1, which is characterized in that the corresponding son in the symmetry axis two sides
Doped layer doping concentration distribution is uniform.
8. a kind of production method of thin film transistor (TFT), which is characterized in that step includes:
The first metal layer is deposited on substrate；
The first insulating layer is deposited on the first metal layer；
Active layer is deposited on the first insulating layer；
Doped layer is deposited on active layer；And
The depositing second metal layer on doped layer；
Wherein, doped layer includes the sub- doped layer that quantity is N, and the N is the odd number more than or equal to three, and the sub- doping is layer by layer
Folded setting, using intermediate sub- doped layer as symmetry axis, the corresponding sub- doped layer doping concentration in symmetry axis two sides is equal.
9. a kind of production method of thin film transistor (TFT) as claimed in claim 8, which is characterized in that described to be deposited on active layer
The step of doped layer includes:
The gas flow ratio of control hydrogen phosphide and silane is between 0.32 to 4.1；
The doped layer on hydrogen phosphide and silane-deposited to active layer, will be formed with chemical vapour deposition technique.
10. a kind of display panel, which is characterized in that including thin film transistor (TFT) as claimed in any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811587013.8A CN109713044B (en) | 2018-12-25 | 2018-12-25 | Thin film transistor, manufacturing method and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811587013.8A CN109713044B (en) | 2018-12-25 | 2018-12-25 | Thin film transistor, manufacturing method and display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109713044A true CN109713044A (en) | 2019-05-03 |
| CN109713044B CN109713044B (en) | 2021-04-13 |
Family
ID=66257398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811587013.8A Active CN109713044B (en) | 2018-12-25 | 2018-12-25 | Thin film transistor, manufacturing method and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109713044B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113193049A (en) * | 2021-04-29 | 2021-07-30 | Tcl华星光电技术有限公司 | Semiconductor device, manufacturing method thereof and display panel |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4746961A (en) * | 1986-06-11 | 1988-05-24 | Hitachi, Ltd. | Field effect transistor |
| CN104576750A (en) * | 2014-12-02 | 2015-04-29 | 信利（惠州）智能显示有限公司 | Thin-film transistor structure |
| CN105161503A (en) * | 2015-09-15 | 2015-12-16 | 深圳市华星光电技术有限公司 | Amorphous silicon semiconductor thin film transistor (TFT) backboard structure |
| CN105405892A (en) * | 2015-12-14 | 2016-03-16 | 深圳市华星光电技术有限公司 | Thin film transistor and array substrate |
| CN108064419A (en) * | 2016-12-29 | 2018-05-22 | 深圳市柔宇科技有限公司 | The preparation method and array substrate of thin film transistor (TFT) and thin film transistor (TFT) |
-
2018
- 2018-12-25 CN CN201811587013.8A patent/CN109713044B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4746961A (en) * | 1986-06-11 | 1988-05-24 | Hitachi, Ltd. | Field effect transistor |
| CN104576750A (en) * | 2014-12-02 | 2015-04-29 | 信利（惠州）智能显示有限公司 | Thin-film transistor structure |
| CN105161503A (en) * | 2015-09-15 | 2015-12-16 | 深圳市华星光电技术有限公司 | Amorphous silicon semiconductor thin film transistor (TFT) backboard structure |
| CN105405892A (en) * | 2015-12-14 | 2016-03-16 | 深圳市华星光电技术有限公司 | Thin film transistor and array substrate |
| CN108064419A (en) * | 2016-12-29 | 2018-05-22 | 深圳市柔宇科技有限公司 | The preparation method and array substrate of thin film transistor (TFT) and thin film transistor (TFT) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113193049A (en) * | 2021-04-29 | 2021-07-30 | Tcl华星光电技术有限公司 | Semiconductor device, manufacturing method thereof and display panel |
| US20230019866A1 (en) * | 2021-04-29 | 2023-01-19 | Tcl China Star Optoelectronics Technology Co., Ltd. | Semiconductor device, manufacturing method thereof, and display panel |
| CN113193049B (en) * | 2021-04-29 | 2024-04-26 | Tcl华星光电技术有限公司 | Semiconductor device, manufacturing method thereof and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109713044B (en) | 2021-04-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101957530B (en) | TFT-LCD (Thin Film Transistor-Liquid Crystal Display) array baseplate and manufacturing method thereof | |
| CN100580955C (en) | Thin film transistor and liquid crystal display device using the same | |
| CN110174787A (en) | Array substrate and preparation method thereof and display device | |
| CN103383946A (en) | Array substrate, display device and preparation method of array substrate | |
| CN105589276A (en) | Array substrate, liquid crystal display panel and liquid crystal display device | |
| CN103499906A (en) | Array substrate, manufacturing method of array substrate and display device | |
| CN103489877A (en) | Array substrate, manufacturing method thereof and display device | |
| CN103311310A (en) | Thin film transistor, preparation method for same and array substrate | |
| US9412761B2 (en) | Array substrate, method for manufacturing the same and display apparatus | |
| CN106941121B (en) | A kind of thin film transistor (TFT) and preparation method thereof, array substrate and display device | |
| CN103811503A (en) | Array substrate and preparation method and display panel | |
| CN104576750A (en) | Thin-film transistor structure | |
| CN109696781A (en) | Array substrate, the production method of array substrate and display device | |
| JP2007173307A (en) | Thin film transistor | |
| WO2019109473A1 (en) | Ffs-mode array substrate and manufacturing method therefor | |
| CN109411485A (en) | Production method, array substrate and the display device of array substrate | |
| CN107910376B (en) | The manufacturing method and vertical structure thin film transistor (TFT) of vertical structure thin film transistor (TFT) | |
| CN107170754B (en) | Display device, array substrate and array substrate manufacturing method | |
| CN109713044A (en) | A kind of thin film transistor (TFT) and production method and display panel | |
| CN107564809B (en) | The etching solution and its engraving method of IGZO film layer | |
| CN101620350A (en) | TFT-LCD array substrate and manufacturing method thereof | |
| CN103700668A (en) | Array substrate and preparation method thereof as well as display device | |
| CN109935551A (en) | A kind of production method and array substrate of array substrate | |
| CN100454562C (en) | Thin-film transistor array substrates, manufacturing method and LCD device containing the same | |
| CN105336683A (en) | LTPS array substrate and manufacturing method thereof and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |