CN109687706A - Negative and positive voltage conversion circuit and negative pressure charge pump loop - Google Patents
Negative and positive voltage conversion circuit and negative pressure charge pump loop Download PDFInfo
- Publication number
- CN109687706A CN109687706A CN201910056502.9A CN201910056502A CN109687706A CN 109687706 A CN109687706 A CN 109687706A CN 201910056502 A CN201910056502 A CN 201910056502A CN 109687706 A CN109687706 A CN 109687706A
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- Prior art keywords
- mirror image
- circuit
- nmos tube
- negative
- image circuit
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/071—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate a negative voltage output from a positive voltage source
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a kind of negative and positive voltage conversion circuits, comprising: the first and second mirror image circuits of the mirror image each other that input terminal is all grounded, input terminal all connect the third and fourth mirror image circuit of the mirror image each other of supply voltage；The output end of the first to three mirror image circuit is separately connected the drain electrode of the first to three NMOS tube, and the drain electrode of the grid of the first to three NMOS tube and the first NMOS tube links together；The current ratio of the ratio of the breadth length ratio of the first to three NMOS tube and the first to three mirror image circuit is identical.First and two resistance be connected to first and two NMOS tube source electrode and negative voltage between；Second is connected with the source electrode of three NMOS tubes；3rd resistor is connected between the source electrode and ground of the first NMOS tube；4th resistance is connected between the output end and ground or negative voltage of the 4th mirror image circuit of output positive voltage.The invention discloses a kind of negative pressure charge pump loops.The present invention does not need that circuit cost can be reduced using additional reference voltage.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, more particularly to a kind of negative pressure charge pump loop.The present invention also relates to
And a kind of negative and positive voltage conversion circuit.
Background technique
As shown in Figure 1, being the schematic diagram of existing negative pressure charge pump loop；Clock signal Clock is connected to one with door 102
A input terminal is connected to the input terminal of negative pressure charge pump 101, the output end output of negative pressure charge pump 101 with the output end of door 102
Negative voltage Vneg, feed circuit are connected to the output end of negative pressure charge pump 101 and between another input terminals of door 102, instead
Current feed circuit includes comparator 103, resistor voltage divider circuit 104 and negative and positive voltage conversion circuit 105.Resistor voltage divider circuit in Fig. 1
104 are connected in series by multiple resistance, can adjust the connection relationship of resistance to the control of switch by digital signal Dac to control
The dividing ratios of resistor voltage divider circuit 104 processed.Since what resistor voltage divider circuit 104 exported is the partial pressure of negative voltage Vneg, therefore go back
It needs through negative and positive voltage conversion circuit 105 to be positive voltage Vpos by partial pressure switch.Negative and positive voltage conversion circuit 105 exports just
Voltage Vpos and reference voltage Vref101 is compared output feedback voltage i.e. clock control signal Clock_en, clock control
Whether signal Clock_en control clock signal Clock is supplied to 101 circuit of charge pump, to adjust the output of charge pump 101
Voltage Vneg is to desired value.
As shown in Fig. 2, being the circuit diagram of existing negative and positive voltage conversion circuit, existing negative and positive voltage conversion circuit includes:
The first input end of comparator 201, comparator 201 connects reference voltage Vref 102, the output end of comparator 201
It is connected with the second input terminal.
Resistance R201 and R202 are connected between the output end of comparator 201 and negative voltage Vneg.
The junction of resistance R201 and R202 export positive voltage Vpos.
Existing negative and positive voltage conversion circuit shown in Fig. 2 needs in addition to use reference voltage Vref 102, additional reference again
Voltage will increase circuit cost.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of negative and positive voltage conversion circuit, do not need using additional ginseng
Voltage is examined, circuit cost can be reduced.For this purpose, the present invention also provides a kind of negative pressure charge pump loops.
In order to solve the above technical problems, negative and positive voltage conversion circuit provided by the invention includes:
The first mirror image circuit and the second mirror image circuit of mirror image each other, enables the output end current of first mirror image circuit be
I1, the output end current of second mirror image circuit are I2, and I2 is k1 times of I1；The input terminal of first mirror image circuit and institute
The input terminal for stating the second mirror image circuit is all grounded.
The third mirror image circuit and the 4th mirror image circuit of mirror image each other, enables the output end current of the third mirror image circuit be
I3, the output end current of the 4th mirror image circuit are I4, and I3 is k2 times of I1, and I4 is k3 times of I1；The third mirror image electricity
The input terminal of the input terminal on road and the third mirror image circuit all connects supply voltage.
The drain and gate of first NMOS tube connect the output end of first mirror image circuit, the second NMOS tube grid and
The grid of third NMOS tube.
The drain electrode of second NMOS tube connects the output end of second mirror image circuit.
The drain electrode of the third NMOS tube connects the output end of the third mirror image circuit.
The source-drain current of first NMOS tube is I1, and the source-drain current of second NMOS tube is I2, the third
The source-drain current of NMOS tube is I3.
The breadth length ratio of the channel of second NMOS tube is k1 times of the breadth length ratio of the channel of first NMOS tube, described
The breadth length ratio of the channel of third NMOS tube is k2 times of the breadth length ratio of the channel of first NMOS tube, makes first NMOS tube
Source voltage, second NMOS tube source voltage and the third NMOS tube source voltage it is equal.
First resistor is connected between the source electrode and negative voltage of first NMOS tube.
Second resistance is connected between the source electrode and negative voltage of second NMOS tube, the source electrode of the third NMOS tube
Connect the source electrode of second NMOS tube.
3rd resistor is connected between the source electrode and ground of first NMOS tube.
4th resistance is connected between the output end and ground of the 4th mirror image circuit or the 4th resistance be connected to it is described
Between the output end and negative voltage of 4th mirror image circuit.
The output end of 4th mirror image circuit exports positive voltage, and the positive voltage is by k1, k2 and k3 and described first
Resistance, the second resistance, the 3rd resistor, the 4th resistance and the negative voltage determine.
A further improvement is that first mirror image circuit is made of the first PMOS tube, second mirror image circuit is by
Two PMOS tube composition, the third mirror image circuit are made of third PMOS tube, and the 4th mirror image circuit is by the 4th PMOS tube group
At.
The breadth length ratio of the channel of second PMOS tube is k1 times of the breadth length ratio of the channel of first PMOS tube, described
The breadth length ratio of the channel of third PMOS tube is k2 times of the breadth length ratio of the channel of first PMOS tube, the 4th PMOS tube
The breadth length ratio of channel is k3 times of the breadth length ratio of the channel of first PMOS tube.
A further improvement is that k1, k2 and k3 are 1.
A further improvement is that the resistance value of the first resistor and the second resistance is equal.
The size of current of the 3rd resistor is equal to I1.
A further improvement is that the negative voltage is provided by the output end of negative pressure charge pump.
A further improvement is that the negative and positive voltage conversion circuit is located in the feed circuit of the negative pressure charge pump, institute
Stating feed circuit includes: the negative and positive voltage conversion circuit, comparator, clock signal generating circuit.
The positive voltage of the negative and positive voltage conversion circuit output is input in an input terminal of the comparator, institute
It states comparator the positive voltage and reference voltage are compared to form clock control signal.
The clock control signal adjusts the clock signal of the clock signal generating circuit output.
The clock signal input after adjusting is into the negative pressure charge pump and controls the size of the negative voltage.
A further improvement is that the feed circuit further includes one and door, it is described to connect institute with the first input end of door
The clock signal of clock signal generating circuit output is stated, it is described to connect the clock control signal, institute with the second input terminal of door
State the input terminal with the clock signal after the output adjusting of the output end of door to the negative pressure charge pump.
A further improvement is that the clock signal generating circuit is pierce circuit (OSC).
In order to solve the above technical problems, negative pressure charge pump loop provided by the invention includes negative pressure charge pump and feedback electricity
Road；The negative pressure charge pump exports negative voltage.
It include negative and positive voltage conversion circuit in the feed circuit, the negative and positive voltage conversion circuit includes:
The first mirror image circuit and the second mirror image circuit of mirror image each other, enables the output end current of first mirror image circuit be
I1, the output end current of second mirror image circuit are I2, and I2 is k1 times of I1；The input terminal of first mirror image circuit and institute
The input terminal for stating the second mirror image circuit is all grounded.
The third mirror image circuit and the 4th mirror image circuit of mirror image each other, enables the output end current of the third mirror image circuit be
I3, the output end current of the 4th mirror image circuit are I4, and I3 is k2 times of I1, and I4 is k3 times of I1；The third mirror image electricity
The input terminal of the input terminal on road and the third mirror image circuit all connects supply voltage.
The drain and gate of first NMOS tube connect the output end of first mirror image circuit, the second NMOS tube grid and
The grid of third NMOS tube.
The drain electrode of second NMOS tube connects the output end of second mirror image circuit.
The drain electrode of the third NMOS tube connects the output end of the third mirror image circuit.
The source-drain current of first NMOS tube is I1, and the source-drain current of second NMOS tube is I2, the third
The source-drain current of NMOS tube is I3.
The breadth length ratio of the channel of second NMOS tube is k1 times of the breadth length ratio of the channel of first NMOS tube, described
The breadth length ratio of the channel of third NMOS tube is k2 times of the breadth length ratio of the channel of first NMOS tube, makes first NMOS tube
Source voltage, second NMOS tube source voltage and the third NMOS tube source voltage it is equal.
First resistor is connected between the source electrode and negative voltage of first NMOS tube.
Second resistance is connected between the source electrode and negative voltage of second NMOS tube, the source electrode of the third NMOS tube
Connect the source electrode of second NMOS tube.
3rd resistor is connected between the source electrode and ground of first NMOS tube.
4th resistance is connected between the output end and ground of the 4th mirror image circuit or the 4th resistance be connected to it is described
Between the output end and negative voltage of 4th mirror image circuit.
The output end of 4th mirror image circuit exports positive voltage, and the positive voltage is by k1, k2 and k3 and described first
Resistance, the second resistance, the 3rd resistor, the 4th resistance and the negative voltage determine.
A further improvement is that first mirror image circuit is made of the first PMOS tube, second mirror image circuit is by
Two PMOS tube composition, the third mirror image circuit are made of third PMOS tube, and the 4th mirror image circuit is by the 4th PMOS tube group
At.
The breadth length ratio of the channel of second PMOS tube is k1 times of the breadth length ratio of the channel of first PMOS tube, described
The breadth length ratio of the channel of third PMOS tube is k2 times of the breadth length ratio of the channel of first PMOS tube, the 4th PMOS tube
The breadth length ratio of channel is k3 times of the breadth length ratio of the channel of first PMOS tube.
A further improvement is that k1, k2 and k3 are 1.
A further improvement is that the resistance value of the first resistor and the second resistance is equal.
The size of current of the 3rd resistor is equal to I1.
A further improvement is that the feed circuit includes: the negative and positive voltage conversion circuit, comparator, clock signal
Generation circuit.
The positive voltage of the negative and positive voltage conversion circuit output is input in an input terminal of the comparator, institute
It states comparator the positive voltage and reference voltage are compared to form clock control signal.
The clock control signal adjusts the clock signal of the clock signal generating circuit output.
The clock signal input after adjusting is into the negative pressure charge pump and controls the size of the negative voltage.
A further improvement is that the feed circuit further includes one and door, it is described to connect institute with the first input end of door
The clock signal of clock signal generating circuit output is stated, it is described to connect the clock control signal, institute with the second input terminal of door
State the input terminal with the clock signal after the output adjusting of the output end of door to the negative pressure charge pump.
A further improvement is that the clock signal generating circuit is pierce circuit.
The present invention does not need that circuit cost can be reduced using additional reference voltage.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the circuit diagram of existing negative pressure charge pump loop；
Fig. 2 is the circuit diagram of existing negative and positive voltage conversion circuit；
Fig. 3 is the circuit diagram of first embodiment of the invention negative and positive voltage conversion circuit；
Fig. 4 is the circuit diagram of second embodiment of the invention negative and positive voltage conversion circuit.
Specific embodiment
First embodiment of the invention negative and positive voltage conversion circuit:
As shown in figure 3, being the circuit diagram of first embodiment of the invention negative and positive voltage conversion circuit, invention first
Embodiment negative and positive voltage conversion circuit includes:
The first mirror image circuit 1 and the second mirror image circuit 2 of mirror image each other enables the output end electricity of first mirror image circuit 1
Stream is I1, and the output end current of second mirror image circuit 2 is I2, and I2 is k1 times of I1；The input of first mirror image circuit 1
The input terminal of end and second mirror image circuit 2 is all grounded Gnd.
The third mirror image circuit 3 and the 4th mirror image circuit 4 of mirror image each other enables the output end electricity of the third mirror image circuit 3
Stream is I3, and the output end current of the 4th mirror image circuit 4 is I4, and I3 is k2 times of I1, and I4 is k3 times of I1；The third mirror
As the input terminal of circuit 3 and the input terminal of the third mirror image circuit 3 all meet supply voltage Vdd.Electric current I1, I2, I3, I4 and after
Continuous electric current I5 is marked in Fig. 3.
The drain and gate of first NMOS tube MN1 connects the output end of first mirror image circuit 1, the second NMOS tube MN2
Grid and third NMOS tube MN3 grid.
The drain electrode of the second NMOS tube MN2 connects the output end of second mirror image circuit 2.
The drain electrode of the third NMOS tube MN3 connects the output end of the third mirror image circuit 3.
The source-drain current of the first NMOS tube MN1 is I1, and the source-drain current of the second NMOS tube MN2 is I2, described
The source-drain current of third NMOS tube MN3 is I3.
The breadth length ratio of the channel of the second NMOS tube MN2 is the k1 of the breadth length ratio of the channel of the first NMOS tube MN1
Times, the breadth length ratio of the channel of the third NMOS tube MN3 is k2 times of the breadth length ratio of the channel of the first NMOS tube MN1, is made
Voltage Va in source voltage, that is, Fig. 3 of the first NMOS tube MN1, in source voltage, that is, Fig. 3 of the second NMOS tube MN2
Voltage Vb and the third NMOS tube MN3 source voltage it is equal.For NMOS tube, when the gate source voltage of NMOS tube is equal
When, the breadth length ratio of the channel of the ratio and NMOS tube of source-drain current is equal between NMOS tube；Conversely, when source and drain electricity between NMOS tube
When the breadth length ratio of the channel of the ratio and NMOS tube of stream is equal, the gate source voltage of each NMOS tube is equal, when grid voltage is equal,
Source voltage is also equal.
First resistor R1 is connected between the source electrode and negative voltage Vneg of the first NMOS tube MN1.
Second resistance R2 is connected between the source electrode and negative voltage Vneg of the second NMOS tube MN2, the 3rd NMOS
The source electrode of pipe MN3 also connects the source electrode of the second NMOS tube MN2.
3rd resistor R3 is connected between the source electrode and ground Gnd of the first NMOS tube MN1.
4th resistance R4 is connected between the output end and ground Gnd of the 4th mirror image circuit 4.
The output end of 4th mirror image circuit 4 exports positive voltage Vpos, the positive voltage Vpos by k1, k2 and k3 and
The first resistor R1, the second resistance R2, the 3rd resistor R3, the 4th resistance R4 and the negative voltage Vneg
It determines.It is specific to calculate are as follows:
It can be obtained by (Va-Vneg)/R1=I1-Va/R3: Va=(I1*R1+Vneg) * R3/ (R3+R1).
The size of Vb are as follows: Vb=(I2+I3) * R2+Vneg=(k1+k2) * I1*R2+Vneg；
I1=Vneg*R1/ (R1*R3- (k1+k2) * R2* (R1+R3)) can be obtained by Va=Vb；
Vpos=I4*R4=k3*I1*R4=k3*R4*Vneg*R1/ (R1*R3- (k1+k2) * R2* (R1+R3)).
In above-mentioned formula, R1, R2, R3 and R4 all indicate for first resistor R1, the second resistance R2, the third
The resistance value of resistance R3, the 4th resistance R4.
Know that Vpos is not needed using reference voltage Vref 101.
It is preferably selected as, first mirror image circuit 1 is made of the first PMOS tube MP1, and second mirror image circuit 2 is by
Two PMOS tube MP2 composition, the third mirror image circuit 3 are made of third PMOS tube MP3, and the 4th mirror image circuit 4 is by the 4th
PMOS tube MP4 composition.
The breadth length ratio of the channel of the second PMOS tube MP2 is the k1 of the breadth length ratio of the channel of the first PMOS tube MP1
Times, the breadth length ratio of the channel of the third PMOS tube MP3 is k2 times of the breadth length ratio of the channel of the first PMOS tube MP1, institute
The breadth length ratio for stating the channel of the 4th PMOS tube MP4 is k3 times of breadth length ratio of channel of the first PMOS tube MP1.
A further improvement is that k1, k2 and k3 are 1.The resistance value phase of the first resistor R1 and the second resistance R2
Deng.At this moment, the size of current of the 3rd resistor R3 is equal to I1.The formula for substituting into Vpos above is available: Vpos=-R4*
Vneg/(R3+2R1)。
As shown in Figure 1, the negative voltage Vneg is provided by the output end of negative pressure charge pump 101 in the embodiment of the present invention.
The negative and positive voltage conversion circuit 105 is located in the feed circuit of the negative pressure charge pump 101, the feed circuit
It include: the negative and positive voltage conversion circuit 105, comparator 103, clock signal generating circuit.The clock signal generating circuit
For pierce circuit.
The positive voltage Vpos that the negative and positive voltage conversion circuit 105 exports is input to one of the comparator 103
In input terminal, the comparator 103 is compared the positive voltage Vpos and reference voltage Vref 101 to form clock control letter
Number Clock_en.
The clock control signal Clock_en adjusts the clock signal Clock of the clock signal generating circuit output.
The clock signal Clock after adjusting is input in the negative pressure charge pump 101 and controls the negative voltage
The size of Vneg.
The feed circuit further includes one and door 102, and the first input end with door 102 connect the clock signal
The clock signal Clock of generation circuit output, it is described to connect the clock control signal Clock_ with the second input terminal of door 102
En, the output end with door 102 export the input of the clock signal Clock after adjusting to the negative pressure charge pump 101
End.
Second embodiment of the invention negative and positive voltage conversion circuit:
As shown in figure 4, being the circuit diagram of second embodiment of the invention negative and positive voltage conversion circuit, invention second
In place of the difference of embodiment negative and positive voltage conversion circuit and first embodiment of the invention negative and positive voltage conversion circuit are as follows:
The 4th resistance R4 in invention second embodiment negative and positive voltage conversion circuit is connected to described
Between the output end and negative voltage Vneg of four mirror image circuits 4.At this moment, Vpos is on the basis of Vneg along with the 4th resistance R4
On pressure drop obtain, again without use reference voltage.
Third embodiment of the invention negative pressure charge pump loop:
As shown in Figure 1, third embodiment of the invention negative pressure charge pump loop includes negative pressure charge pump 101 and feed circuit；
The negative pressure charge pump 101 exports negative voltage Vneg.
It include negative and positive voltage conversion circuit 105 in the feed circuit, as shown in figure 3, the negative and positive voltage conversion circuit
105 include:
The first mirror image circuit 1 and the second mirror image circuit 2 of mirror image each other enables the output end electricity of first mirror image circuit 1
Stream is I1, and the output end current of second mirror image circuit 2 is I2, and I2 is k1 times of I1；The input of first mirror image circuit 1
The input terminal of end and second mirror image circuit 2 is all grounded Gnd.
The third mirror image circuit 3 and the 4th mirror image circuit 4 of mirror image each other enables the output end electricity of the third mirror image circuit 3
Stream is I3, and the output end current of the 4th mirror image circuit 4 is I4, and I3 is k2 times of I1, and I4 is k3 times of I1；The third mirror
As the input terminal of circuit 3 and the input terminal of the third mirror image circuit 3 all meet supply voltage Vdd.
The drain and gate of first NMOS tube MN1 connects the output end of first mirror image circuit 1, the second NMOS tube MN2
Grid and third NMOS tube MN3 grid.
The drain electrode of the second NMOS tube MN2 connects the output end of second mirror image circuit 2.
The drain electrode of the third NMOS tube MN3 connects the output end of the third mirror image circuit 3.
The source-drain current of the first NMOS tube MN1 is I1, and the source-drain current of the second NMOS tube MN2 is I2, described
The source-drain current of third NMOS tube MN3 is I3.
The breadth length ratio of the channel of the second NMOS tube MN2 is the k1 of the breadth length ratio of the channel of the first NMOS tube MN1
Times, the breadth length ratio of the channel of the third NMOS tube MN3 is k2 times of the breadth length ratio of the channel of the first NMOS tube MN1, is made
The source voltage of the first NMOS tube MN1, the source voltage of the second NMOS tube MN2 and the third NMOS tube MN3
Source voltage is equal.
First resistor R1 is connected between the source electrode and negative voltage Vneg of the first NMOS tube MN1.
Second resistance R2 is connected between the source electrode and negative voltage Vneg of the second NMOS tube MN2, the 3rd NMOS
The source electrode of pipe MN3 also connects the source electrode of the second NMOS tube MN2.
3rd resistor R3 is connected between the source electrode and ground Gnd of the first NMOS tube MN1.
4th resistance R4 is connected between the output end and ground Gnd of the 4th mirror image circuit 4.
The output end of 4th mirror image circuit 4 exports positive voltage Vpos, the positive voltage Vpos by k1, k2 and k3 and
The first resistor R1, the second resistance R2, the 3rd resistor R3, the 4th resistance R4 and the negative voltage Vneg
It determines.
Preferably, first mirror image circuit 1 is made of the first PMOS tube MP1, and second mirror image circuit 2 is by second
PMOS tube MP2 composition, the third mirror image circuit 3 are made of third PMOS tube MP3, and the 4th mirror image circuit 4 is by the 4th
PMOS tube MP4 composition.
The breadth length ratio of the channel of the second PMOS tube MP2 is the k1 of the breadth length ratio of the channel of the first PMOS tube MP1
Times, the breadth length ratio of the channel of the third PMOS tube MP3 is k2 times of the breadth length ratio of the channel of the first PMOS tube MP1, institute
The breadth length ratio for stating the channel of the 4th PMOS tube MP4 is k3 times of breadth length ratio of channel of the first PMOS tube MP1.
A further improvement is that k1, k2 and k3 are 1.The resistance value phase of the first resistor R1 and the second resistance R2
Deng.The size of current of the 3rd resistor R3 is equal to I1.
The feed circuit includes: the negative and positive voltage conversion circuit 105, comparator 103, clock signal generating circuit.
The positive voltage Vpos that the negative and positive voltage conversion circuit 105 exports is input to one of the comparator 103
In input terminal, the comparator 103 is compared the positive voltage Vpos and reference voltage Vref 101 to form clock control letter
Number Clock_en.
The clock control signal Clock_en adjusts the clock signal Clock of the clock signal generating circuit output.
The clock signal Clock after adjusting is input in the negative pressure charge pump 101 and controls the negative voltage
The size of Vneg.
The feed circuit further includes one and door 102, and the first input end with door 102 connect the clock signal
The clock signal Clock of generation circuit output, it is described to connect the clock control signal Clock_ with the second input terminal of door 102
En, the output end with door 102 export the input of the clock signal Clock after adjusting to the negative pressure charge pump 101
End.
The clock signal generating circuit is pierce circuit.
Fourth embodiment of the invention negative and positive voltage conversion circuit:
As shown in figure 4, negative and positive voltage conversion circuit and sheet that fourth embodiment of the invention negative and positive voltage conversion circuit uses
In place of the difference for the negative and positive voltage conversion circuit that invention 3rd embodiment negative and positive voltage conversion circuit uses are as follows:
The 4th electricity in the negative and positive voltage conversion circuit that fourth embodiment of the invention negative and positive voltage conversion circuit uses
Resistance R4 is connected between the output end and negative voltage Vneg of the 4th mirror image circuit 4.At this moment, Vpos is on the basis of Vneg
Along with the pressure drop on the 4th resistance R4 obtains, again without using reference voltage.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of negative and positive voltage conversion circuit characterized by comprising
The first mirror image circuit and the second mirror image circuit of mirror image each other, enabling the output end current of first mirror image circuit is I1,
The output end current of second mirror image circuit is I2, and I2 is k1 times of I1；The input terminal of first mirror image circuit and described
The input terminal of second mirror image circuit is all grounded；
The third mirror image circuit and the 4th mirror image circuit of mirror image each other, enabling the output end current of the third mirror image circuit is I3,
The output end current of 4th mirror image circuit is I4, and I3 is k2 times of I1, and I4 is k3 times of I1；The third mirror image circuit
The input terminal of input terminal and the third mirror image circuit all connects supply voltage；
The drain and gate of first NMOS tube connects the grid and third of the output end of first mirror image circuit, the second NMOS tube
The grid of NMOS tube；
The drain electrode of second NMOS tube connects the output end of second mirror image circuit；
The drain electrode of the third NMOS tube connects the output end of the third mirror image circuit；
The source-drain current of first NMOS tube is I1, and the source-drain current of second NMOS tube is I2, the third NMOS tube
Source-drain current be I3；
The breadth length ratio of the channel of second NMOS tube is k1 times of the breadth length ratio of the channel of first NMOS tube, the third
The breadth length ratio of the channel of NMOS tube is k2 times of the breadth length ratio of the channel of first NMOS tube, makes the source of first NMOS tube
The source voltage of pole tension, the source voltage of second NMOS tube and the third NMOS tube is equal；
First resistor is connected between the source electrode and negative voltage of first NMOS tube；
Second resistance is connected between the source electrode and negative voltage of second NMOS tube, and the source electrode of the third NMOS tube also connects
The source electrode of second NMOS tube；
3rd resistor is connected between the source electrode and ground of first NMOS tube；
4th resistance is connected between the output end and ground of the 4th mirror image circuit or the 4th resistance is connected to the described 4th
Between the output end and negative voltage of mirror image circuit；
The output end of 4th mirror image circuit exports positive voltage, the positive voltage by k1, k2 and k3 and the first resistor,
The second resistance, the 3rd resistor, the 4th resistance and the negative voltage determine.
2. negative and positive voltage conversion circuit as described in claim 1, it is characterised in that: first mirror image circuit is by the first PMOS
Pipe composition, second mirror image circuit are made of the second PMOS tube, and the third mirror image circuit is made of third PMOS tube, described
4th mirror image circuit is made of the 4th PMOS tube；
The breadth length ratio of the channel of second PMOS tube is k1 times of the breadth length ratio of the channel of first PMOS tube, the third
The breadth length ratio of the channel of PMOS tube is k2 times of the breadth length ratio of the channel of first PMOS tube, the channel of the 4th PMOS tube
Breadth length ratio be k3 times of breadth length ratio of channel of first PMOS tube.
3. negative and positive voltage conversion circuit as claimed in claim 1 or 2, it is characterised in that: k1, k2 and k3 are 1.
4. negative and positive voltage conversion circuit as claimed in claim 3, it is characterised in that: the first resistor and the second resistance
Resistance value it is equal；
The size of current of the 3rd resistor is equal to I1.
5. negative and positive voltage conversion circuit as described in claim 1, it is characterised in that: the negative voltage is defeated by negative pressure charge pump
Outlet provides.
6. negative and positive voltage conversion circuit as claimed in claim 5, it is characterised in that: the negative and positive voltage conversion circuit is located at institute
In the feed circuit for stating negative pressure charge pump, the feed circuit includes: the negative and positive voltage conversion circuit, comparator, clock letter
Number generation circuit；
The positive voltage of the negative and positive voltage conversion circuit output is input in an input terminal of the comparator, the ratio
The positive voltage and reference voltage are compared to form clock control signal compared with device；
The clock control signal adjusts the clock signal of the clock signal generating circuit output；
The clock signal input after adjusting is into the negative pressure charge pump and controls the size of the negative voltage.
7. negative and positive voltage conversion circuit as claimed in claim 6, it is characterised in that: the feed circuit further include one with
Door, the clock signal that the clock signal generating circuit output is connect with the first input end of door, second with door
Input terminal connects the clock control signal, the clock signal after the output end output adjusting with door to the negative pressure
The input terminal of charge pump.
8. negative and positive voltage conversion circuit as claimed in claim 6, it is characterised in that: the clock signal generating circuit is oscillation
Device circuit.
9. a kind of negative pressure charge pump loop, which is characterized in that including negative pressure charge pump and feed circuit；The negative pressure charge pump is defeated
Negative voltage out；
It include negative and positive voltage conversion circuit in the feed circuit, the negative and positive voltage conversion circuit includes:
The first mirror image circuit and the second mirror image circuit of mirror image each other, enabling the output end current of first mirror image circuit is I1,
The output end current of second mirror image circuit is I2, and I2 is k1 times of I1；The input terminal of first mirror image circuit and described
The input terminal of second mirror image circuit is all grounded；
The third mirror image circuit and the 4th mirror image circuit of mirror image each other, enabling the output end current of the third mirror image circuit is I3,
The output end current of 4th mirror image circuit is I4, and I3 is k2 times of I1, and I4 is k3 times of I1；The third mirror image circuit
The input terminal of input terminal and the third mirror image circuit all connects supply voltage；
The drain and gate of first NMOS tube connects the grid and third of the output end of first mirror image circuit, the second NMOS tube
The grid of NMOS tube；
The drain electrode of second NMOS tube connects the output end of second mirror image circuit；
The drain electrode of the third NMOS tube connects the output end of the third mirror image circuit；
The source-drain current of first NMOS tube is I1, and the source-drain current of second NMOS tube is I2, the third NMOS tube
Source-drain current be I3；
The breadth length ratio of the channel of second NMOS tube is k1 times of the breadth length ratio of the channel of first NMOS tube, the third
The breadth length ratio of the channel of NMOS tube is k2 times of the breadth length ratio of the channel of first NMOS tube, makes the source of first NMOS tube
The source voltage of pole tension, the source voltage of second NMOS tube and the third NMOS tube is equal；
First resistor is connected between the source electrode and negative voltage of first NMOS tube；
Second resistance is connected between the source electrode and negative voltage of second NMOS tube, and the source electrode of the third NMOS tube also connects
The source electrode of second NMOS tube；
3rd resistor is connected between the source electrode and ground of first NMOS tube；
4th resistance is connected between the output end and ground of the 4th mirror image circuit or the 4th resistance is connected to the described 4th
Between the output end and negative voltage of mirror image circuit；
The output end of 4th mirror image circuit exports positive voltage, the positive voltage by k1, k2 and k3 and the first resistor,
The second resistance, the 3rd resistor, the 4th resistance and the negative voltage determine.
10. negative pressure charge pump loop as claimed in claim 9, it is characterised in that: first mirror image circuit is by the first PMOS
Pipe composition, second mirror image circuit are made of the second PMOS tube, and the third mirror image circuit is made of third PMOS tube, described
4th mirror image circuit is made of the 4th PMOS tube；
The breadth length ratio of the channel of second PMOS tube is k1 times of the breadth length ratio of the channel of first PMOS tube, the third
The breadth length ratio of the channel of PMOS tube is k2 times of the breadth length ratio of the channel of first PMOS tube, the channel of the 4th PMOS tube
Breadth length ratio be k3 times of breadth length ratio of channel of first PMOS tube.
11. the negative pressure charge pump loop as described in claim 9 or 10, it is characterised in that: k1, k2 and k3 are 1.
12. negative pressure charge pump loop as claimed in claim 11, it is characterised in that: the first resistor and the second resistance
Resistance value it is equal；
The size of current of the 3rd resistor is equal to I1.
13. negative pressure charge pump loop as claimed in claim 9, it is characterised in that: the feed circuit includes: the negative and positive electricity
Voltage conversion circuit, comparator, clock signal generating circuit；
The positive voltage of the negative and positive voltage conversion circuit output is input in an input terminal of the comparator, the ratio
The positive voltage and reference voltage are compared to form clock control signal compared with device；
The clock control signal adjusts the clock signal of the clock signal generating circuit output；
The clock signal input after adjusting is into the negative pressure charge pump and controls the size of the negative voltage.
14. negative pressure charge pump loop as claimed in claim 13, it is characterised in that: the feed circuit further include one with
Door, the clock signal that the clock signal generating circuit output is connect with the first input end of door, second with door
Input terminal connects the clock control signal, the clock signal after the output end output adjusting with door to the negative pressure
The input terminal of charge pump.
15. negative pressure charge pump loop as claimed in claim 13, it is characterised in that: the clock signal generating circuit is oscillation
Device circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910056502.9A CN109687706A (en) | 2019-01-22 | 2019-01-22 | Negative and positive voltage conversion circuit and negative pressure charge pump loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910056502.9A CN109687706A (en) | 2019-01-22 | 2019-01-22 | Negative and positive voltage conversion circuit and negative pressure charge pump loop |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109687706A true CN109687706A (en) | 2019-04-26 |
Family
ID=66193666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910056502.9A Pending CN109687706A (en) | 2019-01-22 | 2019-01-22 | Negative and positive voltage conversion circuit and negative pressure charge pump loop |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109687706A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6469554B1 (en) * | 1999-11-23 | 2002-10-22 | Sony United Kingdom Limited | Charge pump |
| CN104518663A (en) * | 2014-07-18 | 2015-04-15 | 上海华虹宏力半导体制造有限公司 | Feedback circuit of negative-pressure charge pump |
| US10061339B1 (en) * | 2017-11-03 | 2018-08-28 | Nxp Usa, Inc. | Feedback circuit and methods for negative charge pump |
-
2019
- 2019-01-22 CN CN201910056502.9A patent/CN109687706A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6469554B1 (en) * | 1999-11-23 | 2002-10-22 | Sony United Kingdom Limited | Charge pump |
| CN104518663A (en) * | 2014-07-18 | 2015-04-15 | 上海华虹宏力半导体制造有限公司 | Feedback circuit of negative-pressure charge pump |
| US10061339B1 (en) * | 2017-11-03 | 2018-08-28 | Nxp Usa, Inc. | Feedback circuit and methods for negative charge pump |
Non-Patent Citations (1)
| Title |
|---|
| 贾建章，武岳: "《最新集成电路设计手册》", 31 March 2004, 银声音像出版社 * |
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Application publication date: 20190426 |