CN109613336B - Frequency domain analysis device and method for FFT (fast Fourier transform) multimode signals with any length - Google Patents
Frequency domain analysis device and method for FFT (fast Fourier transform) multimode signals with any length Download PDFInfo
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Abstract
The invention discloses an FFT multimode signal frequency domain analysis device and method with any length, belonging to the field of multimode signal frequency domain analysis, wherein the device comprises a 4-frequency division counter, an FFT output data frame counter, a DSP48E adder, a double-port RAM storage unit and a logic shift circuit; the embedded DSP48E adder comprises a DSP48E adder input enable trigger signal module and a DSP48E adder output clear trigger signal module. The invention realizes the requirements of synthesizing the LTE-Advanced Pro baseband signal which is flexible, dynamic and can be loaded in real time; can efficiently support the real-time synthesis processing of LTE-Advanced Pro signals such as 3D/FD-MIMO, Massive CA and the like.
Description
Technical Field
The invention belongs to the field of multimode signal frequency domain analysis, and particularly relates to an FFT multimode signal frequency domain analysis device and method with any length.
Background
The consistency test of the multi-mode multi-frequency terminal is used for verifying the conformity degree of the multi-mode multi-frequency terminal to the standard, is a key protocol regulation for verifying and promoting whether the multi-mode multi-frequency terminal has a commercial level, and is a key means for effectively avoiding protocol understanding errors and effective control of radio frequency indexes when a terminal manufacturer researches and develops terminal equipment. For a terminal manufacturer, the consistency test before network access is carried out on the terminal in the research and development stage, whether the multi-mode multi-frequency terminal product strictly follows the corresponding protocol regulations can be judged, the standard index requirements are met, risks caused by understood access are avoided, the influence on equipment and other terminals after the terminal is connected to the network is avoided, the lengthening of an authentication test period is avoided, the project progress of the manufacturer is seriously influenced, and even the abortion of the project is avoided.
In various detection and verification of multi-mode multi-frequency terminal products, radio frequency consistency test is a key loop, and the design scheme of the whole terminal can be comprehensively checked. Through the test process, terminal research and development and manufacturing enterprises can find problems continuously, solve the problems, improve the design scheme step by step and improve the commercialization degree of the terminal continuously. It can be said that the radio frequency conformance test of the multi-mode multi-frequency terminal is the first step of the multi-mode multi-frequency terminal product really going to the market, and the function of the multi-mode multi-frequency terminal product is irreplaceable.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides the FFT multimode signal frequency domain analysis device and method with any length, which are reasonable in design, overcome the defects of the prior art and have good effects.
In order to achieve the purpose, the invention adopts the following technical scheme:
an FFT multi-mode signal frequency domain analysis device with any length comprises a frequency division 4 counter, an FFT output data frame counter, a DSP48E adder, a double-port RAM storage unit and a logic shift circuit; the embedded DSP48E adder comprises a DSP48E adder input enable trigger signal module and a DSP48E adder output zero clearing trigger signal module;
a divide-by-4 counter configured to divide the data period output by the FFT output data frame counter into 4 uniform slots at equal intervals, including slot 0, slot 1, slot 2, and slot 3; a gap 0 configured to indicate reading of RAM data; gap 1, configured to indicate to read DSP48E adder output data; gap 2, configured to indicate clearing of DSP48E adder output data after the FFT frame accumulator reaches a threshold value; gap 3, configured to instruct writing of DSP48E adder output data to RAM;
the FFT output data frame counter is configured to be used for recording the number of times of FFT frame accumulation, and the FFT frame is conveniently accumulated according to the wireless frame length of the communication signal of the actual standard system;
a DSP48E adder configured to perform an addition operation;
the DSP48E adder input enable trigger signal module is configured to control the DSP48E adder to perform addition operation and update the output value of the DSP48E adder at the output end;
the DSP48E adder output zero clearing trigger signal module is configured to control the output value of the DSP48E adder to be zero;
a dual-port RAM storage unit configured to store the last-time frequency-domain data output by the FFT output data frame counter and the DSP48E adder;
and the logic shifting circuit is configured to divide the accumulated value of the FFT frame.
In addition, the invention also provides a frequency domain analysis method of the FFT multimode signal with any length, which adopts the frequency domain analysis device of the FFT multimode signal with any length, and specifically comprises the following steps:
step 1: initializing output ports of the DSP48E adder and the dual-port RAM storage unit;
step 2: finishing preset actions according to the 4-frequency division counter and the FFT output data frame counter, and specifically comprising the following steps:
step 2.1: when the output value of the 4-frequency division counter is 0 and the count value of the FFT frame accumulation counter is smaller than a preset value, RAM reading operation is carried out through a logic shifting circuit;
step 2.2: when the output value of the 4-frequency division counter is 1 and the count value of the FFT frame accumulation counter is smaller than a preset value, performing addition operation through a logic shift circuit;
step 2.3: when the output value of the 4-frequency division counter is 2 and the count value of the FFT frame accumulation counter is smaller than the preset value, no operation is performed through the logic shift circuit;
step 2.4: when the output value of the 4-frequency division counter is 3 and the count value of the FFT frame accumulation counter is smaller than a preset value, RAM writing operation is carried out through a logic shifting circuit;
step 2.5: when the output value of the 4-frequency division counter is 2 and the count value of the FFT frame accumulation counter is equal to the preset value, the DSP48E adder is cleared through a logic shift circuit, and meanwhile, the final accumulated value is output;
step 2.6: when the output value of the 4-frequency division counter is 3 and the count value of the FFT frame accumulation counter is equal to the preset value, the DSP48E adder completes the RAM zero writing operation and realizes the RAM zero clearing.
The invention has the following beneficial technical effects:
the requirements of synthesizing the LTE-Advanced Pro baseband signals which are flexible, dynamic and capable of being loaded in real time are met; can efficiently support the real-time synthesis processing of LTE-Advanced Pro signals such as 3D/FD-MIMO, Massive CA and the like.
Drawings
Fig. 1 is a schematic block diagram of the apparatus of the present invention.
Fig. 2 is a schematic diagram of a core module design.
FIG. 3 is a schematic diagram of trigger synchronization design.
FIG. 4 is a schematic diagram of a timing control state machine.
Detailed Description
The invention is described in further detail below with reference to the following figures and detailed description:
the invention discloses an FFT frequency domain analysis device with any length, which is used for meeting the LTE-Advanced Pro standard and the 5G air interface signal standard, and the principle is as shown in figure 1, and the FFT frequency domain analysis device mainly comprises the following components: (1) a high-speed clock (clkh) based 4-division counter module (cnt _ xk), (2) a high-speed clock (clkh) based FFT output data frame counter module (cnt _ fr), (3) a high-speed clock (clkh) based DSP48E adder input enable trigger signal module (adder48b _ ce), (4) a high-speed clock (clkh) based DSP48E adder output clear trigger signal module (adder48b _ sclr), (5) a high-speed clock (clkh) based DSP48E adder module (adder48b), (6) a high-speed clock (clkh) based dual-port RAM memory cell module (RAM48x1024), (7) a high-speed clock (clkh) based logic shift circuit module (s _ out), and the like.
The core design idea of the scheme is as follows: by utilizing the mutual cooperation of an adder module (adder48b) and a buffer module (ram48x1024), the cnt _ xk module and the cnt _ fr module are combined with a control logic circuit to respectively generate 4 key control signals: "adder 48b _ ce", "adder 48b _ ce1 d" (adder48b _ ce signal delayed by 1 clkh), "adder 48b _ ce3 d" (adder48b _ ce signal delayed by 3 clkh), and "adder 48b _ sclr" (adder48b _ ce signal delayed by 2 clkh with cnt _ fr being a threshold value). When cnt _ xk is 0, taking RAM data; when cnt _ xk is 1, the output value of the adder is taken to update data; when cnt _ xk is equal to 2 and cnt _ fr is equal to a threshold value, the output data of the adder is cleared; when cnt _ xk is 3, the RAM data is written. The core module design is shown in fig. 2.
The edone signal (slow clk clock domain) is the standard output signal of the FFT module indicating that 1 frame length data is about to start to be output. The edge signal is regarded as a trigger signal by a high-speed clock (clkh), the counter cnt _ xk module is cleared, and as a result, the output value of cnt _ xk is 0, 1, 2, 3, the start position 0 of the counter is always kept synchronous with the FFT output address bus data, namely, the corresponding output value of cnt _ xk is 0, 1, 2, 3 in the xk _ index data holding time period. Similarly, the high-speed clock (clkh) regards the edone signal as a trigger signal to detect and count, and when the count value (frame number) is equal to the preset value (threshold value), the output value of the cnt _ fr module is cleared. The trigger synchronization design is shown in fig. 3.
The specific logic control idea is as follows: when the whole circuit is powered on, the initial state value output by all ports in the chip is 0, so that the internal initial value of the memory cell module (ram48x1024) and the output port (s _ out) of the adder module (adder48b) are also 0. The logic control idea of the design is that, in a period (equivalent to 4 period lengths of cnt _ xk) in which the value of the xk _ index is kept unchanged, the following operations are accurately and unmistakably performed by using the synchronization relationship between cnt _ xk and xk _ index: 1) fetching data from a storage unit; 2) taking out data and adding corresponding FFT output data at the moment; 3) and the output result of the addition operation at the next moment is stored in the RAM for temporary storage. The operation is repeated and circulated until the value of the frame counter is equal to the set threshold value, and the operation steps are changed into: 1) fetching data from a storage unit; 2) taking out data and adding corresponding FFT output data at the moment; 3) the final output of the whole device is carried out on the output result (the final accumulation result value) of the addition operation at the next moment, and the output result of the adder is cleared; 4) the output result of the addition operation at the next moment (which is cleared at the moment) is stored in the RAM for temporary storage. The timing control state machine design is shown in fig. 4.
The invention provides an FFT frequency domain analysis method with any length, which is used for meeting the LTE-Advanced Pro standard and the 5G air interface signal standard, and specifically comprises the following steps:
step 1: initializing output ports of the DSP48E adder and the dual-port RAM storage unit;
step 2: finishing preset actions according to the 4-frequency division counter and the FFT output data frame counter, and specifically comprising the following steps:
step 2.1: when the output value of the 4-frequency division counter is 0 and the count value of the FFT frame accumulation counter is smaller than a preset value, RAM reading operation is carried out through a logic shifting circuit;
step 2.2: when the output value of the 4-frequency division counter is 1 and the count value of the FFT frame accumulation counter is smaller than a preset value, performing addition operation through a logic shift circuit;
step 2.3: when the output value of the 4-frequency division counter is 2 and the count value of the FFT frame accumulation counter is smaller than the preset value, no operation is performed through the logic shift circuit;
step 2.4: when the output value of the 4-frequency division counter is 3 and the count value of the FFT frame accumulation counter is smaller than a preset value, RAM writing operation is carried out through a logic shifting circuit;
step 2.5: when the output value of the 4-frequency division counter is 2 and the count value of the FFT frame accumulation counter is equal to the preset value, the DSP48E adder is cleared through a logic shift circuit, and meanwhile, the final accumulated value is output;
step 2.6: when the output value of the 4-frequency division counter is 3 and the count value of the FFT frame accumulation counter is equal to the preset value, the DSP48E adder completes the RAM zero writing operation and realizes the RAM zero clearing.
The method has clear principle and reasonable architecture, and is mainly characterized in that:
1. based on an FPGA platform, an FFT processing unit, an embedded double-port RAM, an embedded DSP48E adder and the like are adopted to realize frequency domain data iterative processing design;
2. an FPGA logic unit circuit is adopted to realize the iteration/accumulation times of parameter control which can change in real time, and the arbitrary change design of the FFT time domain big data processing length is met;
3. and a low-speed working main clock and high-speed iteration auxiliary clock combined processing mode is adopted, so that the accumulation processing of the current frequency domain data and the last frequency domain data is ensured to be completed in a low-speed data working time window, and the working state of the data is updated in real time relative to the working main clock.
The invention adopts the following scheme in the aspect of solving the technical problem:
based on a software radio theory, a digital signal processing method and an embedded development technology, the method is applied to the LTE-Advanced Pro mobile communication standard mapping test technology; and carrying out real-time spectrum analysis on 3GPP standard signals such as LTE-Advanced Pro/LTE-Advanced/LTE/WCDMA/TD-SCDMA/GSM and other signals of any system in a signaling working mode or a non-signaling working mode. Especially for the digital signal spectrum analysis with large bandwidth and high sampling rate, the method effectively overcomes the limitation that the maximum point of the processing depth of an embedded FFT processing unit in the FPGA is fixed. The scheme utilizes a small FFT processing unit with limited length, combines a RAM and a high-speed hard-wire adder module, and constructs a spectrum analysis device capable of processing signals with any length through an iterative algorithm logic circuit.
It is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make modifications, alterations, additions or substitutions within the spirit and scope of the present invention.
Claims (2)
1. An arbitrary length FFT multimode signal frequency domain analysis device is characterized in that: the system comprises a 4-frequency division counter module based on a high-speed clock (clkh), an FFT output data frame counter module based on the high-speed clock (clkh), a DSP48E adder input enabling trigger signal module based on the high-speed clock (clkh), a DSP48E adder output clearing trigger signal module based on the high-speed clock (clkh), a DSP48E adder module based on the high-speed clock (clkh), a dual-port RAM storage unit module based on the high-speed clock (clkh) and a logic shift circuit module based on the high-speed clock (clkh);
a high speed clock (clkh) based divide-by-4 counter module configured for equally dividing the data period output by the high speed clock (clkh) based FFT output data frame counter module into 4 uniform slots including slot 0, slot 1, slot 2 and slot 3; a gap 0 configured to indicate reading of RAM data; slot 1, configured to indicate to read the high speed clock (clkh) based DSP48E adder module output data; gap 2 configured to indicate clearing of high speed clock (clkh) based DSP48E adder module output data after the FFT frame accumulator reaches a threshold value; slot 3, configured to instruct the high speed clock (clkh) based DSP48E adder module output data to be written to RAM;
the FFT output data frame counter module based on a high-speed clock (clkh) is configured to be used for recording the number of times of FFT frame accumulation, and is convenient for accumulating the FFT frame according to the wireless frame length of the communication signal of an actual standard system;
a high speed clock (clkh) based DSP48E adder module configured to perform addition operations;
a high speed clock (clkh) based DSP48E adder input enable trigger signal block configured to control a high speed clock (clkh) based DSP48E adder block to perform addition operations and update at an output a high speed clock (clkh) based DSP48E adder block output value;
a high speed clock (clkh) based DSP48E adder output clear trigger signal module configured to control the output value of the high speed clock (clkh) based DSP48E adder module to be cleared;
a high speed clock (clkh) based dual port RAM memory cell module configured for storing the last time frequency domain data output by the high speed clock (clkh) based FFT output data frame counter module and the high speed clock (clkh) based DSP48E adder module;
a high speed clock (clkh) based logic shift circuit module configured to divide the accumulated value of the FFT frame.
2. A frequency domain analysis method for FFT multimode signals with any length is characterized in that: the frequency domain analysis device for the FFT multimode signal with arbitrary length according to claim 1, comprising the following steps:
step 1: initializing output ports of the DSP48E adder module based on a high-speed clock (clkh) and the dual-port RAM memory unit module based on the high-speed clock (clkh);
step 2: the method comprises the following steps of finishing preset actions according to a 4-frequency division counter module based on a high-speed clock (clkh) and an FFT output data frame counter module based on the high-speed clock (clkh), and specifically comprising the following steps:
step 2.1: when the output value of the 4-frequency division counter module based on the high-speed clock (clkh) is 0 and the count value of the FFT frame accumulation counter is smaller than a preset value, the RAM reading operation is carried out through the logic shift circuit module based on the high-speed clock (clkh);
step 2.2: when the output value of the 4-frequency division counter module based on the high-speed clock (clkh) is 1 and the count value of the FFT frame accumulation counter is smaller than a preset value, performing addition operation through a logic shift circuit module based on the high-speed clock (clkh);
step 2.3: when the output value of the 4-frequency division counter module based on the high-speed clock (clkh) is 2 and the count value of the FFT frame accumulation counter is smaller than the preset value, the logic shift circuit module based on the high-speed clock (clkh) does no operation;
step 2.4: when the output value of the 4-frequency division counter module based on the high-speed clock (clkh) is 3 and the count value of the FFT frame accumulation counter is smaller than a preset value, performing RAM write operation through the logic shift circuit module based on the high-speed clock (clkh);
step 2.5: when the output value of the 4-frequency division counter module based on the high-speed clock (clkh) is 2 and the count value of the FFT frame accumulation counter is equal to the preset value, carrying out zero clearing operation on the DSP48E adder module based on the high-speed clock (clkh) through the logic shift circuit module based on the high-speed clock (clkh), and simultaneously outputting a final accumulated value;
step 2.6: when the output value of the 4-frequency division counter module based on the high-speed clock (clkh) is 3 and the count value of the FFT frame accumulation counter is equal to the preset value, the DSP48E adder module based on the high-speed clock (clkh) completes the RAM zero writing operation, and the RAM zero clearing is realized.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101091209A (en) * | 2005-09-02 | 2007-12-19 | 日本电气株式会社 | Noise suppressing method and apparatus and computer program |
| CN101881796A (en) * | 2010-06-30 | 2010-11-10 | 天津市德力电子仪器有限公司 | Frequency counting module and counting method and application |
| WO2011101305A1 (en) * | 2010-02-19 | 2011-08-25 | Telefonaktiebolaget L M Ericsson (Publ) | Down-conversion using square wave local oscillator signals |
| CN102497200A (en) * | 2011-12-13 | 2012-06-13 | 东南大学 | Clock signal loss detecting circuit and clock signal loss detecting method |
| CN102751983A (en) * | 2012-07-30 | 2012-10-24 | 中国电子科技集团公司第四十一研究所 | Multi-loop synthesized local oscillation device of TD-LTE (time division-long term evolution) comprehensive test instrument |
| CN103414469A (en) * | 2013-06-27 | 2013-11-27 | 深圳市创成微电子有限公司 | RFID fractional-N PLL technology |
| CN106712779A (en) * | 2016-12-16 | 2017-05-24 | 中国电子科技集团公司第四十研究所 | FPGA + DSP hardware architecture method for testing consistency of 32-antenna multimode radio frequency |
-
2018
- 2018-12-07 CN CN201811491638.4A patent/CN109613336B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101091209A (en) * | 2005-09-02 | 2007-12-19 | 日本电气株式会社 | Noise suppressing method and apparatus and computer program |
| WO2011101305A1 (en) * | 2010-02-19 | 2011-08-25 | Telefonaktiebolaget L M Ericsson (Publ) | Down-conversion using square wave local oscillator signals |
| CN101881796A (en) * | 2010-06-30 | 2010-11-10 | 天津市德力电子仪器有限公司 | Frequency counting module and counting method and application |
| CN102497200A (en) * | 2011-12-13 | 2012-06-13 | 东南大学 | Clock signal loss detecting circuit and clock signal loss detecting method |
| CN102751983A (en) * | 2012-07-30 | 2012-10-24 | 中国电子科技集团公司第四十一研究所 | Multi-loop synthesized local oscillation device of TD-LTE (time division-long term evolution) comprehensive test instrument |
| CN103414469A (en) * | 2013-06-27 | 2013-11-27 | 深圳市创成微电子有限公司 | RFID fractional-N PLL technology |
| CN106712779A (en) * | 2016-12-16 | 2017-05-24 | 中国电子科技集团公司第四十研究所 | FPGA + DSP hardware architecture method for testing consistency of 32-antenna multimode radio frequency |
Non-Patent Citations (2)
| Title |
|---|
| 《TD-LTE终端射频一致性检测》;鲍大志等;《现代电信科技》;20150630;全文 * |
| 《Using calibration methods for the verification of NFC RF Conformance Test Tool》;Qian Sun等;《IEEE》;20141002;全文 * |
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