CN109585538A - Semiconductor devices and its manufacturing method - Google Patents
Semiconductor devices and its manufacturing method Download PDFInfo
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- CN109585538A CN109585538A CN201811474149.8A CN201811474149A CN109585538A CN 109585538 A CN109585538 A CN 109585538A CN 201811474149 A CN201811474149 A CN 201811474149A CN 109585538 A CN109585538 A CN 109585538A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000463 material Substances 0.000 claims description 53
- 239000004020 conductor Substances 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 34
- 238000000926 separation method Methods 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000010894 electron beam technology Methods 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 claims description 5
- 229910021389 graphene Inorganic materials 0.000 claims description 5
- 241000219289 Silene Species 0.000 claims description 4
- 229910052918 calcium silicate Inorganic materials 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 abstract description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 166
- 239000003989 dielectric material Substances 0.000 description 19
- 238000010586 diagram Methods 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 238000005530 etching Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000002210 silicon-based material Substances 0.000 description 7
- 239000012212 insulator Substances 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 238000000609 electron-beam lithography Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 239000007769 metal material Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000000427 thin-film deposition Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 150000001336 alkenes Chemical class 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
This application provides a kind of semiconductor devices and its manufacturing methods.In the semiconductor device, backgate is only located on gate electrode contact layer localized area.That is, the backgate is local backgate, the part backgate is only located at the region between source-drain electrode, so, the part back grid structure overcomes the defect that traditional global backgate cannot be controlled independently, is conducive to the integrated level of semiconductor devices, in addition, metal using heavy doping or is used using the part backgate, so the driveability for the semiconductor devices being somebody's turn to do is also preferable.
Description
Technical field
This application involves technical field of semiconductors more particularly to a kind of semiconductor devices and its manufacturing methods.
Background technique
Compared to silicon materials, such as electron transfer with higher such as graphene, black phosphorus and silene of two-dimensional semiconductor material
Rate, therefore, two-dimensional semiconductor material are possible to the channel layer materials that silicon materials can be replaced to become in the following large scale integrated circuit.
However, the intensity of single layer two-dimensional semiconductor material is little, therefore, using single layer two-dimensional semiconductor material as channel
Requirement of the semiconductor devices of layer to many process is more tightened up and harsh than traditional silicon channel layer semiconductor devices.
Based on this, currently, using single layer two-dimensional semiconductor material as the semiconductor devices of channel layer, grid is mainly adopted
With global back grid structure.And have the size of the semiconductor devices of global back grid structure larger, it is unfavorable for improving semiconductor devices
Integrated level.Moreover, having the driveability of the semiconductor devices of global back grid structure poor.
Summary of the invention
In view of this, this application provides a kind of semiconductor devices and its manufacturing method, to improve the drive of semiconductor devices
Dynamic performance, and be conducive to improve the integrated level of semiconductor devices.
In order to solve the above-mentioned technical problem, the application adopts the technical scheme that
A kind of semiconductor devices, comprising:
Substrate；
Positioned at the gate electrode contact layer of the substrate；
Backgate on the gate electrode contact layer regional area；
Around the backgate and positioned at the isolation of the overlying regions in addition to the gate electrode contact layer regional area
Layer；
Gate dielectric layer on the backgate and the separation layer；
Two-dimensional semiconductor material layer on the gate dielectric layer；
The source electrode being in electrical contact on the two-dimensional semiconductor material layer and with the two-dimensional semiconductor material layer and leakage
Pole；The source electrode and drain electrode is located at the two sides of the backgate.
Optionally, the material of the two-dimensional semiconductor material layer is selected from least one of graphene, black phosphorus or silene.
Optionally, the gate dielectric layer is oxide layer or high K medium material layer.
Optionally, the backgate and the gate electrode contact layer are an integral molding structure.
Optionally, the width of the backgate is 10~100nm.
A kind of manufacturing method of semiconductor devices, which comprises
Substrate is provided；
It forms gate electrode contact layer over the substrate and backgate, the backgate is located at the part of the gate electrode contact layer
Overlying regions；
Around the backgate and it is located at the overlying regions formation isolation in addition to the gate electrode contact layer regional area
Layer；
Gate dielectric layer is formed above the backgate and the separation layer；
Two-dimensional semiconductor material layer is formed on the gate medium；
Source electrode and drain electrode, the source electrode and leakage are respectively formed on the two-dimensional semiconductor material layer of the two sides of the backgate
Pole and the two-dimensional semiconductor material layer are in electrical contact.
Optionally, described to form gate electrode contact layer and backgate over the substrate, it specifically includes:
Conductive material layer is formed over the substrate；
The first figure is formed in the top of the conductive material layer by side wall shifting process, then, according to described first
Conductive material layer described in pattern etching, to make the conductive material layer form gate electrode contact layer and protrude from the gate electrode
Backgate on contact layer regional area.
Optionally, described to form gate electrode contact layer and backgate over the substrate, it specifically includes:
Conductive material layer is formed over the substrate；
Second graph is formed in the top of the conductive material layer by electron beam, and passes through removing or dry etch process
It gets rid of except the conductive material layer outside the second graph, so that the conductive material layer be made to form gate electrode contact layer
And protrude from backgate on the gate electrode contact layer regional area.
Optionally, described to form gate dielectric layer above the backgate and the separation layer, it specifically includes:
By atom layer deposition process in the backgate and the separation layer disposed thereon high K medium material layer, the high k
Layer of dielectric material is the gate dielectric layer.
Optionally, the backgate is made of low-resistance silicon, described to form gate medium above the backgate and the separation layer
Layer, specifically includes:
Using oxidation technology, gate dielectric layer is formed above the backgate and the separation layer.
Compared to the prior art, the application has the advantages that
Based on above technical scheme it is found that in semiconductor devices provided by the present application, backgate is only located at gate electrode contact layer
On localized area.That is, the backgate is local backgate, which is only located at the region between source-drain electrode, in this way,
The part back grid structure overcomes the defect that traditional global backgate cannot be controlled independently, is conducive to the integrated of semiconductor devices
Degree heavy doping or uses metal in addition, using using the part backgate, thus the driveability for the semiconductor devices being somebody's turn to do also compared with
It is good.
Detailed description of the invention
In order to which the specific embodiment of the application is expressly understood, used when the application specific embodiment is described below
Attached drawing do a brief description.
Fig. 1 is the structural schematic diagram of semiconductor devices provided by the embodiments of the present application；
Fig. 2 is method, semi-conductor device manufacturing method flow diagram provided by the embodiments of the present application；
Fig. 3 (1) to Fig. 3 (6) is that a series of processing procedures of method, semi-conductor device manufacturing method provided by the embodiments of the present application are corresponding
The schematic diagram of the section structure.
Specific embodiment
It is based on background technology part it is found that existing using single layer two-dimensional semiconductor material as the semiconductor device of channel layer
Part is unfavorable for improving the integrated level of semiconductor devices, and driveability is poor.
In order to improve using single layer two-dimensional semiconductor material as the integrated level of the semiconductor devices of channel layer and driving
Performance, this application provides a kind of semiconductor devices, the gate structure of the semiconductor devices is back grid structure, and the back grid structure
It is only located on gate electrode contact layer localized area.That is, the backgate is local backgate, which is only located at source and drain
It is improved in this way, the part back grid structure overcomes the defect that traditional global backgate cannot be controlled independently in region between pole
The integrated level of semiconductor devices, in addition, this has the driveability of the semiconductor devices of local backgate also preferable.
In order to which the specific embodiment of the application is expressly understood, with reference to the accompanying drawing to provided by the embodiments of the present application half
The specific structure of conductor device is described in detail.
Referring to Figure 1, semiconductor devices provided by the embodiments of the present application includes:
Substrate 101；
Gate electrode contact layer 102 on substrate 101；
Backgate 103 on 102 regional area of gate electrode contact layer；
Around backgate 103 and positioned at the separation layer of the overlying regions in addition to 102 regional area of gate electrode contact layer
104；
Gate dielectric layer 105 on backgate 103 and separation layer 104；
Two-dimensional semiconductor material layer 106 on gate dielectric layer 105；
The source electrode 107 being in electrical contact on two-dimensional semiconductor material layer 106 and with two-dimensional semiconductor material layer 106 and leakage
Pole 108；Source electrode 107 and drain electrode 108 are located at the two sides of backgate 103.
In the embodiment of the present application, substrate 101 can be semiconductor substrate, such as can be Si substrate, Ge substrate, SiGe
Substrate, SOI (silicon-on-insulator, Silicon On Insulator) or GOI (germanium on insulator, Germanium On
Insulator) etc..In other embodiments, the semiconductor substrate can also be include other elements semiconductor or compound
The substrate of semiconductor, such as GaAs, InP or SiC etc. can also be laminated construction, such as Si/SiGe etc. can be outside other
Prolong structure, such as SGOI (silicon germanium on insulator) etc..In the specific embodiment, the substrate 101 is body silicon substrate.
As more specific example, substrate 101 can be polycrystalline silicon material.
Gate electrode contact layer 102 can be made of heavily-doped semiconductor material or metal material.Backgate 103 can also be with
It is made of heavily-doped semiconductor material or metal material.As more specific example, gate electrode contact layer 102 and backgate 103
It can be made of low-resistance silicon materials.In order to realize each unit independent control in device, and then improve semiconductor devices
Integrated level, the width of the backgate 103 can be nanoscale, and the local back grid structure of nanoscale can effectively inhibit defect and miscellaneous
Matter scatters the influence for mobility, ensure that two-dimensional semiconductor material layer 106 has ultra thin channel, high mobility, energy band can
The intrinsic features such as tune, so as to improve driving and the controllability of device.Width as more specific example, the backgate 103 can
In 10~100nm.
As the specific example of the application, in order to simplify device fabrication, gate electrode contact layer 102 and backgate 104
It can be an integral molding structure.
As another specific example of the application, separation layer 104 can be made of earth silicon material.
As the another example of the application, gate dielectric layer 105 can be oxide layer or high K medium material layer.
Wherein, when the material of backgate 103 is low-resistance silicon materials, gate dielectric layer 105 can be by aoxidizing low-resistance silicon
Technique is formed.In addition, the performance of semiconductor devices so can be improved when gate dielectric layer 105 is that high K dielectric material is made.
Optionally, when gate dielectric layer 105 is made of high K dielectric material, can by atom layer deposition process or
Other thin film deposition processes form gate dielectric layer 105.
As the another example of the application, the material of two-dimensional semiconductor material layer 106 can be selected from graphene, black phosphorus or silicon
At least one of alkene.
Source electrode 107 and drain electrode 108 can be made of metal material.
The above are the specific implementations of semiconductor devices provided by the embodiments of the present application.In the specific implementation,
The gate structure of the semiconductor devices is back grid structure, and the back grid structure is only located on gate electrode contact layer localized area.
That is, the backgate is local backgate, which is only located at the region between source-drain electrode, in this way, the part backgate knot
Structure overcomes the defect that traditional global backgate cannot be controlled independently, the integrated level of semiconductor devices is improved, in addition, the office
The width of portion's backgate can control in nanoscale, and it can be made using heavy doping or using metal, should so having
The driveability of semiconductor devices with local backgate is also preferable.
The semiconductor devices provided based on the above embodiment, correspondingly, present invention also provides the systems of the semiconductor devices
Make method.
Refer to Fig. 2 to Fig. 3 (6), the manufacturing method of semiconductor devices provided by the embodiments of the present application the following steps are included:
S201: substrate is provided.
Fig. 3 (1) shows the structural schematic diagram of substrate 101.
S202: it forms gate electrode contact layer over the substrate and backgate, the backgate is located at the gate electrode contact layer
Regional area above.
It is to be appreciated that in the embodiment of the present application, gate electrode contact layer and backgate can use metal or low-resistance silicon material
Material is made.In addition, gate electrode contact layer and backgate can be an integral molding structure for simplification of flowsheet.
In addition, for the lesser backgate of formation width size, and then improve the integrated level and driven nature of semiconductor devices
Can, backgate can be formed using side wall shifting process or electron beam technology.
As an example, when forming backgate using side wall shifting process, S202 can with specifically includes the following steps:
A1: conductive material layer 301 is formed on substrate 101.
This step can be with specifically: forms low-resistance silicon by thin film deposition processes on substrate 101 or electroplating technology is formed
Metal layer, the low-resistance silicon or metal layer of formation are conductive material layer 301, which has executed corresponding the schematic diagram of the section structure
As shown in Fig. 3 (2-1).
A2: forming sacrificial layer, and etching sacrificial layer on 301 surface of conductive material layer, thus in conductive material layer 301
The first figure 302 is formed in local surfaces.
This step can be with specifically: and silicon nitride layer is formed on 301 surface of conductive material layer, and etches the silicon nitride layer,
To form the first figure 302 in the local surfaces of conductive material layer 301.
The step has executed shown in corresponding the schematic diagram of the section structure such as Fig. 3 (2-2).
A3: the conductive material layer not covered in the upper surface of the first figure 302 and side and by the first figure 302
Layer of dielectric material 303 is formed on 301 surface.
This step can be with specifically: use low-pressure chemical vapor deposition (LPCVD) the upper surface in the first figure 302 with
And layer of dielectric material 303 is formed on side and the surface for the conductive material layer 301 not covered by the first figure 302.The medium
The material of material layer 303 can be silica.
It is to be appreciated that in this step, can control the thickness for being formed in the layer of dielectric material 303 of 302 side of the first figure
Degree.Optionally, it will be formed in the thickness control of the layer of dielectric material 303 of 302 side of the first figure in nanoscale, more specifically
Ground, which can be between 10~100nm.
The step has executed shown in corresponding the schematic diagram of the section structure such as Fig. 3 (2-3).
A4: 302 upper surface of the first figure is etched away using dry etch process and is not led by what the first figure 302 covered
Layer of dielectric material 303 is formed on the surface of material layer 301, thus retain the layer of dielectric material 303 of 302 side of the first figure,
The layer of dielectric material 303 for being retained in 302 side of the first figure is side wall 304.
This step can be with specifically: etches away the first figure 302 using anisotropic reactive ion etching (RIE) technique
Layer of dielectric material 303 is formed on upper surface and the surface for the conductive material layer 301 not covered by the first figure 302, to protect
The layer of dielectric material 303 for staying 302 side of the first figure, the layer of dielectric material 303 for being retained in 302 side of the first figure is side wall
304。
It is to be appreciated that because of the anisotropy of reactive ion etching process, in its etching 302 upper surface of the first figure and not
When forming layer of dielectric material 303 on the surface of the conductive material layer 301 covered by the first figure 302, it will not etch away and be formed in
Layer of dielectric material 303 on first figure, 302 side, therefore, the layer of dielectric material 303 of 302 side of the first figure remain,
To form the lesser side wall 304 of width in the top of conductive material layer 301.
The step has executed shown in corresponding the schematic diagram of the section structure such as Fig. 3 (2-4).
A5: being mask, etch conductive layer 301 to certain thickness, thus in conductive material layer 301 with side wall 304
Top half forms fin-shaped grid, and the lower half portion for the conductive material layer 301 not being etched forms grid contact layer 102, wherein fin
Shape grid is backgate 103.
This step can be with specifically: with side wall 304 is mask, using dry etch process such as reactive ion etching process
Etch conductive layer 301 is not carved to certain thickness so that the top half in conductive material layer 301 forms fin-shaped grid
The lower half portion of the conductive material layer 301 of erosion forms grid contact layer 102, wherein fin-shaped grid is backgate 103.
It is to be appreciated that backgate 103, which is with side wall 304, is that mask is formed, so, the width of backgate 103 and side wall 304
Of same size, because the width of the side wall 304 of above-mentioned formation can be nanoscale, therefore, the width of backgate 103 is also a nanometer ruler
Degree, more specifically, the width of the backgate 103 can be between 10~100nm.
The step has executed shown in corresponding the schematic diagram of the section structure such as Fig. 3 (2-5).
Because the precision of electron beam is higher, critical size can achieve 20nm, therefore, as another example of S202,
Backgate can be formed by electron beam lithography technique.
It is to be appreciated that electron beam lithography technique is identical as traditional etching technics.It is described below in detail and is carved by electron beam
The specific implementation of etching technique formation backgate.As an example, when forming backgate by electron beam lithography technique, S202 can be with
The following steps are included:
B1: conductive material layer 301 is formed on substrate 101.
The specific implementation of the step is identical as above-mentioned A1, for the sake of brevity, is not described in detail herein.
B2: forming sacrificial layer on 301 surface of conductive material layer, and use electron beam lithography technique etching sacrificial layer, from
And second graph 302 ' is formed in the local surfaces of conductive material layer 301.
This step can be with specifically: forms sacrificial layer on 301 surface of conductive material layer first, is then carved using electron beam
Etching technique etching sacrificial layer, so that the sacrificial layer after etching be made to form second graph 302 ', which is located at electric material
In the local surfaces of the bed of material 301.
It is to be appreciated that in order to control the width for the backgate being subsequently formed, the width of the second graph 302 of formation is nanometer ruler
Degree, specifically, the width of the second graph 302 can be between 10~100nm.
B 3: with second graph 302 ' for mask, etch conductive layer 301 to certain thickness, thus in conductive material layer
301 top half forms fin-shaped grid, and the lower half portion for the conductive material layer 301 not being etched forms grid contact layer 102,
In, fin-shaped grid is backgate 103.
S203: it is formed around the backgate and positioned at the overlying regions in addition to the gate electrode contact layer regional area
Separation layer.
This step can be with specifically: around to backgate 103 and is located in addition to 102 regional area of gate electrode contact layer
Region on fill silica, and by CMP process, polish silica surface, and get rid of side wall
304, thus around backgate 103 and be located at overlying regions in addition to 102 regional area of gate electrode contact layer formed every
Absciss layer 104.
The step has executed shown in corresponding the schematic diagram of the section structure such as Fig. 3 (3).
S204: gate dielectric layer is formed above the backgate and the separation layer.
As an example, this step can be with specifically: using atom layer deposition process in backgate 103 and separation layer 104
One layer of dielectric material of disposed thereon, to form gate dielectric layer 105.
It is to be appreciated that the dielectric material of deposition can be silica, or high K dielectric material.
It as another example, can be by the technique that is aoxidized to low-resistance silicon described when backgate is made of low-resistance silicon
Gate dielectric layer 105 is formed above backgate 103.The step has executed shown in corresponding the schematic diagram of the section structure such as Fig. 3 (4).
S205: two-dimensional semiconductor material layer is formed on the gate dielectric layer.
This step can be with specifically: one layer of two-dimensional semiconductor material layer 106 is shifted on gate dielectric layer 105, as showing
The material of example, the two-dimensional semiconductor material layer 106 is selected from least one of graphene, black phosphorus or silene.
The step has executed shown in corresponding the schematic diagram of the section structure such as Fig. 3 (5).
S206: source electrode and drain electrode, the source are respectively formed on the two-dimensional semiconductor material layer of the two sides of the backgate
Pole and drain electrode are in electrical contact with the two-dimensional semiconductor material layer.
This step can be with specifically: one layer of gold is deposited in two-dimensional semiconductor material layer 106 by thermal evaporation process first
Belong to layer, the metal layer above 106 part of the surface of two-dimensional semiconductor material layer is then got rid of by stripping technology, thus in backgate
Source electrode 107 and drain electrode 108 are respectively formed on the two-dimensional semiconductor material layer 106 of 103 two sides.
The step has executed shown in corresponding the schematic diagram of the section structure such as Fig. 3 (6).
It is to be appreciated that being based on above-mentioned manufacturing process, two backgates 103 are formd above gate contact layer 102, accordingly
Ground includes two device cells in semiconductor devices shown in Fig. 3 (6).Wherein, structure such as Fig. 1 including a device cell
It is shown.
The above are the specific implementations of method, semi-conductor device manufacturing method provided by the embodiments of the present application.
Claims (10)
1. a kind of semiconductor devices characterized by comprising
Substrate；
Positioned at the gate electrode contact layer of the substrate；
Backgate on the gate electrode contact layer regional area；
Around the backgate and positioned at the separation layer of the overlying regions in addition to the gate electrode contact layer regional area；
Gate dielectric layer on the backgate and the separation layer；
Two-dimensional semiconductor material layer on the gate dielectric layer；
Source electrode and drain electrode on the two-dimensional semiconductor material layer and with two-dimensional semiconductor material layer electrical contact；Institute
State the two sides that source electrode and drain electrode is located at the backgate.
2. semiconductor devices according to claim 1, which is characterized in that the material of the two-dimensional semiconductor material layer is selected from
At least one of graphene, black phosphorus or silene.
3. semiconductor devices according to claim 1, the gate dielectric layer is oxide layer or high K medium material layer.
4. semiconductor devices according to claim 1, which is characterized in that the backgate and the gate electrode contact layer are one
Forming structure.
5. semiconductor devices according to claim 1, which is characterized in that the width of the backgate is 10~100nm.
6. a kind of manufacturing method of semiconductor devices, which is characterized in that the described method includes:
Substrate is provided；
It forms gate electrode contact layer over the substrate and backgate, the backgate is located at the regional area of the gate electrode contact layer
Top；
Around the backgate and it is located at the overlying regions formation separation layer in addition to the gate electrode contact layer regional area；
Gate dielectric layer is formed above the backgate and the separation layer；
Two-dimensional semiconductor material layer is formed on the gate medium；
Be respectively formed source electrode and drain electrode on the two-dimensional semiconductor material layer of the two sides of the backgate, the source electrode and drain electrode with
The two-dimensional semiconductor material layer electrical contact.
7. according to the method described in claim 6, it is characterized in that, described form gate electrode contact layer and back over the substrate
Grid specifically include:
Conductive material layer is formed over the substrate；
The first figure is formed in the top of the conductive material layer by side wall shifting process, then, according to first figure
The conductive material layer is etched, to make the conductive material layer form gate electrode contact layer and protrude from the gate electrode contact
Backgate on layer regional area.
8. according to the method described in claim 6, it is characterized in that, described form gate electrode contact layer and back over the substrate
Grid specifically include:
Conductive material layer is formed over the substrate；
Second graph is formed in the top of the conductive material layer by electron beam, and passes through removing or dry etch process removal
Fall except the conductive material layer outside the second graph, thus make the conductive material layer formed gate electrode contact layer and
Protrude from the backgate on the gate electrode contact layer regional area.
9. according to the method described in claim 6, it is characterized in that, described form grid above the backgate and the separation layer
Dielectric layer specifically includes:
By atom layer deposition process in the backgate and the separation layer disposed thereon high K medium material layer, the high K medium
Material layer is the gate dielectric layer.
10. described in the backgate according to the method described in claim 6, it is characterized in that, the backgate is made of low-resistance silicon
With formation gate dielectric layer above the separation layer, specifically include:
Using oxidation technology, gate dielectric layer is formed above the backgate and the separation layer.
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