CN109545750B - Method for manufacturing thin film transistor substrate and thin film transistor substrate - Google Patents
Method for manufacturing thin film transistor substrate and thin film transistor substrate Download PDFInfo
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- CN109545750B CN109545750B CN201811167707.6A CN201811167707A CN109545750B CN 109545750 B CN109545750 B CN 109545750B CN 201811167707 A CN201811167707 A CN 201811167707A CN 109545750 B CN109545750 B CN 109545750B
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- 239000000758 substrate Substances 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 239000010409 thin film Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 57
- 239000002184 metal Substances 0.000 claims abstract description 57
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000002161 passivation Methods 0.000 claims description 25
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 6
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 6
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000005289 physical deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides a manufacturing method of a thin film transistor substrate, which comprises the following steps: forming a first metal layer on a substrate; etching the first metal layer to form a grid; forming a gate insulating layer covering the gate electrode on the substrate; forming a semiconductor layer on the gate insulating layer; forming a second metal layer on the semiconductor layer and the gate insulating layer; etching the second metal layer to form a source electrode, a drain electrode and a pixel electrode; wherein the second metal layer is made of a transparent conductive material. Has the advantages that: the second metal layer is made of transparent conductive metal, so that the drain electrode can be directly extended to serve as a pixel electrode, and the source electrode, the drain electrode and the pixel electrode are formed through the same etching process, so that the manufacturing procedures are reduced, and the production cost, the manufacturing time and the complexity are reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a manufacturing method of a thin film transistor substrate and the thin film transistor substrate.
Background
In the prior art, in the manufacture of the thin film transistor array substrate, a plurality of processes (for example, four processes) are required, and the more processes are required, the higher the production cost of the thin film transistor array substrate is, and the processing time and the complexity are increased.
Disclosure of Invention
The invention provides a manufacturing method of a thin film transistor substrate, which aims to solve the technical problem that the manufacturing cost of the thin film transistor substrate is higher due to more required manufacturing processes in the conventional manufacturing method of the thin film transistor substrate.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
a method for manufacturing a thin film transistor substrate comprises the following steps:
s10, forming a first metal layer on the substrate;
s20, etching the first metal layer to form a grid;
s30, forming a gate insulating layer covering the gate on the substrate;
s40, forming a semiconductor layer on the gate insulating layer;
s50, forming a second metal layer on the semiconductor layer and the gate insulating layer;
s60, etching the second metal layer to form a source electrode, a drain electrode and a pixel electrode;
wherein the second metal layer is made of a transparent conductive material.
Preferably, the method for manufacturing a thin film transistor substrate further includes:
and S70, forming a passivation layer covering the source electrode and the drain electrode on the gate insulating layer.
Preferably, the passivation layer covers the pixel electrode, and the method for manufacturing the thin film transistor substrate further includes:
and S80, forming a through hole on the passivation layer to expose the pixel electrode.
Preferably, the thickness of the second metal layer is greater than or equal to half of the thickness of the passivation layer.
Preferably, the transparent conductive material is indium tin oxide, indium zinc oxide or indium tin zinc oxide.
The invention also provides a manufacturing method of the thin film transistor substrate, which comprises the following steps:
a substrate;
a gate electrode disposed on the substrate;
a gate insulating layer disposed on the substrate and covering the gate electrode;
a semiconductor layer disposed on the gate insulating layer;
a second metal layer disposed on the gate insulating layer, the second metal layer including a source electrode, a drain electrode, and a pixel electrode;
the source electrode, the drain electrode and the pixel electrode are all made of transparent conductive materials.
Preferably, the thin film transistor substrate further includes a passivation layer disposed on the gate insulating layer and covering the source electrode and the drain electrode.
Preferably, a through hole exposing the pixel electrode is provided on the passivation layer.
Preferably, the thickness of the second metal layer is greater than or equal to half of the thickness of the passivation layer.
Preferably, the transparent conductive material is indium tin oxide, indium zinc oxide or indium tin zinc oxide.
The invention has the beneficial effects that: the second metal layer is made of transparent conductive metal, so that the drain electrode can be directly extended to serve as a pixel electrode, and the source electrode, the drain electrode and the pixel electrode are formed through the same etching process, so that the manufacturing procedures are reduced, and the production cost, the manufacturing time and the complexity are reduced.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic view of a process for fabricating a thin film transistor substrate according to an embodiment of the present invention;
FIG. 2 is a schematic illustration of the formation of a gate and a gate insulating layer in accordance with an embodiment of the present invention;
FIG. 3 is a schematic illustration of the formation of a semiconductor layer in accordance with an embodiment of the present invention;
FIG. 4 is a diagram illustrating the formation of a second metal layer according to one embodiment of the present invention;
FIG. 5 is a schematic diagram of forming source, drain and pixel electrodes according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating the formation of a passivation layer in accordance with an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a thin film transistor substrate according to an embodiment of the invention.
Reference numerals:
10. a substrate; 20. a gate electrode; 30. a gate insulating layer; 40. a semiconductor layer; 50. a second metal layer; 51. a source electrode; 52. a drain electrode; 53. a pixel electrode; 60. a passivation layer; 70. and a through hole.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
The invention aims at the technical problem that the production cost of the thin film transistor substrate is higher due to more required manufacturing processes of the existing manufacturing method of the thin film transistor substrate, and the problem can be solved.
A method for manufacturing a thin film transistor substrate, as shown in fig. 1, includes:
s10, forming a first metal layer on the substrate;
s20, etching the first metal layer to form a grid;
s30, forming a gate insulating layer covering the gate on the substrate;
s40, forming a semiconductor layer on the gate insulating layer;
s50, forming a second metal layer on the semiconductor layer and the gate insulating layer;
s60, etching the second metal layer to form a source electrode, a drain electrode and a pixel electrode;
wherein the second metal layer is made of a transparent conductive material.
The second metal layer is formed by transparent conductive metal, so that the drain electrode can be directly extended to serve as a pixel electrode, and the source electrode, the drain electrode and the pixel electrode are formed through the same etching process, so that the manufacturing procedures are reduced, and the production cost, the manufacturing time and the complexity are reduced.
Note that the transparent conductive material is Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or Indium Tin Zinc Oxide (ITZO).
Specifically, as shown in fig. 2, a first metal layer is formed on a substrate 10, and is patterned to form a patterned gate electrode 20, and then a gate insulating layer 30 covering the gate electrode 20 is formed on the substrate 10.
In the present preferred embodiment, the first metal layer is formed on the substrate 10 by a sputtering method; it should be noted that, in practical implementation, the first metal layer may also be formed by chemical vapor deposition or other physical deposition methods.
In the process of patterning the first metal layer to form the gate electrode 20, it is preferable to perform wet etching on the first metal layer by using a mixed solution of nitric acid, phosphoric acid, and acetic acid; it is to be understood that, in an implementation, the first metal layer may be wet etched in other manners, which are not listed here.
Specifically, as shown in fig. 3, after the semiconductor layer 40 is formed on the gate insulating layer 30, the semiconductor layer 40 is subjected to patterning.
In this embodiment, the semiconductor layer 40 may be an amorphous silicon layer deposited first, and then the amorphous silicon layer is subjected to a rapid thermal annealing step to recrystallize the amorphous silicon layer into a polysilicon layer.
Specifically, as shown in fig. 4, a second metal layer 50 is formed on the semiconductor layer 40 and the gate insulating layer 30, and the second metal layer 50 is made of a transparent conductive material.
In the preferred embodiment, the second metal layer 50 is preferably deposited by sputtering, but it is understood that in the specific implementation, the second metal layer 50 can be formed in other manners according to the process conditions and the production cost.
Specifically, as shown in fig. 5, the second metal layer 50 is etched to form a source electrode 51, a drain electrode 52, and a pixel electrode 53.
Specifically, as shown in fig. 6, the method for manufacturing the thin film transistor substrate 10 further includes:
s70, forming a passivation layer 60 on the gate electrode 20 insulating layer to cover the source electrode 51 and the drain electrode 52. The passivation layer 60 provides insulation protection.
Specifically, as shown in fig. 7, the passivation layer 60 covers the pixel electrode 53, and the method for manufacturing the thin film transistor substrate 10 further includes:
s80, forming a via hole 70 on the passivation layer 60 to expose the pixel electrode 53. The direct extended drain electrode 52 serves as the pixel electrode 53, and does not interfere with the pixel display function.
Specifically, the thickness of the second metal layer 50 is greater than or equal to half of the thickness of the passivation layer 60.
It should be noted that, in practical applications, the resistance of the second metal layer 50 made of the transparent conductive material is found to be relatively large, and the thickness of the second metal layer 50 is increased, so that the impedance is reduced, and the passivation layer 60 is prevented from affecting the pixel electrode 53.
Based on the above method for manufacturing the thin film transistor substrate 10, the present invention further provides a thin film transistor substrate 10, as shown in fig. 7, the thin film transistor substrate 10 includes a substrate 10, a gate electrode 20 disposed on the substrate 10, a gate insulating layer 30 disposed on the substrate 10 and covering the gate electrode 20, a semiconductor layer 40 disposed on the gate insulating layer 30, and a second metal layer 50 disposed on the gate insulating layer 30.
The second metal layer 50 includes a source electrode 51, a drain electrode 52, and a pixel electrode 53, and the source electrode 51, the drain electrode 52, and the pixel electrode 53 are made of a transparent conductive material.
The second metal layer 50 is formed of a transparent conductive metal, so that the drain electrode 52 can be directly extended to serve as the pixel electrode 53, and the source electrode 51, the drain electrode 52 and the pixel electrode 53 are formed by the same etching process, thereby reducing the number of process steps, and reducing the production cost, the processing time and the complexity.
The transparent conductive material is indium tin oxide, indium zinc oxide, or indium tin zinc oxide.
Specifically, the thin film transistor substrate 10 further includes a passivation layer 60 disposed on the gate insulating layer 30 and covering the source electrode 51 and the drain electrode 52.
Specifically, the passivation layer 60 is provided with a through hole 70 exposing the pixel electrode 53.
Specifically, the thickness of the second metal layer 50 is greater than or equal to half of the thickness of the passivation layer 60.
The invention has the beneficial effects that: the second metal layer 50 is formed of a transparent conductive metal, so that the drain electrode 52 can be directly extended to serve as the pixel electrode 53, and the source electrode 51, the drain electrode 52 and the pixel electrode 53 are formed by the same etching process, thereby reducing the number of process steps, the production cost, the process time and the complexity.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (6)
1. A method for manufacturing a thin film transistor substrate is characterized by comprising the following steps:
s10, forming a first metal layer on the substrate;
s20, etching the first metal layer to form a grid;
s30, forming a gate insulating layer covering the gate on the substrate;
s40, forming a semiconductor layer on the gate insulating layer;
s50, forming a second metal layer on the semiconductor layer and the gate insulating layer;
s60, etching the second metal layer to form a source electrode, a drain electrode and a pixel electrode;
s70, forming a passivation layer covering the source electrode and the drain electrode on the gate insulating layer;
wherein the second metal layer is made of a transparent conductive material; the thickness of the second metal layer is greater than or equal to half of the thickness of the passivation layer.
2. The method of manufacturing a thin film transistor substrate according to claim 1, wherein the passivation layer covers the pixel electrode, the method further comprising:
and S80, forming a through hole on the passivation layer to expose the pixel electrode.
3. The method of manufacturing a thin film transistor substrate according to claim 1, wherein the transparent conductive material is indium tin oxide, indium zinc oxide, or indium tin zinc oxide.
4. A thin film transistor substrate, comprising:
a substrate;
a gate electrode disposed on the substrate;
a gate insulating layer disposed on the substrate and covering the gate electrode;
a semiconductor layer disposed on the gate insulating layer;
a second metal layer disposed on the gate insulating layer, the second metal layer including a source electrode, a drain electrode, and a pixel electrode;
the source electrode, the drain electrode and the pixel electrode are all made of transparent conductive materials; the thin film transistor substrate further includes a passivation layer disposed on the gate insulating layer and covering the source electrode and the drain electrode; the thickness of the second metal layer is greater than or equal to half of the thickness of the passivation layer.
5. The thin film transistor substrate according to claim 4, wherein a through hole exposing the pixel electrode is provided on the passivation layer.
6. The thin film transistor substrate of claim 4, wherein the transparent conductive material is indium tin oxide, indium zinc oxide, or indium tin zinc oxide.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811167707.6A CN109545750B (en) | 2018-10-08 | 2018-10-08 | Method for manufacturing thin film transistor substrate and thin film transistor substrate |
| PCT/CN2019/079097 WO2020073617A1 (en) | 2018-10-08 | 2019-03-21 | Manufacturing method for thin-film transistor substrate, and thin-film transistor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811167707.6A CN109545750B (en) | 2018-10-08 | 2018-10-08 | Method for manufacturing thin film transistor substrate and thin film transistor substrate |
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| Publication Number | Publication Date |
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| CN109545750A CN109545750A (en) | 2019-03-29 |
| CN109545750B true CN109545750B (en) | 2020-03-27 |
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| WO (1) | WO2020073617A1 (en) |
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| CN112289834A (en) * | 2020-10-22 | 2021-01-29 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
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| KR101282893B1 (en) * | 2006-06-30 | 2013-07-05 | 엘지디스플레이 주식회사 | An array substrate for LCD and method for fabricating thereof |
| JP2011253921A (en) * | 2010-06-02 | 2011-12-15 | Mitsubishi Electric Corp | Active matrix substrate and liquid crystal device |
| CN102655155B (en) * | 2012-02-27 | 2015-03-11 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method and display device thereof |
| CN102651343B (en) * | 2012-03-16 | 2014-12-24 | 京东方科技集团股份有限公司 | Manufacturing method of array substrate, array substrate and display device |
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| CN109545750A (en) | 2019-03-29 |
| WO2020073617A1 (en) | 2020-04-16 |
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