CN109545688B - 薄膜晶体管的沟道区的最终宽长比确定方法及装置 - Google Patents

薄膜晶体管的沟道区的最终宽长比确定方法及装置 Download PDF

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CN109545688B
CN109545688B CN201811385425.3A CN201811385425A CN109545688B CN 109545688 B CN109545688 B CN 109545688B CN 201811385425 A CN201811385425 A CN 201811385425A CN 109545688 B CN109545688 B CN 109545688B
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film transistor
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CN109545688A (zh
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胡迎宾
赵策
丁远奎
宋威
汪军
张扬
李伟
闫梁臣
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Hefei Xinsheng Optoelectronics Technology Co Ltd
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Abstract

本发明提供一种薄膜晶体管的沟道区的最终宽长比确定方法,所述确定方法包括:S1、设置栅极在有源层上的正投影的初始宽长比;S2、根据初始宽长比制得薄膜晶体管;S3、对根据初始宽长比制得的薄膜晶体管进行测试;S4、判断测试结果是否满足预定结果;若是,执行步骤S5,若否,执行步骤S6;S5、确定所述初始宽长比为所述薄膜晶体管的沟道区的最终宽长比;S6、改变初始宽长比的数值,并重复执行步骤S2至步骤S4。本发明还提供一种薄膜晶体管的沟道区的最终宽长比确定装置;所述确定方法用于通过多次的调节、测试获得薄膜晶体管的沟道区的最终宽长比。

Description

薄膜晶体管的沟道区的最终宽长比确定方法及装置
技术领域
本发明涉及薄膜晶体管技术领域,具体地,涉及一种薄膜晶体管的沟道区的最终宽长比确定方法、以及一种薄膜晶体管的沟道区的最终宽长比确定装置。
背景技术
薄膜晶体管是微电子设备中的重要元件,薄膜晶体管的性能对微电子设备的性能有着重要的影响。对于薄膜晶体管而言,衡量其性能的指标包括开启电流、载流子迁移率、阈值电压等,而薄膜晶体管的沟道区的宽长比对上述指标具有决定性的影响。
因此,为了获得性能良好的薄膜晶体管,在量产制造薄膜晶体管之前就应当确定薄膜晶体管的沟道区的宽长比。
目前尚无有效确定薄膜晶体管的沟道区的宽长比的方法。
发明内容
本发明的目的在于提供一种薄膜晶体管的沟道区的最终宽长比确定方法,以及一种执行所述确定方法的薄膜晶体管的沟道区的最终宽长比确定装置;所述确定方法用于通过多次的调节、测试获得薄膜晶体管的沟道区的最终宽长比。
为解决上述技术问题,作为本发明第一个方面,提供一种薄膜晶体管的沟道区的最终宽长比确定方法,其中,所述确定方法包括:
S1、设置栅极在有源层上的正投影的初始宽长比;
S2、根据初始宽长比制得薄膜晶体管;
S3、对根据初始宽长比制得的薄膜晶体管进行测试;
S4、判断测试结果是否满足预定结果;
若是,执行步骤S5,若否,执行步骤S6;
S5、确定所述初始宽长比为所述薄膜晶体管的沟道区的最终宽长比;
S6、改变初始宽长比的数值,并重复执行步骤S2至步骤S4。
优选地,步骤S2包括:
形成有源层;
形成栅极绝缘层;
形成栅极材料层;
图案化所述栅极材料层以形成栅极,所述栅极绝缘层将所述栅极与所述有源层绝缘间隔。
优选地,所述图案化所述栅极材料层以形成栅极的步骤包括:
形成光刻胶层;
利用掩膜板对所述光刻胶层进行曝光;
对曝光后的光刻胶层进行显影,以形成保护图形,所述保护图形的形状与所述栅极的形状一致;
以所述保护图形为掩膜刻蚀所述栅极材料层以形成所述栅极。
优选地,所述薄膜晶体管的源极和所述薄膜晶体管的漏极分别位于所述有源层的长度方向的两端,所述栅极在所述有源层上的正投影在所述有源层的宽度方向的尺寸小于所述有源层的宽度,在制造不同的薄膜晶体管时,利用同一个掩膜板执行所述利用掩膜板对所述光刻胶层进行曝光显影的步骤,其中,所述掩膜板的曝光区域在光刻胶层的上正投影在有源层的宽度方向上的相对位置不同于在制造前一个测试结果不满足预定结果的薄膜晶体管的栅极时,所述掩膜板的曝光区域在光刻胶层的上正投影在有源层的宽度方向上的相对位置。
优选地,步骤S2还包括在形成有源层的步骤之前进行的:
形成遮光层,所述有源层在所述遮光层上的正投影位于所述遮光层的范围内。
优选地,步骤S2还包括在形成遮光层的步骤和形成有源层的步骤之间进行的:
形成缓冲层,所述有源层形成在所述缓冲层上,所述栅极绝缘层覆盖所述缓冲层,所述栅极的一部分位于所述栅极绝缘层上,所述栅极的另一部分位于所述缓冲层上。
优选地,步骤S2还包括在图案化所述栅极材料层以形成栅极的步骤之后进行的:
形成层间绝缘层;
形成源极过孔、漏极过孔以及栅极过孔,所述源极过孔、所述漏极过孔和所述栅极过孔均贯穿所述层间绝缘层,所述栅极过孔设置在所述栅极位于所述缓冲层的部分上;
形成源漏图形层,所述源漏图形层包括源极、漏极和栅极连接件,所述源极通过所述源极过孔与所述有源层连接,所述漏极通过所述漏极过孔与所述有源层连接,所述栅极连接件通过所述栅极过孔与所述栅极连接。
优选地,有源层的材料包括IGZO、非晶ZnO、多晶ZnO、InZnO、ZnSnO中的至少一者。
优选地,所述预定结果包括开启电流满足预定电流范围、阈值电压满足预定电压范围、沟道载流子迁移率满足预定迁移率范围中的至少一者。
作为本发明第二个方面,提供一种用于薄膜晶体管的沟道区的最终宽长比确定装置,其中,所述确定装置用于执行本发明所提供的薄膜晶体管的沟道区的最终宽长比确定方法,所述最终宽长比确定装置包括:
宽长比确定单元,用于设置栅极在有源层上的正投影的初始宽长比;
测试单元,用于对根据初始宽长比制得的薄膜晶体管进行测试;
判断单元,用于判断测试结果是否满足预定结果;
所述宽长比确定单元还用于在所述测试结果满足所述预定结果时将所述初始宽长比确定为所述薄膜晶体管的沟道区的最终宽长比,以及在所述测试结果不满足所述预定结果时改变初始宽长比的数值。
附图说明
附图是用来提供对本发明的进一步理解,并且构成说明书的一部分,与下面的具体实施方式一起用于解释本发明,但并不构成对本发明的限制。在附图中:
图1为本发明所提供的薄膜晶体管的沟道区的最终宽长比确定方法的流程图;
图2为本发明所提供的薄膜晶体管的沟道区的最终宽长比确定装置的结构框图;
图3为执行图1中步骤S2制得薄膜晶体管的俯视结构示意图;
图4为图3中薄膜晶体管沿A-A线的剖面结构示意图;
图5为图3中薄膜晶体管沿B-B线的剖面结构示意图。
附图标记说明
101:基板 102:遮光层
103:缓冲层 104:有源层
104a:沟道部 104b:导体化部
105:栅极绝缘层 106:栅极
107:层间绝缘层 108:栅极连接件
109:源极 110漏极
200:确定装置 210:宽长比确定单元
220:测试单元 230:判断单元
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是,此处所描述的具体实施方式仅用于说明和解释本发明,并不用于限制本发明。
作为本发明的一个方面,提供了一种薄膜晶体管的沟道区的最终宽长比确定方法,其中,如图1所示,所述确定方法包括:
S1、设置栅极在有源层上的正投影的初始宽长比;
S2、根据初始宽长比制得薄膜晶体管;
S3、对根据初始宽长比制得的薄膜晶体管进行测试;
S4、判断测试结果是否满足预定结果;
若是,执行步骤S5,若否,执行步骤S6;
S5、确定所述初始宽长比为所述薄膜晶体管的沟道区的最终宽长比;
S6、改变初始宽长比的数值,并重复执行步骤S2至步骤S4。
首先,需要说明的是,本发明所提供的薄膜晶体管的沟道区的最终宽长比确定方法应用于薄膜晶体管的开发测试阶段,用于确定满足预定结果的薄膜晶体管的沟道区的最终宽长比,之后按照该最终宽长比进行薄膜晶体管的批量生产。
其次,如图1所示,执行上述S1至S6,通过多次的调节、测试获得薄膜晶体管的沟道区的最终宽长比,基于该最终宽长比制得的薄膜晶体管的特性满足预定结果。
本发明对制作的薄膜晶体管具体结构不做特殊限制,例如,作为一种优选地实施方式,制作的所述薄膜晶体管为如图3至图5所示的顶栅型薄膜晶体管。具体地,在步骤S2中,根据初始宽长比制得薄膜晶体管的步骤包括:
形成有源层104;
形成栅极绝缘层105;
形成栅极材料层,图案化所述栅极材料层以形成栅极106,栅极绝缘层105将栅极106与有源层104绝缘间隔。
其中,对制作有源层的材料不作限制,例如,有源层的材料可以为氧化物或者多晶硅,其中,氧化物可以包括IGZO、非晶ZnO、多晶ZnO、InZnO、ZnSnO中的至少一者。
进一步地,在本发明中,所述图案化所述栅极材料层以形成栅极的步骤包括:
形成光刻胶层;
利用掩膜板对所述光刻胶层进行曝光;
对曝光后的光刻胶层进行显影,以形成保护图形,所述保护图形的形状与所述栅极的形状一致;
以所述保护图形为掩膜刻蚀所述栅极材料层以形成所述栅极。
需要说明的是,本发明对于光刻胶的类型选择不做限制,例如,作为一种可选地实施方式,所述光刻胶可以为负性光刻胶,执行曝光、显影工艺步骤之后,对应掩膜板的曝光区的负性光刻胶形成保护图形,非曝光区的光刻胶经过显影工艺清除。
步骤S6中,改变初始宽长比的数值的步骤包括:
所述薄膜晶体管的源极109和所述薄膜晶体管的漏极110分别位于有源层104的长度方向的两端,栅极106在有源层104上的正投影在有源层104的宽度方向的尺寸小于有源层104的宽度,在制造不同的薄膜晶体管时,利用同一个掩膜板执行所述利用掩膜板对所述光刻胶层进行曝光显影的步骤,其中,所述掩膜板的曝光区域在光刻胶层的上正投影在有源层104的宽度方向上的相对位置不同于在制造前一个测试结果不满足预定结果的薄膜晶体管的栅极时,所述掩膜板的曝光区域在光刻胶层的上正投影在有源层104的宽度方向上的相对位置。
本发明对有源层的具体结构不做特殊限定,作为一种实施方式,如图5所示,有源层104包括沟道部104a和两个导体化部104b,导体化部104b设置在沟道部104a长度方向的两端,两个导体化部104b用于分别连接源源极109和漏极110,沟道部104a用于在薄膜晶体管加电后形成沟道,换言之,在沟道部104a上与栅极106的正投影对应的区域形成为所述沟道区。
由于现有技术中薄膜晶体管的栅极与有源层在正投影方向完全交叉,因此导致薄膜晶体管的沟道区的宽长比固定,若想要改变沟道区的宽长比,就需要设计或者购买新的掩膜板,从而增加了设备成本。
本发明中,设置栅极106在有源层104上的正投影在有源层104的宽度方向的尺寸小于有源层104的宽度,换言之,所述掩膜板的曝光区的正投影在有源层104的宽度方向的尺寸小于有源层104的宽度,进而,每一次改变初始宽长比的数值时,只要改变掩膜板的曝光区域在光刻胶层的上正投影与有源图层的相对位置即可实现,因此,本发明利用一套掩膜板就可以制作多种不同宽长比的薄膜晶体管,相比于现有技术每改一次需求就要重新设计或者购买新的掩膜板,降低了开发阶段的设备成本。
本发明对于调节掩膜板的位置的步骤不做特殊限制,例如,作为一种优选地实施方式,如图3至图5所示,沿Y方向调节掩膜板的位置,如图所示,Y方向实际上就是有源层104的宽度方向,调节之后沟道区的宽度d发生变化,进而改变了在步骤S1中设置的沟道区的初始宽长比。
进而,基于该最终宽长比制得的薄膜晶体管的特性满足预定结果。例如,预定结果可以是减低TFT导通时的开启电流,则可以沿Y方向移动掩膜板,使得沟道区的宽度d减小,即沟道区的宽长比减小,以实现降低TFT导通时的开启电流。
此外,掩膜板在Y方向上的位置改变,不会引入新的影响因素,从而在改变沟道区的宽长比后,调整薄膜晶体管的特性的效果单一显著,不会产生其他不良连锁反应。
在所述薄膜晶体管为如图3至图5所示的顶栅型薄膜晶体管的实施方式中,步骤S2还包括在形成有源层的步骤之前进行的:
形成遮光层102,有源层104在遮光层102上的正投影位于遮光层102的范围内。
如上所述,遮光层102用于对有源层104遮挡,防止背光或其他光线照射有源层104,对薄膜晶体管的沟道区产生不良影响。
本发明制作的所述薄膜晶体管为如图3至图5所示的顶栅型薄膜晶体管的实施方式中,步骤S2还包括在形成遮光层的步骤和形成有源层的步骤之间进行的:
形成缓冲层103,有源层104形成在缓冲层103上,栅极绝缘层105覆盖缓冲层103,栅极106的一部分位于栅极绝缘层105上,栅极106的另一部分位于缓冲层103上。
缓冲层103用于将遮光层102和有源层104绝缘间隔。
进一步地,步骤S2还包括在图案化所述栅极材料层以形成栅极的步骤之后进行的:
形成层间绝缘层107;
形成源极过孔、漏极过孔以及栅极过孔;
所述源极过孔、所述漏极过孔和所述栅极过孔均贯穿层间绝缘层107,所述栅极过孔设置在栅极106位于缓冲层103的部分上;
形成源漏图形层,所述源漏图形层包括源极109、漏极110和栅极连接件108,源极109通过所述源极过孔与有源层104连接,漏极110通过所述漏极过孔与有源层104连接,栅极连接件108通过所述栅极过孔与栅极106连接。
如上所述,所述栅极过孔设置在栅极106位于缓冲层103的部分上,可以避免当薄膜晶体管加电工作时,通过栅极连接件108的电荷对有源层104产生影响。
本发明所制作的薄膜晶体管用于显示装置,例如,OLED显示面板中,需要说明的是,如图3和图5所示,栅极连接件108与源极109、漏极110同层设置,与栅极连接件108连接的栅极驱动线(图中未示出)和与源极109连接的数据线(图中未示出)布线方向一致,不会出现交叉,从而保证薄膜晶体管正常工作。
作为另一种可选地实施方式,制作所述晶体管为底栅型薄膜晶体管,根据初始宽长比制得薄膜晶体管的步骤包括:
形成栅极;
形成栅极绝缘层;
形成有源材料层;
图案化所述有源材料层以形成有源层,所述栅极绝缘层将所述栅极与所述有源层绝缘间隔。
本发明对于形成有源层的具体工艺不做特殊限制,例如,作为一种实施方式,可以采用磁控溅射工艺形成所述有源层,具体地,所述图案化所述有源层材料层以形成有源层的步骤包括:
形成光刻胶层;
利用掩膜板对所述光刻胶层进行曝光显影,以形成保护图形,所述保护图形的形状与所述有源层的形状一致;
以所述保护图形为掩膜刻蚀所述有源材料层以形成所述有源层。
在上述制作所述晶体管为底栅型薄膜晶体管的实施方式中,执行改变初始宽长比的数值的步骤包括:
利用同一个掩膜板执行所述利用掩膜板对所述光刻胶层进行曝光显影的步骤,其中,所述掩膜板的曝光区域在光刻胶层的上正投影与栅极的相对位置不同于在制造前一个测试结果不满足预定结果的薄膜晶体管的有源层时,所述掩膜板的曝光区域在光刻胶层的上正投影与栅极的相对位置。
本发明对于所述预定结果不做特殊限制,例如,作为一种实施方式,所述预定结果包括开启电流满足预定电流范围、阈值电压满足预定电压范围、沟道载流子迁移率满足预定迁移率范围中的至少一者。
优选地,预定电流范围为20μA~100μA;预定迁移率范围为5cm2/(VS)~100cm2/(VS);预设阈值电压范围为大于0V。
作为本发明第二个方面,提供一种用于薄膜晶体管的沟道区的最终宽长比确定装置,其中,如图2所示,确定装置200用于执行本发明所提供的薄膜晶体管的沟道区的最终宽长比确定方法,确定装置200包括宽长比确定单元210、测试单元220和判断单元230。
其中,宽长比确定单元210用于设置栅极在有源层上的正投影的初始宽长比;测试单元220用于对根据初始宽长比制得的薄膜晶体管进行测试;判断单元230,用于判断测试结果是否满足预定结果。
宽长比确定单元210还用于在所述测试结果满足所述预定结果时将所述初始宽长比确定为所述薄膜晶体管的沟道区的最终宽长比,以及在所述测试结果不满足所述预定结果时改变初始宽长比的数值。
具体地,当测试结果满足预定结果时,宽长比确定单元210确定所述初始宽长比为所述薄膜晶体管的沟道区的最终宽长比;当测试结果不满足预定结果时,宽长比确定单元210改变初始宽长比的数值,测试单元210对根据改变的初始宽长比制得的薄膜晶体管进行测试。
重复上述步骤,通过多次的调节、测试获得薄膜晶体管的沟道区的最终宽长比,基于该最终宽长比制得的薄膜晶体管的特性满足预定结果。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。

Claims (10)

1.一种薄膜晶体管的沟道区的最终宽长比确定方法,其特征在于,所述确定方法包括:
S1、设置栅极在有源层上的正投影的初始宽长比;
S2、提供掩膜板,用于根据初始宽长比制得薄膜晶体管;
S3、对根据初始宽长比制得的薄膜晶体管进行测试;
S4、判断测试结果是否满足预定结果;
若是,执行步骤S5,若否,执行步骤S6;
S5、确定所述初始宽长比为所述薄膜晶体管的沟道区的最终宽长比;
S6、改变初始宽长比的数值,根据改变后的初始宽长比的数值调整所述掩膜 板的位置,并重复执行步骤S2至步骤S4;
其中,在薄膜晶体管的宽长比为第一宽长比的情况下,将掩膜板的位置调整到第一位置,在该位置处,薄膜晶体管的有源层上掩膜板的曝光区域的正交投影区域具有对应于第一宽长比的宽长比;
在薄膜晶体管的宽长比是不同于第一宽长比的第二宽长比的情况下,将掩膜板的位置调整到第二位置,在该位置处,薄膜晶体管的有源层上掩膜板的曝光区域的正交投影区域具有与第二宽长比相对应的宽长比,第二位置不同于第一位置。
2.根据权利要求1所述的最终宽长比确定方法,其特征在于,步骤S2包括:
形成有源层;
形成栅极绝缘层;
形成栅极材料层;
图案化所述栅极材料层以形成栅极,所述栅极绝缘层将所述栅极与所述有源层绝缘间隔。
3.根据权利要求2所述的最终宽长比确定方法,其特征在于,所述图案化所述栅极材料层以形成栅极的步骤包括:
形成光刻胶层;
利用掩膜板对所述光刻胶层进行曝光;
对曝光后的光刻胶层进行显影,以形成保护图形,所述保护图形的形状与所述栅极的形状一致;
以所述保护图形为掩膜刻蚀所述栅极材料层以形成所述栅极。
4.根据权利要求3所述的最终宽长比确定方法,其特征在于,所述薄膜晶体管的源极和所述薄膜晶体管的漏极分别位于所述有源层的长度方向的两端,所述栅极在所述有源层上的正投影在所述有源层的宽度方向的尺寸小于所述有源层的宽度,在制造不同的薄膜晶体管时,利用同一个掩膜板执行所述利用掩膜板对所述光刻胶层进行曝光显影的步骤,其中,所述掩膜板的曝光区域在光刻胶层的上正投影在有源层的宽度方向上的相对位置不同于在制造前一个测试结果不满足预定结果的薄膜晶体管的栅极时,所述掩膜板的曝光区域在光刻胶层的上正投影在有源层的宽度方向上的相对位置。
5.根据权利要求2所述的最终宽长比确定方法,其特征在于,步骤S2还包括在形成有源层的步骤之前进行的:
形成遮光层,所述有源层在所述遮光层上的正投影位于所述遮光层的范围内。
6.根据权利要求5所述的最终宽长比确定方法,其特征在于,步骤S2还包括在形成遮光层的步骤和形成有源层的步骤之间进行的:
形成缓冲层,所述有源层形成在所述缓冲层上,所述栅极绝缘层覆盖所述缓冲层,所述栅极的一部分位于所述栅极绝缘层上,所述栅极的另一部分位于所述缓冲层上。
7.根据权利要求6所述的最终宽长比确定方法,其特征在于,步骤S2还包括在图案化所述栅极材料层以形成栅极的步骤之后进行的:
形成层间绝缘层;
形成源极过孔、漏极过孔以及栅极过孔,所述源极过孔、所述漏极过孔和所述栅极过孔均贯穿所述层间绝缘层,所述栅极过孔设置在所述栅极位于所述缓冲层的部分上;
形成源漏图形层,所述源漏图形层包括源极、漏极和栅极连接件,所述源极通过所述源极过孔与所述有源层连接,所述漏极通过所述漏极过孔与所述有源层连接,所述栅极连接件通过所述栅极过孔与所述栅极连接。
8.根据权利要求2至7中任意一项所述的最终宽长比确定方法,其特征在于,有源层的材料包括IGZO、非晶ZnO、多晶ZnO、InZnO、ZnSnO中的至少一者。
9.根据权利要求1至7中任意一项所述的最终宽长比确定方法,其特征在于,所述预定结果包括开启电流满足预定电流范围、阈值电压满足预定电压范围、沟道载流子迁移率满足预定迁移率范围中的至少一者。
10.一种用于薄膜晶体管的沟道区的最终宽长比确定装置,其特征在于,所述确定装置用于执行权利要求1至9中任意一项所述薄膜晶体管的沟道区的最终宽长比确定方法,所述最终宽长比确定装置包括:
宽长比确定单元,用于设置栅极在有源层上的正投影的初始宽长比;
测试单元,用于对根据初始宽长比制得的薄膜晶体管进行测试;
判断单元,用于判断测试结果是否满足预定结果;
所述宽长比确定单元还用于在所述测试结果满足所述预定结果时将所述初始宽长比确定为所述薄膜晶体管的沟道区的最终宽长比,以及在所述测试结果不满足所述预定结果时改变初始宽长比的数值。
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Publication number Priority date Publication date Assignee Title
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7091077B1 (en) * 2005-06-07 2006-08-15 Xilinx, Inc. Method of directionally trimming polysilicon width
CN107068770A (zh) * 2017-05-04 2017-08-18 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示面板
CN108538860A (zh) * 2018-04-27 2018-09-14 武汉华星光电技术有限公司 顶栅型非晶硅tft基板的制作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001007290A (ja) * 1999-06-24 2001-01-12 Mitsubishi Electric Corp 半導体装置、半導体装置の製造方法、および、通信方法
JP2001318627A (ja) * 2000-02-29 2001-11-16 Semiconductor Energy Lab Co Ltd 発光装置
JP3992976B2 (ja) * 2001-12-21 2007-10-17 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2003264292A (ja) * 2002-03-11 2003-09-19 Fujitsu Display Technologies Corp シミュレーション方法
US7339187B2 (en) * 2002-05-21 2008-03-04 State Of Oregon Acting By And Through The Oregon State Board Of Higher Education On Behalf Of Oregon State University Transistor structures
KR100966420B1 (ko) * 2003-06-30 2010-06-28 엘지디스플레이 주식회사 폴리실리콘 액정표시소자 및 그 제조방법
KR100881818B1 (ko) * 2006-09-04 2009-02-03 주식회사 하이닉스반도체 반도체 소자의 형성 방법
JP5294651B2 (ja) * 2007-05-18 2013-09-18 キヤノン株式会社 インバータの作製方法及びインバータ
JP6063757B2 (ja) * 2012-02-03 2017-01-18 株式会社半導体エネルギー研究所 トランジスタ及び半導体装置
US8410816B1 (en) * 2012-02-09 2013-04-02 International Business Machines Corporation Low-swing signaling scheme for data communication
WO2015114476A1 (en) * 2014-01-28 2015-08-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9791497B2 (en) * 2014-03-27 2017-10-17 International Business Machines Corporation Method of characterizing and modeling leakage statistics and threshold voltage for ensemble devices
US9705004B2 (en) * 2014-08-01 2017-07-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN108780757B (zh) * 2016-03-22 2022-08-23 株式会社半导体能源研究所 半导体装置以及包括该半导体装置的显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7091077B1 (en) * 2005-06-07 2006-08-15 Xilinx, Inc. Method of directionally trimming polysilicon width
CN107068770A (zh) * 2017-05-04 2017-08-18 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示面板
CN108538860A (zh) * 2018-04-27 2018-09-14 武汉华星光电技术有限公司 顶栅型非晶硅tft基板的制作方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
像素设计中沟道宽和长的选择;汪海林;《应用技术》;20070531(第75期);第24-26页 *
汪海林.像素设计中沟道宽和长的选择.《应用技术》.2007,(第75期),第24-26页. *

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