CN109524410A - Three-dimensional storage - Google Patents
Three-dimensional storage Download PDFInfo
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- CN109524410A CN109524410A CN201811404852.1A CN201811404852A CN109524410A CN 109524410 A CN109524410 A CN 109524410A CN 201811404852 A CN201811404852 A CN 201811404852A CN 109524410 A CN109524410 A CN 109524410A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The present invention provides a kind of three-dimensional storages, comprising: semiconductor structure, the first storehouse of stacking of the semiconductor structure with the first substrate, on the first substrate and multiple first channel layers across first storehouse；The conductive pattern layer being bonded with first storehouse, the conductive pattern layer include multiple mutually isolated intermediate conductive parts；Cover the second storehouse of the conductive pattern layer；Across multiple second channel layers of second storehouse, every one second channel layer is electrically connected to corresponding first channel layer by intermediate conductive part；Wherein, the conductive pattern layer is formed by patterning peeling layer, and the peeling layer is formed in the surface of the second substrate, and the material of the peeling layer is monocrystalline silicon.
Description
Technical field
The invention mainly relates to field of semiconductor manufacture more particularly to a kind of three-dimensional storages.
Background technique
In order to overcome the limitation of two-dimensional storage device, industry has been researched and developed and scale of mass production has three-dimensional (3D) structure
Memory device, improve integration density by the way that memory cell is three-dimensionally disposed in substrate.
In the three-dimensional storage part of such as 3D nand flash memory, storage array may include the core with channel structure
(core) area.Channel structure is formed in the channel hole for the stack layer (stack) for extending vertically through three-dimensional storage part.Usually pass through
Single etch forms the channel hole of stack layer.But in order to improve storage density and capacity, the number of plies of three-dimensional storage
(tier) continue to increase, such as rise to 96 layers, 128 layers or more from 64 layers.Under this trend, the method for single etch
It is higher and higher in processing cost, it is more and more inefficent in processing capacity.
Some improved methods are attempted stack layer being divided into multiple storehouses (deck) being stacked with.Forming a storehouse
Afterwards, it first etches channel hole and forms channel structure, then proceed to stack storehouse.By positioned there between shared between storehouse
Conductive part connection.The material of conductive part is usually polysilicon.When the position of conductive part or bad form, it is easy to cause polycrystalline
Silicon transoid (inversion) failure, to cause that polysilicon resistance is excessively high, electron mobility is too low.This causes channel current to drop
It is low, to seriously affect the performances such as programmed written/erasing of three-dimensional storage.To solve this problem, some further to change
First etch lower channel hole after forming push-down stack into method, then the stacked on storehouse of heap and etch upper channel hole, then formed filling it is upper,
The channel structure in lower channel hole.However this mode is easily damaged the stack layer of storehouse in wet etching step.And when upper and lower
When the misregistration of channel hole, the plasma during filling channel structure can also damage the stack layer of storehouse.In addition, filling
It is also easy to lead to the blocking in hole when channel layer and dielectric layer, introduces air-gap and influence storage unit performance.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of three-dimensional storages to improve electron mobility to reduce resistance,
Promote the electric property of three-dimensional storage.
In order to solve the above technical problems, the present invention provides a kind of three-dimensional storages, comprising: semiconductor structure, described half
Conductor structure has the first substrate, the first storehouse of stacking on the first substrate and across the multiple of first storehouse
First channel layer；The conductive pattern layer being bonded with first storehouse, the conductive pattern layer include it is multiple it is mutually isolated in
Between conductive part；Cover the second storehouse of the conductive pattern layer；Across multiple second channel layers of second storehouse, every 1
Two channel layers are electrically connected to corresponding first channel layer by intermediate conductive part；Wherein, the conductive pattern layer passes through patterning
Peeling layer is formed, and the peeling layer is formed in the surface of the second substrate, and the material of the peeling layer is monocrystalline silicon.
In one embodiment of this invention, using plasma injection technology forms peeling layer on the surface of the second substrate.
In one embodiment of this invention, the plasma is hydrogen plasma.
In one embodiment of this invention, the bottom of the multiple second channel layer includes silicon epitaxy layer, the silicon epitaxy
At least part of layer is embedded in the intermediate conductive part.
In one embodiment of this invention, the bottom of first channel layer includes silicon epitaxy layer, first channel layer
Material with the silicon epitaxy layer of second channel layer bottom is silicon.
In one embodiment of this invention, the center line pair of the center line of second channel layer and first channel layer
Together.
In one embodiment of this invention, the center line and described the of second channel layer is aligned using optical alignment method
The center line of one channel layer.
In one embodiment of this invention, the multiple centre of isolation is formed between the multiple intermediate conductive part to lead
The interlayer insulating film in electric portion, the material of the interlayer insulating film are insulating materials.
In one embodiment of this invention, the conductive pattern layer and the interlayer insulating film are flat.
In one embodiment of this invention, the insulating materials is silica.
Compared with prior art, the invention has the following advantages that the present invention provides a kind of three-dimensional storage, in the first heap
The surface of stack covers peeling layer be bonded with the first storehouse, and the material of peeling layer is monocrystalline silicon, with lower capture density with
The electron mobility between storehouse can be improved in resistance, to promote the electric property of memory；In addition, conductive pattern layer is by shelling
Absciss layer patterns to be formed, and material is also monocrystalline silicon, and the silicon epitaxy layer of the second storehouse can be directly formed in conductive pattern layer,
Make storage unit that there is more convergent threshold voltage (Vt) distribution；Peeling layer is formed by the second substrate desquamation, and the second substrate can be with
It reuses, reduces Silicon Wafer process costs.
Detailed description of the invention
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates, in which:
Fig. 1 is the channel structure schematic diagram formed by several times in a kind of three-dimensional storage.
Fig. 2 is the channel structure schematic diagram that single is formed in a kind of three-dimensional storage.
Fig. 3 is the flow chart of the method for the formation three-dimensional storage of an embodiment according to the present invention.
Fig. 4 A-4E is the section of the example process of the method for the formation three-dimensional storage of an embodiment according to the present invention
Schematic diagram.
Fig. 5 is that the surface in the first storehouse of an embodiment according to the present invention covers the peeling layer being bonded with the first storehouse
Method flow chart.
Fig. 6 A-6E is that the surface in the first storehouse of an embodiment according to the present invention covers the stripping being bonded with the first storehouse
The diagrammatic cross-section of the example process of the method for absciss layer.
Fig. 7 is the diagrammatic cross-section of the three-dimensional storage of an embodiment according to the present invention.
Specific embodiment
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, therefore the present invention is by the limit of following public specific embodiment
System.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus
The step of may also including other or element.
When describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and the schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in practical system
It should include the three-dimensional space of length, width and depth in work.
For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper"
Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason
Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing
Other directions.For example, being described as be in other elements or feature " below " or " under " if overturning the device in attached drawing
Or the direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " under
Side " and " following " can include upper and lower both direction.Device may also have other directions (to be rotated by 90 ° or in its other party
To), therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer at two layers
" between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.
In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first
Be formed as the embodiment directly contacted with second feature, also may include that other feature is formed between the first and second features
Embodiment, such first and second feature may not be direct contact.
It is referred to as " on the other part " it should be appreciated that working as a component, " being connected to another component ", " is coupled in
When another component " or " contacting another component ", it can directly on another component, be connected or coupled to,
Or another component is contacted, or may exist insertion part.In contrast, when a component is referred to as " directly another
On a component ", " being directly connected in ", " being coupled directly to " or when " directly contact " another component, insertion part is not present.Together
Sample, when first component referred to as " is in electrical contact " or " being electrically coupled to " second component, in the first component and this second
There is the power path for allowing electric current flowing between part.The power path may include capacitor, the inductor of coupling and/or permission electricity
Other components of flowing, or even do not contacted directly between conductive component.
The stack layer (stack) of three-dimensional storage is stacked by multiple storehouses (deck), the channel layer between adjacent storehouse
Electrical connection.Form of the channel layer manufactured by existing method between storehouse is bad, it is easy to reduce the conduction of channel interlayer
Ability.
Fig. 1 is a kind of channel structure schematic diagram for forming (multiple etching is repeatedly filled) in three-dimensional storage by several times: DCF
(Dual Cell Formation) after the completion of the first channel hole etches and fills, is formed that is, for the channel hole of Multilayer stack
Conductive pattern between stack, then the etching and filling in the second channel hole are carried out, and so on, layer-by-layer storehouse superposition.As shown in Figure 1, three
Dimension memory 100 may include substrate 11, lower stack 12 and upper layer stacks 13 in core space.Lower stack 12 and upper layer stacks
13 stack gradually on substrate 11.Lower stack 12 has multiple the first channel hole 12a perpendicular to substrate, inside there is first
Memory layer 12b and the first channel layer 12c.Upper layer stacks 13 have multiple the second channel holes being aligned with the first channel hole 12a
13a inside has second memory layer 13b and the second channel layer 13c.Here, memory layer 12b or 13b may include barrier layer, electricity
Lotus trapping layer and tunnel layer.It is equipped with conductive part 14a in storehouse middle layer 14 between lower stack 12 and upper layer stacks 13, connects
Meet the first channel layer 12b and the second channel layer 13b.The lower stack 12 and upper layer stacks 13 of this three-dimensional storage 100 can be with
Successively production, so that the first channel hole 12a and the second channel hole 13a and its channel structure are segmented into and are formed twice.In this way, drop
The low difficulty of channel technique.But during forming upper layer stacks 13, a part the can be also formed on conductive part 14a
Two memory layer 13b cause second memory layer 13b that can have nonconducting protrusion 13d on conductive part 14a.When to grid
Apply voltage when, protrusion cause intermediate conductive part as conducting channel position can not transoid so that upper and lower first ditch
Road hole 12a and the second channel hole 13a electricity continuity failure.However, removal protrusion 13d, which exists, destroys conductive part 14a pattern
Risk, after additional complicated processing step, the pattern of the second channel hole bottom is also difficult to control, and influences Cell storage performance.
Fig. 2 is a kind of channel structure schematic diagram that (multiple etching is once filled) is once formed in three-dimensional storage: SCF
(Single Cell Formation), i.e., for the channel hole of Multilayer stack, the first channel hole is individually etched, and with interim sacrificial
Domestic animal layer filling, re-forms conductive pattern between stack, carries out the second channel hole etching, after removing sacrificial layer, the first, second channel hole is same
When fill.Refering to what is shown in Fig. 2, three-dimensional storage 200 may include substrate 21, lower stack 22 and upper layer stacks in core space
23.Lower stack 22 and upper layer stacks 23 stack gradually on substrate 21.Lower stack 22 has multiple perpendicular to substrate
First channel hole 22a, upper layer stacks 23 have multiple the second channel hole 23a being generally aligned with the first channel hole 22a.Storage
There are also memory layer 24a and channel layer 24b that the second channel hole 23a is extended through from the first channel hole 22a for device 200.Here, storage
Device layer 24a may include barrier layer, electric charge capture layer and tunnel layer.This three-dimensional storage 100 can form the first channel hole
22a and the second channel hole 23a once form channel structure.This way it is possible to avoid the problem of conductive part transoid such as Fig. 1 fails.
But during forming channel structure, the stack layer that is easily damaged at stack position A, B.And work as upper and lower channel hole
When 22a, 23a misregistration as shown in Figure 2, fill the plasma during channel structure can also damage stack position C,
The stack layer of D.In addition, being also easy to lead to the blocking in channel hole when filling channel layer 24b and dielectric layer 24c, especially in storehouse
Junction can not effectively fill so as to cause the first channel hole in lower layer including such as barrier layer, electric charge capture layer, tunnelling
Layer and dielectric layer.
The embodiment of the present invention describe it is a kind of formed three-dimensional storage method, can overcome it is above-mentioned it is existing it is multiple formation or
Primary the problem of forming Multilayer stack three-dimensional storage.Fig. 3 is that the formation three-dimensional of an embodiment according to the present invention is deposited
The flow chart of the method for reservoir.Fig. 4 A-4E is the example of the method for the formation three-dimensional storage of an embodiment according to the present invention
The diagrammatic cross-section of property process.Below with reference to the method for the formation three-dimensional storage for describing the present embodiment shown in Fig. 3-4E.
In step 302, semiconductor structure is provided.
This semiconductor structure is at least part that will be used for follow-up process to ultimately form three-dimensional storage part.Partly lead
Body structure may include array area, and array area may include core space and wordline bonding pad.In terms of vertical direction, core space can have lining
Bottom, the first storehouse of stacking on substrate and the first vertical structure across the first storehouse.First vertical structure includes
First channel layer, the first channel layer can be electrically connected to each other with other conductive parts.In the semiconductor structure exemplified by Fig. 4 A, partly lead
Body structure 400a may include substrate 401, the first storehouse 410 on substrate 401.First storehouse 410 can be first material layer
411 and the alternately stacked lamination of second material layer 412.First material layer 411 can be grid layer or dummy gate layer.First storehouse
The first vertical structure perpendicular to 401 surface of substrate, including the first channel layer 413 are equipped in 410.It is pointed out that first
Vertical structure may be virtual channel structure, and internal structure can be identical as the channel structure for core space or
Difference.
First vertical structure may additionally include between the first channel hole where the first channel layer 413 and the first vertical structure
Barrier layer, electric charge capture layer and the tunnel layer being arranged from outside to inside.These layers constitute first memory layer 414.Memory layer 414
It can not be the dielectric layer being arranged in the first channel hole, but be arranged in first material layer 411 close to the first channel hole
FGS floating gate structure in lateral trench.Some example details of first memory layer 414 are described further below.
In an embodiment of the present invention, the material of substrate 401 is, for example, silicon.First material layer 411 and second material layer 412
The e.g. combination of silicon nitride and silica.By taking the combination of silicon nitride and silica as an example, chemical vapor deposition can be used
(CVD), atomic layer deposition (ALD) or other suitable deposition methods successively replace deposited silicon nitride and oxidation on substrate 401
Silicon forms the first storehouse 410.
The bottom of first vertical structure can have silicon epitaxy layer 413a.The material of silicon epitaxy layer 413a is, for example, silicon.
Although there is described herein the exemplary composition of initial semiconductor structure, it is to be understood that, one or more features
It can be omitted, substitute or increase to from this semiconductor structure in this semiconductor structure.For example, can basis in substrate
Need to form various well regions；Filled layer 415 can be also equipped in first channel layer 413.Filled layer 415 can play the work of supporter
With.The material of filled layer 415 can be silica.Filled layer 415 can be solid, be also possible to hollow.In addition, being lifted
The material of each layer of example is only exemplary, such as substrate 401 can also be other siliceous substrates, such as SOI (insulator
Upper silicon), SiGe, Si:C etc..
In step 304, the peeling layer being bonded with the first storehouse is covered on the surface of the first storehouse.
In this step, the peeling layer of the first storehouse of covering, the peeling layer and the first heap are formed on the surface of the first storehouse
Stack bonding.Here, the material of peeling layer is monocrystalline silicon.Compared with polysilicon, monocrystalline silicon has lower capture density and resistance,
The electron mobility between storehouse can be improved, to promote the readwrite performance of memory.Peeling layer can be from other materials layer
Removing is formed, therefore is called peeling layer.It forms the first storehouse of covering and the method for being bonded peeling layer with the first storehouse can be intelligence
Energy stripping method (Smart-cut method), the detailed process of smart peeling method will be described in detail later.
In the sectional view of the semiconductor structure exemplified by Fig. 4 B, the surface of the first storehouse 410 of semiconductor structure 400b
It is formed with the peeling layer 420 of the first storehouse 410 of covering.Peeling layer 420 is bonded with the first storehouse 410.The material of peeling layer 420 is
Monocrystalline silicon has lower capture density and resistance, the electron mobility between storehouse can be improved, to promote the electricity of memory
Gas performance.
Within step 306, patterning peeling layer forms conductive pattern layer.
In this step, patterning peeling layer formed conductive pattern layer, conductive pattern layer include it is multiple it is mutually isolated in
Between conductive part.The step of patterning peeling layer forms conductive pattern layer may include: to cover etch stopper on the surface of peeling layer
Layer, there is pattern on etching barrier layer, can be transferred to the pattern on etching barrier layer by exposure, lithography and etching technique
On peeling layer, so as to form conductive pattern layer.Wherein, the peeling layer that barrier layer covers that is not etched is etched, so that first
It is exposed at the top of storehouse, the peeling layer for the barrier layer covering that is etched is not etched, forms multiple intermediate conductive parts.Pattern
Changing the step of peeling layer forms conductive pattern layer can also include: later the fill insulant between multiple intermediate conductive parts,
To form the interlayer insulating film (Inter-Layer Dielectric, ILD) that multiple intermediate conductive parts are isolated.Fill insulant
Method can be deposition of insulative material, then carry out chemical-mechanical planarization (Chemical Mechanical
Polishing, CMP).Insulating materials may, for example, be silica.
In the sectional view of the semiconductor structure exemplified by Fig. 4 C, the surface of the first storehouse 410 of semiconductor structure 400c
It is formed with conductive pattern layer 421.Conductive pattern layer 421 includes multiple mutually isolated intermediate conductive part 421a.Patterning removing
The step of 420 formation conductive pattern layer 421 of layer may include: to cover etching barrier layer on the surface of peeling layer 420, pass through exposure
Pattern on etching barrier layer can be transferred on peeling layer 420 by light, lithography and etching technique, so as to form conductive pattern
Layer 421.Wherein, the peeling layer 420 that barrier layer covers that is not etched is etched, so that the top of the first storehouse 410 is exposed
Come, the peeling layer 420 for the barrier layer covering that is etched is not etched, forms multiple intermediate conductive part 421a.Pattern peeling layer shape
At that can also include: later the fill insulant between multiple intermediate conductive part 421a the step of conductive pattern layer 421, with shape
At the interlayer insulating film 422 that multiple intermediate conductive parts are isolated.The method of fill insulant can be deposition of insulative material, then
Carry out chemical-mechanical planarization.Insulating materials may, for example, be silica.
In step 308, the second storehouse of covering conductive pattern layer is formed.
In this step, the second storehouse is formed to form stack layer (stack) with the first storehouse.It is worth noting that,
This second storehouse is not limited to layer stack, can also greater than the storehouse of one layer of other numbers, such as two layers, three layers or
More layers.
The structure of second storehouse can be similar with the structure of the first storehouse.For example, the second storehouse includes being stacked with
First material layer and second material layer.It is appreciated that the second storehouse and the first storehouse can also structure, in terms of have
Institute is different.
In the sectional view of the semiconductor structure exemplified by Fig. 4 D, formed on the first storehouse 410 of semiconductor structure 500d
Second storehouse 430.Second storehouse 430 is first material layer 431 and the alternately stacked lamination of second material layer 432.
Step 310, multiple second channel layers across the second storehouse are formed.Here, every one second channel layer is by wherein
One intermediate conductive part connects corresponding first channel layer.The step of being formed across multiple second channel layers of the second storehouse can be with
Including forming silicon epitaxy layer in the bottom of the second channel layer, at least part of silicon epitaxy layer is embedded into intermediate conductive part.?
In an optimization example of the invention, when being formed across multiple second channel layers of the second storehouse, it is aligned the center line of the second channel layer
With the center line of the first channel layer.For example, the center line and the first channel of the second channel layer can be aligned using optical alignment method
The center line of layer.
Here, multiple the second channel holes perpendicular to substrate surface, the second channel hole can first be formed in the second storehouse
Corresponding first channel hole.Second channel hole is used to accommodate the memory element being subsequently formed.
One of lithographic process can be used to form the second channel hole in the second storehouse of core space.For example, a light can be used
Mask is exposed core space, cooperates corresponding etching, forms the second channel hole.Photomask used herein can be with shape
It is identical at photomask used in the first channel hole.
In the sectional view of the semiconductor structure exemplified by Fig. 4 E, in the second channel hole 433 of semiconductor structure 400e
Form barrier layer, electric charge capture layer and the tunnel layer being arranged from outside to inside along its side wall.These layers constitute second memory layer
434.In addition, forming the second vertical channel layer 435 in second memory layer 434.Second channel layer 435 extends to the second channel
The bottom in hole 433.The bottom in the second channel hole 433 is formed with silicon epitaxy layer 436, at least part insertion of silicon epitaxy layer 436
Into intermediate conductive part 421a, to connect intermediate conductive part 421a.
Optionally, it when being formed across multiple second channel layers 433 of the second storehouse 430, is aligned in the second channel layer 433
The center line of heart line and the first channel layer 413.For example, the center line of the second channel layer 433 can be aligned using optical alignment method
With the center line of the first channel layer 413.
Optionally, filled layer 437 can be formed in the second channel layer 435.Filled layer 437 can play the role of supporter.
Filled layer 437 can be solid, be also possible to hollow.
Here, the other details of second memory layer 434, the second channel layer 435 and filled layer 437 can refer to step 402
Described in first memory layer 414, the first channel layer 415 and filled layer 416, it is not reinflated herein.
So far, the technique of the channel structure of three-dimensional storage is basically completed.After the completion of these techniques, along with routine
Three-dimensional storage can be obtained in technique.For example, when three-dimensional storage is charge trapping memory, shown in Fig. 4 E
The first storehouse 410 and the second storehouse 430 in semiconductor structure 400e are dummy grid storehouse, and first material layer 411 and 431 is puppet
Grid layer further includes then after step 408 replacing with the first material layer 411 and 431 in the first storehouse and the second storehouse
Grid layer.For another example, when three-dimensional storage is floating gate type memory, the first storehouse 410 and the second storehouse 430 are stack,
First material layer 411 and 431 in first storehouse and the second storehouse is grid layer, is not required to replace by material after step 408
The step of changing.
Flow chart has been used to be used to illustrate operation performed by method according to an embodiment of the present application herein.It should be understood that
, the operation of front not necessarily accurately carries out in sequence.On the contrary, various steps can be handled according to inverted order or simultaneously
Suddenly.Meanwhile or during other operations are added to these, or from these processes remove a certain step or number step operation.
The present invention provides a kind of method for forming three-dimensional storage, covering and the first storehouse key on the surface of the first storehouse
The peeling layer of conjunction, the material of peeling layer are monocrystalline silicon, have lower electronics capture defect state density and resistance, heap can be improved
Electron mobility between stack, to promote the electrical property of memory；In addition, conductive pattern layer is formed by removing pattern layers,
Material is also monocrystalline silicon, and the silicon epitaxy layer of the second storehouse can be directly formed in conductive pattern layer, has storage unit more
Convergent threshold voltage (Vt) distribution；Peeling layer is formed by the second substrate desquamation, and the second substrate may be reused, and reduces silicon
The process costs of wafer.
Fig. 5 is that the surface in the first storehouse of an embodiment according to the present invention covers the peeling layer being bonded with the first storehouse
Method flow chart.Fig. 6 A-6E is an embodiment according to the present invention in the covering of the surface of the first storehouse and the first storehouse
The diagrammatic cross-section of the example process of the method for the peeling layer of bonding.Below with reference to described shown in Fig. 5-6E the present embodiment
The surface of first storehouse covers the method for being bonded peeling layer with the first storehouse.
In step 502, peeling layer is formed on the surface of the second substrate.
In this step, peeling layer is formed on the surface of the second substrate.It can be with Plasma inpouring technique in the second substrate
Surface forms peeling layer.Plasma implantation process plasma can be hydrogen plasma, be also possible to the isotope of hydrogen,
Such as deuterium plasma, tritium plasma or other neither destruction silicon atom crystal structures, nor affect on memory electrical property
Plasma or other activation particle (Radical) states.By taking hydrogen plasma as an example, hydrogen plasma include hydrogen atom,
Hydrogen molecule, hydrogen ion and electrification hydrogen particle, cluster etc., whole is in plasmoid.In plasma implantation processes, pass through tune
Whole Implantation Energy can control the thickness to form peeling layer.
In the sectional view of the semiconductor structure exemplified by Fig. 6 A, plasma is injected on the surface of the second substrate 601.Deng
Gas ions can be hydrogen plasma, be also possible to the isotope of hydrogen, such as deuterium plasma, tritium plasma or other
Neither destroy silicon atom crystal structure, nor affect on memory electrical property plasma or other activation particles (Radical)
State.By taking hydrogen plasma as an example, hydrogen plasma includes hydrogen atom, hydrogen molecule, hydrogen ion and electrification hydrogen particle, cluster
Deng whole in plasmoid.In the sectional view of the semiconductor structure exemplified by Fig. 6 B, by plasma implantation process it
Afterwards, peeling layer 602 is formed on the surface of the second substrate 601.It, can be with by adjusting Implantation Energy in plasma implantation processes
Control forms the thickness of peeling layer 602.
In step 504, the second substrate and the first storehouse are bonded.
In this step, it is bonded the second substrate and the first storehouse, the second substrate has first heap of face contact of peeling layer
Stack.The method for being bonded the second substrate and the first storehouse can be the second substrate of overturning, by the second substrate and the first storehouse of overturning
Bonding, the first storehouse is located at the lower section of the second substrate at this time, is also possible to the first storehouse of overturning, by the first storehouse of overturning and the
Two substrate bondings, the first storehouse is located at the top of the second substrate at this time.
In the sectional view of the semiconductor structure exemplified by Fig. 6 C, the second substrate 601 has a face contact of peeling layer 602
First storehouse 610.Second substrate 602 is reversed, and the second substrate 602 being reversed is bonded with the first storehouse 610, the first storehouse
610 are located at the lower section of the second substrate 601.In the sectional view of the semiconductor structure exemplified by Fig. 6 C-1, the second substrate 601 has
One the first storehouse of face contact 610 of peeling layer 602.First storehouse 610 is reversed, the first storehouse 610 being reversed and the second lining
Bottom 602 is bonded, and the first storehouse 610 is located at the top of the second substrate 601.
In step 506, peeling layer is separated with the second substrate.
In this step, the peeling layer for injecting plasma has different performances from the other parts of the second substrate, utilizes
The difference of performance can separate peeling layer and the second substrate, to form the peeling layer being bonded with the first storehouse.In subsequent work
In skill, some high temperature process can make the plasma in peeling layer volatilize, and the material of peeling layer is monocrystalline silicon, do not include it is equal from
Daughter constituent.
In the sectional view of the semiconductor structure exemplified by Fig. 6 D and 6E, the peeling layer 602 and the second lining of plasma are injected
The other parts at bottom 601 have different performances, and the difference of utility can separate peeling layer 602 and the second substrate 601,
To form the peeling layer 602 being bonded with the first storehouse 610.In the subsequent process, some high temperature process can make peeling layer 602
In plasma volatilization, the material of peeling layer 602 is monocrystalline silicon, not comprising the plasma injected when forming peeling layer at
Point, so do not influence device performance.
Fig. 7 is the diagrammatic cross-section of the three-dimensional storage of an embodiment according to the present invention.The three-dimensional storage can lead to
Method as described above is crossed to be formed.Three-dimensional storage includes semiconductor structure 700.Refering to what is shown in Fig. 7, semiconductor structure 700 has
There are the first substrate 701, the first storehouse 710 of stacking on the first substrate and across multiple the first of the first storehouse 710
Channel layer 711.The conductive pattern layer 720 being bonded with the first storehouse 710, conductive pattern layer 720 include it is multiple it is mutually isolated in
Between conductive part 721.Cover the second storehouse 730 of conductive pattern layer 720.Across multiple second channel layers of the second storehouse 730
731, every one second channel layer 731 is electrically connected to corresponding first channel layer 711 by intermediate conductive part 721.Wherein, conductive pattern
Pattern layer 720 is formed by patterning peeling layer, and peeling layer is formed in the surface of the second substrate, and the material of peeling layer is monocrystalline
Silicon.
In one embodiment of this invention, using plasma injection technology forms peeling layer on the surface of the second substrate.
In one embodiment of this invention, plasma is hydrogen plasma.In one embodiment of this invention, multiple second channel layers
731 bottom includes silicon epitaxy layer 732, and at least part of silicon epitaxy layer 732 is embedded in intermediate conductive part 721.Of the invention
In one embodiment, the center line of the second channel layer 731 is aligned with the center line of the first channel layer 711.
The present invention provides a kind of three-dimensional storages, cover and the conduction of the first storehouse being bonded on the surface of the first storehouse
Pattern layer, the material of conductive pattern layer are monocrystalline silicon, have lower capture density and resistance, the electronics between storehouse can be improved
Mobility makes storage unit have more convergent threshold voltage (Vt) distribution；Furthermore, it is possible to directly be formed in conductive pattern layer
The silicon epitaxy layer of second storehouse, further improves electric conductivity.
The application has used particular words to describe embodiments herein.As " one embodiment ", " embodiment ",
And/or " some embodiments " means a certain feature relevant at least one embodiment of the application, structure or feature.Therefore, it answers
Emphasize and it is noted that " embodiment " or " one embodiment " that is referred to twice or repeatedly in this specification in different location or
" alternate embodiment " is not necessarily meant to refer to the same embodiment.In addition, certain in one or more embodiments of the application
Feature, structure or feature can carry out combination appropriate.
Although the present invention is described with reference to current specific embodiment, those of ordinary skill in the art
It should be appreciated that above embodiment is intended merely to illustrate the present invention, can also make in the case where no disengaging spirit of that invention
Various equivalent change or replacement out, therefore, as long as to the variation of above-described embodiment, change in spirit of the invention
Type will all be fallen in the range of following claims.
Claims (10)
1. a kind of three-dimensional storage, comprising:
Semiconductor structure, the semiconductor structure have the first substrate, stacking on the first substrate the first storehouse and
Across multiple first channel layers of first storehouse；
The conductive pattern layer being bonded with first storehouse, the conductive pattern layer include multiple mutually isolated intermediate conductions
Portion；
Cover the second storehouse of the conductive pattern layer；
Across multiple second channel layers of second storehouse, every one second channel layer is electrically connected to correspondence by intermediate conductive part
The first channel layer；
Wherein, the conductive pattern layer is formed by patterning peeling layer, and the peeling layer is formed in the surface of the second substrate, and
The material of the peeling layer is monocrystalline silicon.
2. three-dimensional storage according to claim 1, which is characterized in that using plasma injection technology is in the second substrate
Surface formed peeling layer.
3. three-dimensional storage according to claim 2, which is characterized in that the plasma is hydrogen plasma.
4. three-dimensional storage according to claim 1, which is characterized in that the bottom of the multiple second channel layer includes silicon
At least part of epitaxial layer, the silicon epitaxy layer is embedded in the intermediate conductive part.
5. three-dimensional storage according to claim 4, which is characterized in that the bottom of first channel layer includes silicon epitaxy
The material of the silicon epitaxy layer of layer, first channel layer and second channel layer bottom is silicon.
6. three-dimensional storage according to claim 1, which is characterized in that the center line of second channel layer and described the
The center line of one channel layer is aligned.
7. three-dimensional storage according to claim 6, which is characterized in that be aligned second channel using optical alignment method
The center line of layer and the center line of first channel layer.
8. three-dimensional storage according to claim 1, which is characterized in that be formed between the multiple intermediate conductive part
The interlayer insulating film of the multiple intermediate conductive part is isolated, the material of the interlayer insulating film is insulating materials.
9. three-dimensional storage according to claim 8, which is characterized in that the conductive pattern layer and the interlayer insulating film
It is flat.
10. three-dimensional storage according to claim 8, which is characterized in that the insulating materials is silica.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109768050A (en) * | 2018-12-18 | 2019-05-17 | 长江存储科技有限责任公司 | Three-dimensional storage and preparation method thereof |
| CN110277396A (en) * | 2019-06-26 | 2019-09-24 | 英特尔半导体(大连)有限公司 | A kind of 3D NAND storage unit mould group, memory and production method |
| CN112635479A (en) * | 2019-09-29 | 2021-04-09 | 长江存储科技有限责任公司 | Three-dimensional memory device having epitaxially grown semiconductor channel and method of forming the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120003800A1 (en) * | 2010-07-02 | 2012-01-05 | Lee Changhyun | Methods of Forming Nonvolatile Memory Devices Having Vertically Integrated Nonvolatile Memory Cell Sub-Strings Therein and Nonvolatile Memory Devices Formed Thereby |
| CN106920772A (en) * | 2017-03-08 | 2017-07-04 | 长江存储科技有限责任公司 | The forming method of three-dimensional storage and its channel pore structure |
| US20180019255A1 (en) * | 2016-07-12 | 2018-01-18 | Micron Technology, Inc. | Elevationally-Extending String Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor And Method Of Forming An Elevationally-Extending String Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor |
| CN108538848A (en) * | 2018-06-21 | 2018-09-14 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
| CN108615733A (en) * | 2018-06-21 | 2018-10-02 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
-
2018
- 2018-11-23 CN CN201811404852.1A patent/CN109524410B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120003800A1 (en) * | 2010-07-02 | 2012-01-05 | Lee Changhyun | Methods of Forming Nonvolatile Memory Devices Having Vertically Integrated Nonvolatile Memory Cell Sub-Strings Therein and Nonvolatile Memory Devices Formed Thereby |
| US20180019255A1 (en) * | 2016-07-12 | 2018-01-18 | Micron Technology, Inc. | Elevationally-Extending String Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor And Method Of Forming An Elevationally-Extending String Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor |
| CN106920772A (en) * | 2017-03-08 | 2017-07-04 | 长江存储科技有限责任公司 | The forming method of three-dimensional storage and its channel pore structure |
| CN108538848A (en) * | 2018-06-21 | 2018-09-14 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
| CN108615733A (en) * | 2018-06-21 | 2018-10-02 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109768050A (en) * | 2018-12-18 | 2019-05-17 | 长江存储科技有限责任公司 | Three-dimensional storage and preparation method thereof |
| CN109768050B (en) * | 2018-12-18 | 2020-11-17 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
| CN110277396A (en) * | 2019-06-26 | 2019-09-24 | 英特尔半导体(大连)有限公司 | A kind of 3D NAND storage unit mould group, memory and production method |
| CN110277396B (en) * | 2019-06-26 | 2020-10-27 | 英特尔半导体(大连)有限公司 | 3D NAND memory cell module, memory and manufacturing method |
| CN112635479A (en) * | 2019-09-29 | 2021-04-09 | 长江存储科技有限责任公司 | Three-dimensional memory device having epitaxially grown semiconductor channel and method of forming the same |
| CN112635479B (en) * | 2019-09-29 | 2023-09-19 | 长江存储科技有限责任公司 | Three-dimensional memory device with epitaxially grown semiconductor channel and method of forming the same |
| US11805647B2 (en) | 2019-09-29 | 2023-10-31 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device having epitaxially-grown semiconductor channel and method for forming the same |
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