CN109524355B - Structure and forming method of semiconductor device - Google Patents
Structure and forming method of semiconductor device Download PDFInfo
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- CN109524355B CN109524355B CN201811273675.8A CN201811273675A CN109524355B CN 109524355 B CN109524355 B CN 109524355B CN 201811273675 A CN201811273675 A CN 201811273675A CN 109524355 B CN109524355 B CN 109524355B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
Abstract
The invention discloses a structure of a semiconductor device, which is characterized in that a conventional semiconductor substrate is used for manufacturing the semiconductor device, and through a stacking process and a back groove process, fully-isolated NMOS and PMOS devices can be manufactured without using an SOI substrate; meanwhile, the grounding of the P well of the NMOS is realized through the processes of back N + injection and P + injection, a back contact hole and a back metal layer, and the N well of the PMOS is connected with a power supply; in addition, the back contact holes are densely distributed on the silicon substrate, so that series resistance can be reduced, and thermal conductivity can be increased, thereby avoiding the floating body effect and self-heating effect of the SOI device and preventing the performance degradation of the device. The invention also discloses a forming method of the structure of the semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor processing technologies, and more particularly, to a structure and a forming method of a semiconductor device.
Background
For half a century, the semiconductor industry has conducted reductions in transistor size, increases in transistor density, and increases in performance on a duty-by-duty basis in accordance with moore's law. However, as the dimensions of bulk silicon transistor devices in planar structures are getting closer to the physical limits, moore's law is also getting closer to its termination; therefore, new structures of semiconductor devices called "non-classical CMOS" have been proposed. These techniques include finfets, carbon nanotubes, and Silicon On Insulator (SOI), among others. The performance of the semiconductor device can be further improved by these new structures.
Among them, the SOI technology has attracted much attention due to its simple process and superior performance. SOI is a technique in which devices are fabricated on an insulating layer rather than on a conventional silicon substrate, thereby achieving all-dielectric isolation of individual transistors. Compared with the traditional planar bulk silicon process, the SOI technology has the advantages of high speed, low power consumption and high integration level. But also causes the deterioration of the parameter performance of part of devices due to the fully isolated device structure.
As shown in fig. 1, which is a cross-sectional view of a conventional non-fully depleted silicon-on-insulator device. Generally, an SOI silicon wafer is processed by SIMOX or SMART CUT technology to finally form a three-layer structure of a substrate silicon wafer 10, a silicon dioxide insulating medium 11 and a device silicon layer 12; then, the fabrication of CMOS (i.e., NMOS and PMOS) devices is performed in the device silicon layer 12, and finally, the contact holes 13 and the subsequent metal interconnections 15 are formed to form a circuit structure. Full device-to-device isolation is achieved because the NMOS and PMOS transistors are surrounded by the trench isolation 16 and the carbon dioxide dielectric layer 12. However, since the devices are fully isolated, the NMOS and PMOS body regions 14 of fig. 1 cannot be effectively connected to a power supply or ground, creating the so-called floating body effect. Although the floating body effect can be improved by the device layout, the floating body effect still appears when the body contact region is far away from the channel region due to the large resistance of the body region 14, thereby causing an abnormality of the output curve of the MOS transistor. Meanwhile, the silicon dioxide 12 below the body region 14 has poor thermal conductivity, which causes a self-heating effect of the device, so that the carrier mobility of the device is reduced, and the performance of the device is degraded. In addition, the preparation process of the SOI silicon wafer is complex and the manufacturing cost is high.
Therefore, there is a need for a new type of semiconductor device that can be manufactured using a lower cost semiconductor substrate without using an SOI silicon wafer, while avoiding the floating body effect and self-heating effect of the SOI device.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned deficiencies of the prior art and to providing a structure and method for forming a semiconductor device.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a structure of a semiconductor device, comprising: a plurality of structures disposed on the front and back sides of the semiconductor substrate; wherein the content of the first and second substances,
the structure arranged on the front surface of the semiconductor substrate comprises:
shallow trench isolation, a well region, a source drain and a gate on the front side of the semiconductor substrate;
a back dielectric layer on the front surface of the semiconductor substrate, and a back metal interconnection layer in the back dielectric layer;
the structure arranged on the back surface of the semiconductor substrate comprises:
a back side trench isolation and heavily doped implant region on the back side of the semiconductor substrate; the back surface groove isolation is connected and positioned above the shallow groove isolation, and the heavy doping injection region is connected and positioned above the well region;
the semiconductor substrate comprises a back dielectric layer positioned on the back surface of the semiconductor substrate, a plurality of back contact holes positioned in the back dielectric layer and connected with the heavily doped injection layer at the lower ends, and a back metal layer connected with the back contact holes and positioned on the upper ends of the back contact holes.
Further, a back contact array is formed by the plurality of back contact holes.
Further, the back trench isolation is filled with a dielectric material.
Further, the structure of the semiconductor device is an NMOS or PMOS structure.
Furthermore, the structure of the semiconductor device is an NMOS and PMOS alternately arranged structure, and the NMOS and the PMOS are isolated by a full isolation structure formed by vertically aligned shallow trench isolation and back trench isolation.
Further, when the structure of the semiconductor device is an NMOS structure, the well region is a P well, and the heavily doped injection region is a P + injection region; when the structure of the semiconductor device is a PMOS structure, the well region is an N well, and the heavily doped injection region is an N + injection region.
A method for forming a structure of a semiconductor device, comprising:
providing a semiconductor substrate, and forming shallow trench isolation, a P well, an N + source drain and a grid of an NMOS, and an N well, a P + source drain and a grid of a PMOS on the front surface of the semiconductor substrate;
depositing a back-end dielectric layer on the surface of the front side of the semiconductor substrate, and forming a contact hole and a back-end metal interconnection layer in the back-end dielectric layer;
inverting the semiconductor substrate to bond the surface of the subsequent dielectric layer with a slide glass; then carrying out first annealing;
thinning the back of the semiconductor substrate to enable the thickness of the thinned semiconductor substrate to be smaller than the injection depth of the N well and the P well;
forming a back groove on the back of the semiconductor substrate, filling a medium in the back groove, and forming a back groove isolation which is vertically connected with and aligned with the shallow groove isolation so as to form a full isolation structure between the NMOS and the PMOS;
p + injection is carried out in a P well of the NMOS, and N + injection is carried out in an N well of the PMOS; then carrying out second annealing, and carrying out activation of N + injection and P + injection;
depositing a back dielectric layer on the back surface of the semiconductor substrate, and defining and filling back contact holes in the back dielectric layer to densely arrange the back contact holes in the back dielectric layer to form a back contact hole array so as to form ohmic contact between the back contact holes and N + injection and P + injection;
and forming a back metal layer on the back contact hole, and realizing the power supply connection and the ground connection of the N well and the P well through the connection of the back metal layer, the power supply and the ground.
Further, the semiconductor substrate is a silicon, germanium, silicon carbide or gallium nitride substrate, or an elemental substrate of indium phosphide, or a compound substrate of indium phosphide.
Further, the filling medium in the back side trench isolation is one or more of silicon dioxide, silicon nitride and silicon oxynitride.
Further, the second annealing is laser annealing or low-temperature annealing.
According to the technical scheme, the conventional semiconductor substrate is used for manufacturing the semiconductor device, and the fully-isolated NMOS and PMOS devices can be manufactured without using an SOI substrate through a stacking process and a back groove process; meanwhile, the grounding of the P well of the NMOS is realized through the processes of back N + injection and P + injection, a back contact hole and a back metal layer, and the N well of the PMOS is connected with a power supply; in addition, the back contact holes are densely distributed on the silicon substrate, so that series resistance can be reduced, and thermal conductivity can be increased, thereby avoiding the floating body effect and self-heating effect of the SOI device and preventing the performance degradation of the device.
Drawings
Fig. 1 is a schematic diagram of a conventional non-fully depleted silicon-on-insulator device.
Fig. 2 is a schematic diagram of a structure of a semiconductor device according to a preferred embodiment of the invention.
Fig. 3-10 are process steps illustrating a method of forming a structure of a semiconductor device according to a preferred embodiment of the invention.
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following detailed description of the present invention, please refer to fig. 2, wherein fig. 2 is a schematic diagram illustrating a structure of a semiconductor device according to a preferred embodiment of the present invention. As shown in fig. 2, a structure of a semiconductor device of the present invention includes a plurality of structures provided on the front and back surfaces of a semiconductor substrate 22. The semiconductor substrate 22 may be a silicon, germanium, silicon carbide, or gallium nitride substrate, or an elemental substrate of indium phosphide, or a compound substrate of indium phosphide. The following description will be given taking a silicon substrate as an example. The structure of the semiconductor device of the invention can be an NMOS or PMOS structure; alternatively, the structure of the semiconductor device of the present invention may be a structure in which NMOS and PMOS are alternately arranged. The present invention will be described in detail below with a structure in which NMOS and PMOS are alternately arranged.
Please refer to fig. 2. In the structure of a semiconductor device of the present invention, the structure provided on the front surface of the silicon substrate 22 may include:
and the shallow trench isolation 21, the P well 25, the N + source drain 23 and the grid 20 of the NMOS, and the N well 25 ', the P + source drain 23 ' and the grid 20 ' of the PMOS are arranged on the front surface of the silicon substrate 22.
A back dielectric layer 32 provided on the front surface of the silicon substrate 22, and a back metal interconnection layer 31 provided in the back dielectric layer 32. The subsequent metal interconnection layer 31 is connected to the silicon substrate 22 through the contact hole 30.
Please refer to fig. 2. Meanwhile, in the structure of a semiconductor device of the present invention, the structure provided on the back surface of the silicon substrate 22 includes:
A backside dielectric layer 29 disposed on the backside surface of the silicon substrate 22, a plurality of backside contact holes 28 and 28 'disposed in the backside dielectric layer 29, and a backside metal layer 27 disposed on the backside contact holes 28 and 28'.
Backside contact holes 28, 28' are located in the NMOS and PMOS regions, respectively. Wherein, the lower end of the back contact hole 28 in the NMOS region is connected to the P + implantation region 26, and the upper end is connected to the back metal layer 27; the lower end of the back contact hole 28 'in the PMOS region is connected to the N + implant region 26', while the upper end is connected to the back metal layer 27.
Please refer to fig. 2. The lower end of the back trench isolation 24 is connected to and located above the shallow trench isolation 21, the P + injection region 26 is connected to and located above the P well 25, and the N + injection region 26 'is connected to and located above the N well 25'.
The upper end of the backside trench isolation 24 and the P + implant region 26, N + implant region 26' may be exposed at the backside surface of the silicon substrate 22.
The backside trench isolation 24 is filled with a dielectric material. The NMOS and the PMOS are isolated by a full isolation structure formed by the vertically aligned shallow trench isolation 21 and the back trench isolation 24. The back side trench isolation 24 and the shallow trench isolation 21 are connected together, so that complete electrical isolation is realized between the NMOS and the PMOS devices, and the full isolation effect similar to that of a silicon-on-insulator device is achieved.
The plurality of backside contact holes 28, 28 'may be configured as a densely packed array of backside contact holes for NMOS and PMOS, respectively, above the P + implant region 26 and the N + implant region 26'.
The N + injection region 26 'and the P + injection region 26 are led out from the back of the silicon substrate 22 through the back contact holes 28 and 28' and the back metal layer 27 which are densely distributed; subsequently, the bias voltage of the circuit is applied, namely, the power supply voltage is applied to the back metal layer 27 of the PMOS, and the ground level is applied to the back metal layer 27 of the NMOS, so that the N well 25' and the P well 25 realize reverse bias, and the floating body effect is avoided. Meanwhile, the back contact holes 28 and 28 'are densely arranged on the silicon substrate 22, and metal materials such as tungsten, aluminum or copper are filled in the contact holes, so that the back contact holes are good thermal conductors, and heat generated in the semiconductor silicon substrate 22 can be quickly led out through the densely arranged back contact holes 28 and 28' and the back metal layer 27, so that the self-heating effect of the device is effectively avoided.
A method for forming a structure of a semiconductor device according to the present invention will be described in detail below with reference to the following detailed description and the accompanying drawings.
Referring to fig. 3-10, fig. 3-10 are process steps of a method for forming a structure of a semiconductor device according to a preferred embodiment of the invention. As shown in fig. 3 to fig. 10, a method for forming a structure of a semiconductor device according to the present invention can be used to form the structure of the semiconductor device. Taking the silicon substrate 22 as an example, the method for forming the structure of the semiconductor device of the present invention may include the following steps:
first, as shown in fig. 3, a conventional CMOS fabrication process may be used to form shallow trench isolations 21, P-wells 25, N + source drains 23 and gates 20 for NMOS, and N-wells 25 ', P + source drains 23 ' and gates 20 ' for PMOS on the front side of a silicon substrate 22. The gate 20 of the NMOS and the gate 20' of the PMOS can be made of polysilicon material.
Next, a subsequent dielectric layer material is deposited on the front surface of the silicon substrate 22 to form a subsequent dielectric layer 32, and a contact hole 30 and a subsequent metal interconnection layer 31 are formed in the subsequent dielectric layer 32.
Then, as shown in fig. 4, the silicon substrate 22 completed with the conventional CMOS process is inverted, and the surface of the subsequent dielectric layer 32 is stacked and bonded to a carrier sheet 33. And then a conventional annealing (first annealing) is performed.
Next, as shown in fig. 5, the back surface of the silicon substrate 22 may be thinned by grinding, wet etching, chemical mechanical polishing, and other processes, so that the thickness of the thinned silicon substrate 22 is smaller than the implantation depth of the N-well 25' and the P-well 25.
Again, as shown in fig. 6, back trenches corresponding in number and position to the shallow trench isolations 21 may be formed on the back surface of the silicon substrate 22 by photolithography, dry etching or wet etching, and dielectric filling may be performed in the back trenches, where the dielectric may be one or more of silicon dioxide, silicon nitride and silicon oxynitride, to form the back trench isolations 24. Wherein the backside trench isolation 24 is aligned and connected to the shallow trench isolation 21 formed in a conventional CMOS process, thereby forming a full isolation structure between NMOS and PMOS.
Next, as shown in fig. 7, P + implantation may be performed in the P-well 25 of the NMOS and N + implantation may be performed in the N-well 25' of the PMOS through an ion implantation process; then, annealing (second annealing) is performed to perform activation of the N + implantation and the P + implantation, thereby forming N + implantation regions 26', P + implantation regions 26. The second annealing can adopt laser annealing or low-temperature annealing to activate the N + implantation and the P + implantation on the premise of not influencing the performance of the device in the conventional CMOS process.
Again, as shown in fig. 8, a backside dielectric layer 29 may be formed by depositing a conventional dielectric layer material on the backside surface of the silicon substrate 22 by chemical vapor deposition or the like.
Subsequently, as shown in fig. 9, the backside contact holes may be defined in the backside dielectric layer 29 by photolithography and etching, and the backside contact holes may be densely arranged on the silicon substrate 22 to reduce the series resistance and increase the thermal conductivity. The backside contact holes 28, 28' are then filled to form backside contact holes, and the filling metal may be a CMOS compatible metal material such as tungsten, aluminum, or copper. The filled back contact holes 28, 28 ' constitute an array of back contact holes, thereby forming ohmic contacts between the back contact holes 28, 28 ' and the N + implant regions 26 ', P + implant regions 26.
Finally, as shown in fig. 10, a back metal layer 27 is formed on the back contact holes 28, 28'. The power and ground connections for the N-well 25' and P-well 25 are made through the connection of the back metal layer 27 to power and ground.
In summary, the invention can manufacture fully isolated NMOS and PMOS devices without using an SOI substrate through a stacking process and a back trench process; meanwhile, the grounding of the P well of the NMOS is realized through the processes of back N + injection and P + injection, a back contact hole and a back metal layer, and the N well of the PMOS is connected with a power supply; in addition, the back contact holes are densely distributed on the silicon substrate, so that series resistance can be reduced, and thermal conductivity can be increased, thereby avoiding the floating body effect and self-heating effect of the SOI device and preventing the performance degradation of the device. The present invention uses conventional silicon substrates for semiconductor device fabrication and is therefore compatible with conventional semiconductor processing.
The above description is only a preferred embodiment of the present invention, and the embodiments are not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the present invention.
Claims (10)
1. A structure of a semiconductor device, comprising: a plurality of structures disposed on the front and back sides of the semiconductor substrate; wherein the content of the first and second substances,
the structure arranged on the front surface of the semiconductor substrate comprises:
shallow trench isolation, a well region, a source drain and a grid electrode are positioned on the front surface of the semiconductor substrate;
a back dielectric layer on the front surface of the semiconductor substrate, and a back metal interconnection layer in the back dielectric layer;
the structure arranged on the back surface of the semiconductor substrate comprises:
a back side trench isolation and heavily doped implant region on the back side of the semiconductor substrate; the back surface groove isolation is connected and positioned above the shallow groove isolation, and the heavy doping injection region is connected and positioned above the well region;
the semiconductor substrate comprises a back dielectric layer positioned on the back surface of the semiconductor substrate, a plurality of back contact holes positioned in the back dielectric layer and connected with the heavily doped injection region at the lower ends, and a back metal layer connected with the back contact holes and positioned on the upper ends of the back contact holes.
2. The structure of the semiconductor device according to claim 1, wherein a back contact array is constituted by the plurality of back contact holes.
3. The structure of the semiconductor device according to claim 1, wherein the backside trench isolation is filled with a dielectric material.
4. The structure of the semiconductor device according to claim 1, wherein the structure of the semiconductor device is an NMOS or PMOS structure.
5. The structure of the semiconductor device as claimed in claim 1, wherein the structure of the semiconductor device is a structure in which NMOS and PMOS are alternately arranged, and the NMOS and PMOS are isolated by a full isolation structure formed by vertically aligned shallow trench isolation and backside trench isolation.
6. The structure of the semiconductor device according to claim 4 or 5, wherein when the structure of the semiconductor device is an NMOS structure, the well region is a P well, and the heavily doped injection region is a P + injection region; when the structure of the semiconductor device is a PMOS structure, the well region is an N well, and the heavily doped injection region is an N + injection region.
7. A method for forming a structure of a semiconductor device, comprising:
providing a semiconductor substrate, and forming shallow trench isolation, a P well, an N + source drain and a grid of an NMOS, and an N well, a P + source drain and a grid of a PMOS on the front surface of the semiconductor substrate;
depositing a back-end dielectric layer on the surface of the front side of the semiconductor substrate, and forming a contact hole and a back-end metal interconnection layer in the back-end dielectric layer;
inverting the semiconductor substrate to bond the surface of the subsequent dielectric layer with a slide glass; then carrying out first annealing;
thinning the back of the semiconductor substrate to enable the thickness of the thinned semiconductor substrate to be smaller than the injection depth of the N well and the P well;
forming a back groove on the back of the semiconductor substrate, filling a medium in the back groove, and forming a back groove isolation which is vertically connected with and aligned with the shallow groove isolation so as to form a full isolation structure between the NMOS and the PMOS;
p + injection is carried out in a P well of the NMOS, and N + injection is carried out in an N well of the PMOS; then carrying out second annealing, and carrying out activation of N + injection and P + injection;
depositing a back dielectric layer on the back surface of the semiconductor substrate, and defining and filling back contact holes in the back dielectric layer to densely arrange the back contact holes in the back dielectric layer to form a back contact hole array so as to form ohmic contact between the back contact holes and N + injection and P + injection;
and forming a back metal layer on the back contact hole, and realizing the power supply connection and the ground connection of the N well and the P well through the connection of the back metal layer, the power supply and the ground.
8. The method according to claim 7, wherein the semiconductor substrate is a silicon, germanium, silicon carbide, or gallium nitride substrate, or an indium phosphide compound substrate.
9. The method as claimed in claim 7, wherein the filling medium in the backside trench isolation is one or more of silicon dioxide, silicon nitride and silicon oxynitride.
10. The method according to claim 7, wherein the second annealing is low-temperature annealing.
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| KR100281109B1 (en) * | 1997-12-15 | 2001-03-02 | 김영환 | Silicon on insulator device and method for fabricating the same |
| CN105336779A (en) * | 2014-08-05 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | LDMOS (lateral double-diffused MOSFET) device and formation method therefor |
| US9812580B1 (en) * | 2016-09-06 | 2017-11-07 | Qualcomm Incorporated | Deep trench active device with backside body contact |
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| KR100281109B1 (en) * | 1997-12-15 | 2001-03-02 | 김영환 | Silicon on insulator device and method for fabricating the same |
| CN105336779A (en) * | 2014-08-05 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | LDMOS (lateral double-diffused MOSFET) device and formation method therefor |
| US9812580B1 (en) * | 2016-09-06 | 2017-11-07 | Qualcomm Incorporated | Deep trench active device with backside body contact |
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