CN109524355A - A kind of structure and forming method of semiconductor devices - Google Patents
A kind of structure and forming method of semiconductor devices Download PDFInfo
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- CN109524355A CN109524355A CN201811273675.8A CN201811273675A CN109524355A CN 109524355 A CN109524355 A CN 109524355A CN 201811273675 A CN201811273675 A CN 201811273675A CN 109524355 A CN109524355 A CN 109524355A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
Abstract
The invention discloses a kind of structures of semiconductor devices, and the manufacture of semiconductor devices is carried out using conventional semiconductor substrate, by stacking technique and backside trench technique, so that without using SOI substrate, so that it may produce the NMOS being isolated entirely and PMOS device；Meanwhile by back side N+ injection and P+ injection, rear-face contact hole and back metal layer process, the p-well ground connection of NMOS is realized, the N trap of PMOS connects power supply；Also, rear-face contact hole carry out on a silicon substrate it is densely arranged, can reduce series resistance and increase thermal conductivity, so as to avoid the floater effect and self-heating effect of SOI device, it is therefore prevented that the deterioration of device performance.The invention also discloses a kind of forming methods of the structure of semiconductor devices.
Description
Technical field
The present invention relates to semiconductor processing technology fields, more particularly, to the structure and formation of a kind of semiconductor devices
Method.
Background technique
Since half a century, semiconductor industry carries out always the contracting of transistor size with following the prescribed order according to Moore's Law
The promotion of small, transistor density raising and performance.However, the body silicon transistor device size with planar structure increasingly connects
Nearly physics limit, Moore's Law also become closer to the termination in it；Therefore, some semiconductors for being referred to as " non-classical CMOS "
Device new construction is suggested.These technologies include FinFET, carbon nanotube and silicon-on-insulator (silicon on
Insulator, SOI) etc..The performance of semiconductor devices can further be promoted by these new constructions.
Wherein, SOI technology is attracted wide attention due to its simple process and superior performance.SOI is a kind of by device system
Make on the insulating layer rather than in traditional silicon substrate, to realize the technology of the Fully dielectric isolation of single transistor.Compared to traditional
Plane bulk silicon technological, SOI technology have high speed, low-power consumption and the high advantage of integrated level.But due to the device architecture that it is isolated entirely,
Also the deterioration of part of devices performance parameters is caused simultaneously.
As shown in Figure 1, its sectional view for the non-fully depleted SOI device of tradition.Usual soi wafer passes through SIMOX
Or SMART CUT technology is processed, and the three of silicon substrate 10, silicon dioxide insulator medium 11 and device silicon layer 12 are ultimately formed
Layer structure；Then the manufacture for carrying out CMOS (i.e. NMOS and PMOS) device in device silicon layer 12 again, finally carries out contact hole 13
With 15 production of rear road metal interconnection, circuit structure is formed.Since NMOS and PMOS tube are by trench isolations 16 and CO 2 medium
Layer 12 surrounds, it is achieved that the full isolation between device and device.But since device is isolated entirely, the NMOS in Fig. 1 and
The body area 14 of PMOS just can not form effective connection with power supply or ground, form so-called floater effect.Although device can be passed through
Domain improves floater effect, but since 14 resistance of body area is larger, and when body contact zone leaves channel region farther out, floating body is imitated
It should or can show, to cause the exception of metal-oxide-semiconductor curve of output.Meanwhile the silica 12 of 14 lower section of body area is thermally conductive
Property is poor, causes the self-heating effect of device, so that the carrier mobility of device declines, device performance degradation.In addition,
The preparation process of soi wafer is complicated, and manufacturing cost is higher.
Therefore, it is necessary to a kind of semiconductor devices, and the semiconductor substrate that lower cost can be used is manufactured, and nothing
Soi wafer need to be used, while can be to avoid the floater effect and self-heating effect of SOI device.
Summary of the invention
It is an object of the invention to overcome drawbacks described above of the existing technology, provide a kind of semiconductor devices structure and
Forming method.
To achieve the above object, technical scheme is as follows:
A kind of structure of semiconductor devices, comprising: set on multiple structures of semiconductor substrate front and back；Wherein,
Include: set on the positive structure of the semiconductor substrate
Shallow trench isolation on the front of the semiconductor substrate, well region, source and drain and grid；
Rear track media layer in the front face surface of the semiconductor substrate, and in the rear track media layer
Road metal interconnecting layer afterwards；
Structure set on the semiconductor substrate back side includes:
Backside trench isolation and heavily-doped implant area on the back side of the semiconductor substrate；The backside trench every
From being connected positioned at the top of the shallow trench isolation, the heavily-doped implant area is connected positioned at the top of the well region；
Back side dielectric layer on the backside surface of the semiconductor substrate, be located at the back side dielectric layer in and lower end
Connect multiple rear-face contact holes of the heavily-doped implant layer, and the back-side gold being connected on the upper end of the rear-face contact hole
Belong to layer.
Further, rear-face contact hole array is constituted by the multiple rear-face contact hole.
Further, dielectric material is filled in the backside trench isolation.
Further, the structure of the semiconductor devices is NMOS or PMOS structure.
Further, the structure of the semiconductor devices be the alternately arranged structure of NMOS and PMOS, the NMOS and
Full isolation structure is formed by by shallow trench isolation and the backside trench isolation being aligned up and down between PMOS to be isolated.
Further, when the structure of the semiconductor devices is NMOS structure, the well region is p-well, the heavy doping
Injection region is the injection region P+；When the structure of the semiconductor devices is PMOS structure, the well region is N trap, the heavy doping
Injection region is the injection region N+.
A kind of forming method of the structure of semiconductor devices, comprising:
Semi-conductive substrate is provided, forms shallow trench isolation, the p-well of NMOS, N+ on the front of the semiconductor substrate
Source and drain and grid, N trap, P+ source and drain and the grid of PMOS；
Track media layer after deposit is formed in the front face surface of the semiconductor substrate, and formed and connect in rear track media layer
Contact hole and rear road metal interconnecting layer；
The semiconductor substrate is inverted, bonds the surface of the rear track media layer with a slide glass；Then
Carry out the first annealing；
The semiconductor substrate is carried out back thinning, the semiconductive substrate thickness after being thinned is made to be less than N trap and p-well
Injection depth；
Form backside trench on the back side of the semiconductor substrate, media filler overleaf carried out in groove, formed with
The backside trench isolation that shallow trench isolation is connected up and down and is aligned, to form the full isolation structure between NMOS and PMOS；
P+ injection is carried out in the p-well of NMOS, and N+ injection is carried out in the N trap of PMOS；Then the second annealing is carried out, is carried out
The activation of N+ injection and P+ injection；
Deposit forms back side dielectric layer on the backside surface of the semiconductor substrate, and is overleaf carried on the back in dielectric layer
The definition and filling in face contact hole carry out rear-face contact hole overleaf in dielectric layer densely arranged, constitute rear-face contact hole battle array
Column, to form the Ohmic contact between rear-face contact hole and N+ injection, P+ injection；
Metal layer on back overleaf is formed on contact hole, passes through the connection of metal layer on back and power supply, ground, Lai Shixian N trap
It is connected with the power supply of p-well and ground connects.
Further, the semiconductor substrate is the simple substance substrate of silicon, germanium, silicon carbide or gallium nitride substrate or indium phosphide,
Or the compound substrate of indium phosphide.
Further, the filled media in the backside trench isolation is in silica, silicon nitride and silicon oxynitride
It is one or more of.
Further, described second laser annealing or low-temperature annealing are annealed into.
It can be seen from the above technical proposal that the present invention carries out the manufacture of semiconductor devices using conventional semiconductor substrate,
By stacking technique and backside trench technique, so that without using SOI substrate, so that it may produce NMOS the and PMOS device being isolated entirely
Part；Meanwhile it being connect by back side N+ injection and P+ injection, rear-face contact hole and back metal layer process, the p-well for realizing NMOS
The N trap on ground, PMOS connects power supply；Also, rear-face contact hole carries out densely arranged on a silicon substrate, can reduce series resistance and increasing
Add thermal conductivity, so as to avoid the floater effect and self-heating effect of SOI device, it is therefore prevented that the deterioration of device performance.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of traditional non-fully depleted SOI device.
Fig. 2 is a kind of schematic diagram of the structure of semiconductor devices of a preferred embodiment of the present invention.
Fig. 3-Figure 10 is a kind of technique step of the forming method of the structure of semiconductor devices of a preferred embodiment of the present invention
Rapid schematic diagram.
Specific embodiment
With reference to the accompanying drawing, specific embodiments of the present invention will be described in further detail.
It should be noted that in following specific embodiments, when describing embodiments of the invention in detail, in order to clear
Ground indicates structure of the invention in order to illustrate, spy does not draw to the structure in attached drawing according to general proportion, and has carried out part
Amplification, deformation and simplified processing, therefore, should be avoided in this, as limitation of the invention to understand.
In specific embodiment of the invention below, referring to FIG. 2, Fig. 2 is one kind of a preferred embodiment of the present invention
The schematic diagram of the structure of semiconductor devices.As shown in Fig. 2, a kind of structure of semiconductor devices of the invention, including be set to and partly lead
Multiple structures of 22 front and back of body substrate.Silicon, germanium, silicon carbide or gallium nitride substrate or phosphorus can be used in semiconductor substrate 22
Change the simple substance substrate of indium or the compound substrate of indium phosphide.It will be illustrated by taking silicon substrate as an example below.Wherein, of the invention
The structure of semiconductor devices can be NMOS or PMOS structure；Alternatively, the structure of semiconductor devices of the invention is also possible to
The alternately arranged structure of NMOS and PMOS.Below with the alternately arranged structure of NMOS and PMOS come to the present invention be situated between in detail
It continues.
Please refer to Fig. 2.In a kind of structure of semiconductor devices of the invention, it can be wrapped set on the positive structure of silicon substrate 22
It includes:
Shallow trench isolation 21 on the front of silicon substrate 22, p-well 25, N+ source and drain 23 and the grid 20, PMOS of NMOS
N trap 25 ', P+ source and drain 23 ' and grid 20 '.
Rear track media layer 32 in the front face surface of silicon substrate 22, and it is located at rear 32 road Zhong Hou of track media layer gold
Belong to interconnection layer 31.Road metal interconnecting layer 31, which passes through, afterwards realizes connection between contact hole 30 and silicon substrate 22.
Please refer to Fig. 2.Meanwhile the structure in a kind of structure of semiconductor devices of the invention, set on 22 back side of silicon substrate
Include:
The injection region P+ 26 of 24 and NMOS and the N+ injection of PMOS is isolated in backside trench on the back side of silicon substrate 22
Area 26 '.
Back side dielectric layer 29 on the backside surface of silicon substrate 22, multiple back sides in back side dielectric layer 29 connect
Contact hole 28 and 28 ', and the metal layer on back 27 being located on rear-face contact hole 28 and 28 '.
Rear-face contact hole 28,28 ' is located at NMOS area and the area PMOS.Wherein, positioned at the rear-face contact hole 28 of NMOS area
Lower end connect the injection region P+ 26, while upper end is connected with metal layer on back 27；Under the rear-face contact hole 28 ' in the area PMOS
The end connection injection region N+ 26 ', while upper end is connected with metal layer on back 27.
Please refer to Fig. 2.The lower end of backside trench isolation 24 is connected positioned at the top of shallow trench isolation 21,26 phase of the injection region P+
Vicinal is connected in the top of p-well 25, the injection region N+ 26 ' positioned at the top of N trap 25 '.
The upper end and the injection region P+ 26, the injection region N+ 26 ' of backside trench isolation 24 can be exposed to the back side of silicon substrate 22
Surface.
Dielectric material is filled in backside trench isolation 24.Shallow trench isolation between NMOS and PMOS by being aligned up and down
21 and backside trench isolation 24 be formed by full isolation structure and be isolated.Backside trench isolation 24 and shallow trench isolation 21 are connected to
Together, so that realizing complete electric isolation between NMOS and PMOS device, reach the full isolation of similar SOI device
Effect.
Above-mentioned multiple rear-face contact holes 28,28 ' can respectively constitute on the injection region P+ 26, the injection region N+ 26 ' and adhere to separately
The densely arranged rear-face contact hole array of NMOS and PMOS.
The present invention is by densely arranged rear-face contact hole 28,28 ' and metal layer on back 27, from 22 back side of silicon substrate by N+
Injection region 26 ' and the injection region P+ 26 are drawn；Subsequently through the bias voltage of circuit, i.e., on the metal layer on back of PMOS 27
Voltage is powered up, the adjunction ground level on the metal layer on back 27 of NMOS is kept away so that N trap 25 ' and p-well 25 are realized reverse-biased
Floater effect is exempted from.Meanwhile rear-face contact hole 28,28 ' carries out dense arrangement on silicon substrate 22, and filled in contact hole
It is the metal materials such as tungsten, aluminium or copper, therefore is the good conductor of heat, the heat formed in bulk silicon substrate 22 can passes through
Densely arranged rear-face contact hole 28,28 ' and metal layer on back 27 quickly exports, to effectively prevent the self-heating effect of device
It answers.
Below by specific embodiment and attached drawing, to the forming method of the structure of semiconductor devices of the invention a kind of into
Row is described in detail.
Fig. 3-Figure 10 is please referred to, Fig. 3-Figure 10 is a kind of shape of the structure of semiconductor devices of a preferred embodiment of the present invention
At the processing step schematic diagram of method.As shown in Fig. 3-Figure 10, a kind of forming method of the structure of semiconductor devices of the invention,
It can be used to form the structure of above-mentioned semiconductor devices.By taking silicon substrate 22 as an example, a kind of structure of semiconductor devices of the invention
Forming method, it may include following steps:
First as shown in figure 3, conventional CMOS manufacturing process can be used, formed on the front of silicon substrate 22 shallow trench every
P-well 25, N+ source and drain 23 and grid 20 from 21, NMOS, and form N trap 25 ', P+ source and drain 23 ' and the grid 20 ' of PMOS.Its
In, the grid 20 of NMOS and the grid 20 ' of PMOS can be used polycrystalline silicon material and make to be formed.
Then, track media layer material after being deposited in the front face surface of silicon substrate 22, track media layer 32 after formation, and rear
Contact hole 30 and rear road metal interconnecting layer 31 are formed in track media layer 32.
Then as shown in figure 4, the silicon substrate 22 for completing stand CMOS is inverted, make the table of rear track media layer 32
Face and a slide glass 33 carry out stacking bonding.Conventional annealing (the first annealing) is carried out later.
Secondly, as shown in figure 5, can be carried out by techniques such as grinding, wet etching and chemically mechanical polishings to silicon substrate 22
Thinning back side makes 22 thickness of silicon substrate after being thinned be less than the injection depth of N trap 25 ' and p-well 25.
Again, as shown in fig. 6, number can be formed on the back side of silicon substrate 22 by photoetching, dry etching or wet etching
Amount and position backside trench corresponding with shallow trench isolation 21, and media filler is overleaf carried out in groove, medium can be two
One or more of silica, silicon nitride and silicon oxynitride, to form backside trench isolation 24.Wherein, backside trench is isolated
24 are aligned and are connected with about 21 shallow trench isolation formed in stand CMOS, to be formed complete between NMOS and PMOS
Isolation structure.
Then, as shown in fig. 7, P+ injection can be carried out in the p-well 25 of NMOS, in the N of PMOS by ion implantation technology
N+ injection is carried out in trap 25 '；Then, it is annealed (the second annealing), to carry out the activation of N+ injection and P+ injection, to be formed
The injection region N+ 26 ', the injection region P+ 26.Wherein, laser annealing or low-temperature annealing can be used in the second annealing, not influence routine
Under the premise of CMOS technology device performance, the activation of N+ injection and P+ injection is carried out.
Again, as shown in figure 8, can be deposited on the backside surface of silicon substrate 22 normal by the methods of chemical vapor deposition
Dielectric layer material is advised, back side dielectric layer 29 is formed.
Then, as shown in figure 9, by lithography and etching the definition in rear-face contact hole can overleaf be carried out in dielectric layer 29,
Rear-face contact hole carried out on silicon substrate 22 it is densely arranged, with reduce series resistance and increase thermal conductivity.The back side is carried out later to connect
The filling of contact hole, forms rear-face contact hole 28,28 ', and filling metal can be the compatible metal material of the CMOS technologies such as tungsten, aluminium or copper
Material.Filled rear-face contact hole 28,28 ' constitutes rear-face contact hole array, to form rear-face contact hole 28,28 ' and N+ note
Enter the Ohmic contact between area 26 ', the injection region P+ 26.
Finally, as shown in Figure 10, overleaf forming metal layer on back 27 on contact hole 28,28 '.Pass through metal layer on back 27
With the connection of power supply, ground, Lai Shixian N trap 25 ' is connected with the power supply of p-well 25 and ground connection.
In conclusion the present invention, which passes through, stacks technique and backside trench technique, so that without using SOI substrate, so that it may make
Produce the NMOS being isolated entirely and PMOS device；Meanwhile passing through back side N+ injection and P+ injection, rear-face contact hole and metal layer on back
Technique, realizes the p-well ground connection of NMOS, and the N trap of PMOS connects power supply；Also, rear-face contact hole is intensively arranged on a silicon substrate
Cloth, can reduce series resistance and increase thermal conductivity prevents so as to avoid the floater effect and self-heating effect of SOI device
The deterioration of device performance.The present invention carries out the manufacture of semiconductor devices, therefore the semiconductor with routine using conventional silicon substrate
Process compatible.
Above is merely a preferred embodiment of the present invention, the scope of patent protection that embodiment is not intended to limit the invention,
Therefore all to change with equivalent structure made by specification and accompanying drawing content of the invention, it similarly should be included in of the invention
In protection scope.
Claims (10)
1. a kind of structure of semiconductor devices characterized by comprising set on multiple knots of semiconductor substrate front and back
Structure；Wherein,
Include: set on the positive structure of the semiconductor substrate
Shallow trench isolation on the front of the semiconductor substrate, well region, source and drain and grid；
Rear track media layer in the front face surface of the semiconductor substrate, and it is located at the rear road track media Ceng Zhonghou
Metal interconnecting layer；
Structure set on the semiconductor substrate back side includes:
Backside trench isolation and heavily-doped implant area on the back side of the semiconductor substrate；Phase is isolated in the backside trench
Vicinal is connected in the top of the shallow trench isolation, the heavily-doped implant area positioned at the top of the well region；
Back side dielectric layer on the backside surface of the semiconductor substrate, is located in the back side dielectric layer and lower end connects
Multiple rear-face contact holes of the heavily-doped implant layer, and the back metal being connected on the upper end of the rear-face contact hole
Layer.
2. the structure of semiconductor devices according to claim 1, which is characterized in that be made of the multiple rear-face contact hole
Rear-face contact hole array.
3. the structure of semiconductor devices according to claim 1, which is characterized in that be filled in the backside trench isolation
Dielectric material.
4. the structure of semiconductor devices according to claim 1, which is characterized in that the structure of the semiconductor devices is
NMOS or PMOS structure.
5. the structure of semiconductor devices according to claim 1, which is characterized in that the structure of the semiconductor devices is
The alternately arranged structure of NMOS and PMOS, shallow trench isolation and backside trench between the NMOS and PMOS by being aligned up and down
Isolation is formed by full isolation structure and is isolated.
6. the structure of semiconductor devices according to claim 4 or 5, which is characterized in that when the knot of the semiconductor devices
When structure is NMOS structure, the well region is p-well, and the heavily-doped implant area is the injection region P+；When the knot of the semiconductor devices
When structure is PMOS structure, the well region is N trap, and the heavily-doped implant area is the injection region N+.
7. a kind of forming method of the structure of semiconductor devices characterized by comprising
Semi-conductive substrate is provided, forms shallow trench isolation, p-well, the N+ source and drain of NMOS on the front of the semiconductor substrate
And grid, N trap, P+ source and drain and the grid of PMOS；
Track media layer after deposit is formed in the front face surface of the semiconductor substrate, and contact hole is formed in rear track media layer
With rear road metal interconnecting layer；
The semiconductor substrate is inverted, bonds the surface of the rear track media layer with a slide glass；Then it carries out
First annealing；
The semiconductor substrate is carried out back thinning, the semiconductive substrate thickness after being thinned is made to be less than the note of N trap and p-well
Enter depth；
Backside trench is formed on the back side of the semiconductor substrate, and media filler, formation and shallow ridges are overleaf carried out in groove
The backside trench isolation that slot isolation is connected up and down and is aligned, to form the full isolation structure between NMOS and PMOS；
P+ injection is carried out in the p-well of NMOS, and N+ injection is carried out in the N trap of PMOS；Then the second annealing is carried out, N+ note is carried out
Enter the activation with P+ injection；
Deposit forms back side dielectric layer on the backside surface of the semiconductor substrate, and overleaf carries out the back side in dielectric layer and connect
The definition and filling of contact hole carry out rear-face contact hole overleaf in dielectric layer densely arranged, constitute rear-face contact hole array, from
And form the Ohmic contact between rear-face contact hole and N+ injection, P+ injection；
Metal layer on back overleaf is formed on contact hole, by the connection of metal layer on back and power supply, ground, Lai Shixian N trap and p-well
Power supply connection and ground connection.
8. the forming method of the structure of semiconductor devices according to claim 7, which is characterized in that the semiconductor substrate
For the compound substrate of the simple substance substrate or indium phosphide of silicon, germanium, silicon carbide or gallium nitride substrate or indium phosphide.
9. the forming method of the structure of semiconductor devices according to claim 7, which is characterized in that the backside trench every
Filled media from is one or more of silica, silicon nitride and silicon oxynitride.
10. the forming method of the structure of semiconductor devices according to claim 7, which is characterized in that second annealing
For laser annealing or low-temperature annealing.
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| CN112582338A (en) * | 2020-12-02 | 2021-03-30 | 上海集成电路研发中心有限公司 | Process method for realizing back extraction |
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| US9812580B1 (en) * | 2016-09-06 | 2017-11-07 | Qualcomm Incorporated | Deep trench active device with backside body contact |
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| KR100281109B1 (en) * | 1997-12-15 | 2001-03-02 | 김영환 | Silicon on insulator device and method for fabricating the same |
| US20020190322A1 (en) * | 2000-08-31 | 2002-12-19 | Mouli Chandra V. | SOI CMOS device with reduced DIBL |
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