CN109509726B - 扇出型半导体封装件 - Google Patents
扇出型半导体封装件 Download PDFInfo
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- CN109509726B CN109509726B CN201810336638.0A CN201810336638A CN109509726B CN 109509726 B CN109509726 B CN 109509726B CN 201810336638 A CN201810336638 A CN 201810336638A CN 109509726 B CN109509726 B CN 109509726B
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Abstract
本发明提供一种扇出型半导体封装件。所述扇出型半导体封装件包括具有通孔的芯构件。半导体芯片位于所述通孔中,并且包括具有连接焊盘的有效表面和与所述有效表面背对的无效表面。包封剂包封所述芯构件和所述半导体芯片的至少部分,并且填充所述通孔的至少部分。连接构件位于所述芯构件和所述半导体芯片的所述有效表面上,并且包括电连接到所述连接焊盘的重新分布层。在所述芯构件的设置有所述连接构件的下部中,所述芯构件包括从所述通孔的壁向外贯穿到所述芯构件的外侧表面的槽部。
Description
本申请要求于2017年9月15日在韩国知识产权局提交的第10-2017-0118705号韩国专利申请的优先权的权益,所述韩国专利申请的全部内容通过引用被包含于此。
技术领域
本公开涉及一种半导体封装件,更具体地,涉及一种电连接结构延伸到设置有半导体芯片的区域的外部的扇出型半导体封装件。
背景技术
与半导体芯片相关的技术的发展的最近重大趋势是减小半导体芯片的尺寸。因此,在封装技术领域,随着对小尺寸半导体芯片的需求等的快速增长,需要实现具有紧凑尺寸同时包括多个引脚的半导体封装件。
为了满足如上所述的技术需求而提出的一种类型的半导体封装技术为扇出型半导体封装件。扇出型封装件具有紧凑尺寸并且使得连接端子从设置有半导体芯片的区域向外重新分布。
发明内容
本公开的一方面可提供一种扇出型半导体封装件,所述扇出型半导体封装件包括设置在半导体芯片被包封的区域中并且可支撑所述扇出型半导体封装件的芯构件。如果需要,所述芯构件可包括布线,并且尽管包括芯构件,也可大体防止包封剂中的空隙的问题。
根据本公开的一方面,所述芯构件可包括槽部,以用作芯构件的下部中的空气路径。
根据本公开的一方面,一种扇出型半导体封装模块可包括具有通孔的芯构件。半导体芯片位于所述通孔中,并且包括具有连接焊盘的有效表面和与所述有效表面背对的无效表面。包封剂包封所述芯构件和所述半导体芯片的至少部分,并且填充所述通孔的至少部分。连接构件位于所述芯构件和所述半导体芯片的所述有效表面上,并且包括电连接到所述连接焊盘的重新分布层。在所述芯构件的设置有所述连接构件的下部中,所述芯构件包括从所述通孔的壁向外贯穿到所述芯构件的外侧表面的槽部。
根据本公开的另一方面,一种扇出型半导体封装模块可包括:连接构件;电子组件,位于所述连接构件上;及芯构件,位于所述连接构件上,包括通孔,并且所述电子组件位于所述通孔内,并且还包括沿着所述芯构件的下表面的一个或更多个槽,所述一个或更多个槽面对所述连接构件并且从所述通孔延伸到所述芯构件的外周方向上的外表面。
根据本公开的另一方面,一种扇出型半导体封装模块可包括:连接构件,具有上表面和下表面并且包括重新分布层以及从所述下表面突出并且电连接到所述重新分布层的电连接结构;半导体芯片,位于所述连接构件的所述上表面上方,包括位于所述半导体芯片的下表面上并面对所述连接构件的连接焊盘,所述连接焊盘电连接到所述连接构件的所述重新分布层;芯构件,位于所述连接构件的所述上表面方,包括容纳所述半导体芯片的通孔、电连接到所述连接构件的所述重新分布层的布线层以及面对所述连接构件并且从所述通孔的相应的内角延伸到所述芯构件的外周方向上的相应的外角的第一槽、第二槽、第三槽和第四槽;包封剂,位于所述半导体芯片和所述芯构件上、位于所述半导体芯片和所述芯构件之间的所述通孔中以及位于所述第一槽至所述第四槽的至少部分中。
附图说明
通过下面结合附图进行的详细描述,本公开的以上和其他方面、特征和优点将被更清楚地理解,在附图中:
图1是示出电子装置***的示例的示意性框图;
图2是示出电子装置的示例的示意性透视图;
图3A和图3B是示出扇入型半导体封装件在被封装之前和之后的状态的示意性截面图;
图4是示出扇入型半导体封装件的封装工艺的示意性截面图;
图5是示出扇入型半导体封装件安装在中介基板上并最终被安装在电子装置的主板上的示意性截面图;
图6是示出扇入型半导体封装件嵌在中介基板中并最终被安装在电子装置的主板上的示意性截面图;
图7是示出扇出型半导体封装件的示意性截面图;
图8是示出扇出型半导体封装件安装在电子装置的主板上的示意性截面图;
图9是示出示例性扇出型半导体封装件的示意性截面图;
图10是图9的扇出型半导体封装件的沿着I-I′线截取的示意性平面图;
图11是示出图9的扇出型半导体封装件的包封工艺的示意图;
图12是示出另一示例性扇出型半导体封装件的示意性截面图;
图13是图12的扇出型半导体封装件的沿着II-II′线截取的示意性平面图;
图14是示出另一示例性扇出型半导体封装件的示意性截面图;及
图15是图14的扇出型半导体封装件的沿着III-III′线截取的示意性平面图。
具体实施方式
在下文中,将参照附图描述本公开的示例性实施例。在附图中,为了清晰,组件的形状、尺寸等可被夸大或缩小。
这里,与附图相关的下侧、下部、下表面等用于指朝向扇出型半导体封装件的安装表面的方向,而上侧、上部、上表面等用于指与朝向扇出型半导体封装件的安装表面的方向相反的方向。然而,这些方向是为了便于解释而限定的,权利要求不被如上所述限定的方向具体限制。
在说明书中的组件与另一组件的“连接”的含义包括通过粘合层的间接连接以及两个组件之间的直接连接。此外,“电连接”意味着包括物理连接和物理断开的概念。可理解的是,当使用“第一”和“第二”来指代元件时,该元件不会由此受限。它们仅用于将该元件与其他元件区分开的目的,而不会限制元件的顺序或重要性。在一些情况下,在不脱离在此阐述的权利要求的范围的情况下,第一元件可被称作为第二元件。类似地,第二元件也可被称作为第一元件。
在此使用的术语“示例性实施例”不指同一示例性实施例,而是被提供来突出与另一示例性实施例的特征或特性不同的特定的特征或特性。然而,在此提供的示例性实施例被理解为能够通过彼此全部组合或部分组合来实现。例如,除非在此提供了相反或对立的描述,否则特定的示例性实施例中描述的一个元件即使在另一示例性实施例中没有被描述,也可被理解为与另一示例性实施例相关的描述。
在此使用的术语仅用于描述示例性实施例,而非限制本公开。在这种情况下,除非上下文中另外解释,否则单数形式包括复数形式。
电子装置
图1是示出电子装置***的示例的示意性框图。
参照图1,电子装置1000可将主板1010容纳在其中。主板1010可包括物理连接和/或电连接到主板1010的芯片相关组件1020、网络相关组件1030、其他组件1040等。这些组件可连接到将在下面描述的其他元件,以形成各种信号线1090。
芯片相关组件1020可包括存储器芯片(诸如易失性存储器(例如,动态随机存取存储器(DRAM))、非易失性存储器(例如,只读存储器(ROM))、闪存等)。芯片相关组件1020还可包括应用处理器芯片(诸如中央处理器(例如,中央处理单元(CPU))、图形处理器(例如,图形处理单元(GPU))、数字信号处理器、密码处理器、微处理器、微控制器等)。芯片相关组件1020还可包括逻辑芯片(诸如模拟数字(ADC)转换器、专用集成电路(ASIC)等)。然而,芯片相关组件1020不限于此,而是还可包括其他类型的芯片相关组件。此外,芯片相关组件1020可彼此组合。
网络相关组件1030可包括被指定为根据诸如以下的协议操作的组件:无线保真(Wi-Fi)(电气和电子工程师协会(IEEE)802.11族等)、全球微波互联接入(WiMAX)(IEEE802.16族等)、IEEE 802.20、长期演进技术(LTE)、演进数据最优化(Ev-DO)、高速分组接入+(HSPA+)、高速下行分组接入+(HSDPA+)、高速上行分组接入+(HSUPA+)、增强型数据GSM环境(EDGE)、全球移动通讯***(GSM)、全球定位***(GPS)、通用分组无线业务(GPRS)、码分多址(CDMA)、时分多址(TDMA)、数字增强型无绳通信(DECT)、蓝牙、3G协议、4G协议和5G协议以及在上述协议之后指定的任何其他无线和有线协议。然而,网络相关组件1030不限于此,而是还可包括被指定为按照各种其他无线或有线标准或协议操作的组件。此外,网络相关组件1030可彼此组合,也可与上面描述的芯片相关组件1020一起组合。
其他组件1040可包括高频电感器、铁氧体电感器、功率电感器、铁氧体磁珠、低温共烧陶瓷(LTCC)、电磁干扰(EMI)滤波器、多层陶瓷电容器(MLCC)等。然而,其他组件1040不限于此,而是还可包括用于各种其他用途的无源组件等。此外,其他组件1040可彼此组合,可与上面描述的芯片相关组件1020和/或网络相关组件1030一起组合。
基于电子装置1000的类型,电子装置1000可包括可以物理连接或电连接到主板1010或可以不物理连接或电连接到主板1010的其他组件。这些其他组件可包括例如相机1050、天线1060、显示器1070或电池1080。可被包括的其他组件(但未示出)包括音频编码解码器、视频编码解码器、功率放大器、指南针、加速计、陀螺仪、扬声器、大容量存储单元(例如,硬盘驱动器)、光盘(CD)驱动器、数字多功能光盘(DVD)驱动器等。然而,其他组件不限于此,而是还可根据电子装置1000的类型等包括用于各种用途的其他组件。
电子装置1000可以为智能电话、个人数字助理(PDA)、数码摄像机、数码相机、网络***、计算机、监视器、平板个人计算机(PC)、膝上型PC、上网本PC、电视机、视频游戏机、智能手表、汽车组件等。然而,电子装置1000不限于此,而可以是任何其他电子装置。
图2是示出电子装置的示例的示意性透视图。
参照图2,可在如上所述的各种电子装置1000中使用用于各种目的的半导体封装件。例如,主板1110可被容纳在智能电话1100的主体1101中,并且各种电子组件1120可物理连接或电连接到主板1110。此外,可以物理连接或电连接到主板1110或者可以不物理连接或电连接到主板1110的其他组件(诸如相机模块1130)可被容纳在主体1101中。电子组件1120中的一些可以为芯片相关组件,半导体封装件100可以为例如芯片相关组件中的应用处理器,但不限于此。电子装置不是必须局限于智能电话1100,而可以为如上所述的其他电子装置。
半导体封装件
通常,多个微电子电路集成在半导体芯片中。半导体芯片本身不可用作成品产品,并且还可能会由于外部物理冲击或化学冲击而损坏。半导体芯片可被封装并且在封装状态下用在电子装置等中。
需要半导体封装的一个原因是在电连接方面半导体芯片与电子装置的主板之间的电路宽度存在差异。详细地,半导体芯片的连接焊盘的尺寸以及这些连接焊盘之间的间距非常精细,而电子装置中使用的主板的组件安装焊盘的尺寸以及这些焊盘之间的间距显著大于半导体芯片的连接焊盘的尺寸以及连接焊盘之间的间距。因此,可能难以将半导体芯片直接安装在主板上,需要用于缓解半导体芯片与主板之间的电路宽度的差异的封装技术。
通过封装技术制造的半导体封装件可基于其结构和用途而分为扇入型半导体封装件和扇出型半导体封装件。
在下文中,将参照附图更详细地描述扇入型半导体封装件和扇出型半导体封装件。
扇入型半导体封装件
图3A和图3B是示出扇入型半导体封装件在被封装之前和之后的状态的示意性截面图。
图4是示出扇入型半导体封装件的封装工艺的示意性截面图。
参照图3A和图3B,半导体芯片2220可以为例如处于裸露状态的集成电路(IC),并且可包括:主体2221,通过硅(Si)、锗(Ge)、砷化镓(GaAs)等制成;连接焊盘2222,形成在主体2221的一个表面上并包括诸如铝(Al)等的导电材料;诸如氧化物膜、氮化物膜等的钝化层2223,形成在主体2221的一个表面上并且覆盖连接焊盘2222的至少部分。由于连接焊盘2222相对小,因此难以将集成电路(IC)安装在中等尺寸等级的印刷电路板(PCB)上或电子装置的主板等上。
因此,连接构件2240可基于半导体芯片2220的尺寸而形成,以使连接焊盘2222重新分布。连接构件2240可通过如下步骤形成:使用诸如感光介电(PID)树脂的绝缘材料在半导体芯片2220上形成绝缘层2241;形成为连接焊盘2222提供开口的通路孔(via hole)2243h;然后形成布线图案2242和过孔2243。可形成保护连接构件2240的钝化层2250。可在钝化层2250中形成开口2251,并且可在开口2251中形成凸块下金属层2260等。如此,可制造包括例如半导体芯片2220、连接构件2240、钝化层2250和凸块下金属层2260的扇入型半导体封装件2200。
如上所述,扇入型半导体封装件可具有半导体芯片的所有连接焊盘(例如,输入/输出(I/O)端子)设置在半导体芯片内部的封装形式。封装件可具有优异的电特性并且以低成本生产。因此,安装在智能电话中的许多元件已按照扇入型半导体封装形式来制造。详细地,安装在智能电话中的许多元件已被开发为在具有紧凑尺寸的同时实现快速的信号传输。
然而,由于在扇入型半导体封装件中需要将所有I/O端子设置在半导体芯片内部,因此扇入型半导体封装件具有大的空间局限性。难以将这种结构应用于具有大量的I/O端子的半导体芯片或具有紧凑尺寸的半导体芯片。此外,由于上面描述的缺点,可能不能将扇入型半导体封装件直接安装在电子装置的主板上来使用。即使当半导体芯片的I/O端子的尺寸和这些I/O端子之间的间距通过重新分布工艺而增大时,I/O端子的尺寸和间隔可能不足以使扇入型半导体封装件直接安装在电子装置的主板上。
图5是示出扇入型半导体封装件安装在中介基板上并最终被安装在电子装置的主板上的示意性截面图。
图6是示出扇入型半导体封装件嵌在中介基板中并最终被安装在电子装置的主板上的示意性截面图。
参照图5,在扇入型半导体封装件2200中,半导体芯片2220的连接焊盘2222(即,I/O端子)可通过中介基板2301被重新分布。扇入型半导体封装件2200可在其安装在中介基板2301上的情况下最终安装在电子装置的主板2500上。焊球2270等可通过底部填充树脂2280等固定,半导体芯片2220的外侧可覆盖有成型材料2290等。可选地,参照图6,扇入型半导体封装件2200可嵌在单独的中介基板2302中。在扇入型半导体封装件2200嵌在中介基板2302中的情况下,半导体芯片2220的连接焊盘2222(即,I/O端子)可通过中介基板2302被重新分布,并且扇入型半导体封装件2200可最终安装在电子装置的主板2500上。
如上所述,可能难以将扇入型半导体封装件直接安装在电子装置的主板上来使用。因此,扇入型半导体封装件可安装在单独的中介基板上,然后通过封装工艺安装在电子装置的主板上,或者可在其嵌在中介基板中的状态下安装在电子装置的主板上来使用。
扇出型半导体封装件
图7是示出扇出型半导体封装件的示意性截面图。
参照图7,在扇出型半导体封装件2100中,例如,半导体芯片2120的外侧可由包封剂2130保护,并且半导体芯片2120的连接焊盘2122可通过连接构件2140被重新分布到半导体芯片2120的外部。钝化层2150还可形成在连接构件2140上,并且凸块下金属层2160可形成在钝化层2150的开口中。焊球2170可形成在凸块下金属层2160上。半导体芯片2120可以为包括主体2121、连接焊盘2122、钝化层(未示出)等的集成电路(IC)。连接构件2140可包括绝缘层2141、形成在绝缘层2141上的重新分布层2142以及将连接焊盘2122和重新分布层2142彼此电连接的过孔2143。
扇出型半导体封装件具有半导体芯片的I/O端子可通过形成在半导体芯片上的连接构件被重新分布并设置在半导体芯片的外部的形式。在扇入型半导体封装件中,半导体芯片的所有I/O端子需要设置在半导体芯片的内部。因此,在扇入型半导体封装件中,当半导体芯片的尺寸减小时,焊球的尺寸和节距需要减小,使得可能不能使用标准化的焊球布局。另一方面,如上所述,扇出型半导体封装件具有半导体芯片的I/O端子通过形成在半导体芯片上的连接构件被重新分布并设置在半导体芯片的外部的形式。因此,即使当半导体芯片的尺寸减小时,也仍可在扇出型半导体封装件中按照原样使用标准化的焊球布局,使得扇出型半导体封装件可在不使用单独的中介基板的情况下安装在电子装置的主板上。
图8是示出扇出型半导体封装件安装在电子装置的主板上的示意性截面图。
参照图8,扇出型半导体封装件2100可通过焊球2170等安装在电子装置的主板2500上。扇出型半导体封装件2100包括连接构件2140,连接构件2140形成在半导体芯片2120上并且能够使连接焊盘2122重新分布到扇出区域(半导体芯片2120的竖直区域的外部)。因此,可在扇出型半导体封装件2100中按照原样使用标准化的焊球布局。结果,扇出型半导体封装件2100可在不使用单独的中介基板等的情况下安装在电子装置的主板2500上。
由于扇出型半导体封装件可在不使用单独的中介基板的情况下安装在电子装置的主板上,因此扇出型半导体封装件可被实现为具有比使用中介基板的扇入型半导体封装件的厚度小的厚度。因此,扇出型半导体封装件可被小型化和纤薄化。此外,扇出型半导体封装件具有优异的热特性和电特性,使得其特别适用于移动产品。因此,扇出型半导体封装件可被实现为比使用印刷电路板(PCB)的通常的叠层封装(POP)类型更紧凑的形式,并且可解决由于翘曲现象的发生而导致的问题。
同时,扇出型半导体封装指如上所述的用于将半导体芯片安装在电子装置的主板等上并且保护半导体芯片免受外部冲击影响的封装技术,并且扇出型半导体封装是与诸如中介基板等的印刷电路板(PCB)(尺寸、用途等与扇出型半导体封装件的尺寸、用途不同并且具有嵌入其中的扇入型半导体封装件)的概念不同的概念。
在下文中,将参照附图描述一种扇出型半导体封装件,该扇出型半导体封装件包括设置在半导体芯片被包封的区域中并且支撑扇出型半导体封装件的芯构件。如果需要,芯构件可包括布线。下面描述的扇出型半导体封装件可大体防止在其包封剂中的空隙的问题。
图9是示出示例性扇出型半导体封装件的示意性截面图。
图10是图9的扇出型半导体封装件的沿着I-I′线截取的示意性平面图。
参照图9和图10,根据本公开的示例性实施例的扇出型半导体封装件100A可包括:芯构件110,具有通孔110H;半导体芯片120,可设置在芯构件110的通孔110H中,并且可具有有效表面和与有效表面背对的无效表面,其中,该有效表面上设置有连接焊盘122;包封剂130,可包封芯构件110和半导体芯片120的至少部分,并且可填充通孔110H的至少部分;连接构件140,可设置在芯构件110和半导体芯片120的有效表面上,并且可包括电连接到连接焊盘122的重新分布层142;钝化层150,可设置在连接构件140上;凸块下金属层160,设置在钝化层150的开口151中;电连接结构170,设置在钝化层150上并且连接到凸块下金属层160。
半导体封装件可通常通过使用包封剂简单地包封半导体芯片并且在被包封的半导体芯片的有效表面上形成重新分布层来制造。然而,难以控制这种半导体封装件的翘曲,并且在各种布线设计方面存在局限性。为了解决这种问题,芯构件可在半导体芯片被包封的区域中设置有通孔。因此,可通过芯构件控制半导体封装件的翘曲,并且可通过在芯构件中设计布线而使各种类型的布线设计变得可行。然而,当引入芯构件时,在诸如通孔的壁与包封剂之间、半导体芯片的侧表面与包封剂之间和/或包封剂与重新分布层的绝缘层之间的位置处可能会产生空隙。由于这些空隙导致可能会发生诸如分层等问题。
在根据示例性实施例的扇出型半导体封装件100A中,一个或更多个槽部GA1可形成在芯构件110的下部中。槽部GA1可从通孔110H的壁向外朝向芯构件110的外侧表面贯穿到芯构件110中。具有这种形式的槽部GA1可用作空气路径,因此防止当使用包封剂130包封半导体芯片和芯构件时产生空隙。也就是说,当使用包封剂130包封半导体芯片120和芯构件110时,包封剂130可向下填充通过槽部GA1或者填充至芯构件110的外部处的锯割线或切割线,以防止产生空隙。为了应对通过包封剂仅部分填充的风险,可通过在添加包封剂130之后使用压力箱(pressureoven)对任意未填充的区域进行补偿。当使用如上所述的通过压力填充包封剂的方式时,可几乎实现大体无空隙的结构。
在下文中,将更详细地描述根据示例性实施例的扇出型半导体封装件100A中包括的各个组件。
芯构件110可基于其材料来提高扇出型半导体封装件100A的刚性,并且可用于确保包封剂130的厚度的均匀性。当芯构件110中形成布线层、过孔等时,扇出型半导体封装件100A可被用作叠层封装(POP)类型封装件。芯构件110可具有通孔110H,并且半导体芯片120设置在通孔110H中且与芯构件110分开预定距离,并且半导体芯片120的侧表面被芯构件110围住。然而,这种形式仅是示例,并且可进行各种修改以具有其他形式,芯构件110可基于这种形式而执行另一种功能。
芯构件110可包括绝缘层111。绝缘材料可用作绝缘层111的材料。绝缘材料可以为诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂、热固性树脂或热塑性树脂与无机填料混合或者与无机填料一起被浸入诸如玻璃纤维(或玻璃布或玻璃织物)的芯材料中的树脂,例如,半固化片、ABF(Ajinomoto build-up film)、FR-4、双马来酰亚胺-三嗪树脂(BT)等。可使用具有刚性的材料(诸如包括玻璃纤维的半固化片等)作为绝缘层111的材料,芯构件110可用作支撑构件,用于控制扇出型半导体封装件100A的翘曲。
一个或更多个槽部GA1可形成在芯构件110的下部中。例如,槽部GA1可形成在芯构件110的下部的四个角区域中。各个槽部GA1可从通孔110H的壁向外贯穿到芯构件110的外侧表面。如上所述,具有这种形式的槽部GA1可用作空气路径,因此防止在使用包封剂130包封半导体芯片和芯构件时产生空隙或使在使用包封剂130包封半导体芯片和芯构件时产生的空隙最小化。沿着芯构件110的边缘贯穿芯构件110的下部的槽部GA2也可形成在芯构件110的下部的一个或更多个外侧部中。各个槽部GA1可连接到槽部GA2,以有效地防止在形成包封剂130时产生空隙或使在形成包封剂130时产生的空隙最小化。
芯构件110的通孔110H可具有锥形形状,并且芯构件110的壁以预定角度(θ)倾斜。该锥形形状可以为通孔110H的上开口区域的宽度大于通孔110H的下开口区域的宽度的形状。也就是说,通孔可具有近似倒梯形形状。当芯构件110的通孔110H具有上面描述的锥形形状时,可更容易形成包封剂130,以进一步减少空隙的产生。
为了便于解释,槽部GA1和GA2在图9的截面图中被示出为完全贯穿芯构件110的下部,但是如图10的平面图中示出的,槽部GA1可形成在芯构件110的下部的特定区域中,多个槽部GA1可基于设计而不同地形成。
半导体芯片120可以是按照在单个芯片中集成数量为数百至数百万的元件或更多的元件而设置的集成电路(IC)。IC可以是例如处理器芯片(更具体地,应用处理器(AP)),诸如中央处理器(例如,CPU)、图形处理器(例如,GPU)、现场可编程门阵列(FPGA)、数字信号处理器、密码处理器、微处理器、微控制器等,但不限于此。IC可以是诸如模拟数字转换器、专用IC(ASIC)等的逻辑芯片或者诸如易失性存储器(例如,DRAM)、非易失性存储器(例如,ROM)、闪存等的储存芯片。上述元件也可彼此组合。
半导体芯片120可基于有效晶圆而形成。半导体芯片120可包括主体121,主体121具有可以为硅(Si)、锗(Ge)、砷化镓(GaAs)等的基体材料。各种电路可形成在主体121上。连接焊盘122可将半导体芯片120电连接到其他组件。连接焊盘122中的每个的材料可以为诸如铝(Al)等的导电材料。使连接焊盘122暴露的钝化层123可形成在主体121上,并且可以为氧化膜、氮化膜等或氧化层和氮化层的双层。连接焊盘122的下表面可通过钝化层123而相对于包封剂130的下表面具有台阶,使得包封剂130可填充钝化层123和连接构件140之间的空间的至少部分。台阶可防止包封剂130流入到连接焊盘122的下表面中。绝缘层(未示出)等还可设置在其他需要的位置中。半导体芯片120可以为裸片。重新分布层(未示出)可形成在半导体芯片120的有效表面,凸块(未示出)等可连接到连接焊盘122。
包封剂130可保护芯构件110、半导体芯片120等。包封剂130的形式不被具体限制,而可以为包封剂130围住芯构件110、半导体芯片120等的至少部分的形式。例如,包封剂130可覆盖芯构件110和半导体芯片120的无效表面,并且可填充通孔110H的壁与半导体芯片120的侧表面之间的空间。包封剂130也可填充半导体芯片120的钝化层123和连接构件140之间的空间的至少部分。包封剂130可填充通孔110H,因此用作粘合剂并且减小半导体芯片120的弯曲。包封剂130可填充槽部GA1和GA2的至少部分。也就是说,可执行包封工艺,以凭借包封剂130被排放到槽部GA1和GA2中而防止空隙缺陷或使空隙缺陷最小化。
包封剂130的材料不被具体限制。例如,绝缘材料可用作包封剂130的材料。绝缘材料可以为诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂、热固性树脂或热塑性树脂与无机填料混合或者与无机填料一起被浸入诸如玻璃纤维(或玻璃布或玻璃织物)的芯材料中的树脂,例如,半固化片、ABF、FR-4或BT等。可选地,感光包封(PIE)树脂也可用作绝缘材料。
连接构件140可使半导体芯片120的连接焊盘122重新分布。具有各种功能的半导体芯片120的数十至数百的连接焊盘122可通过连接构件140被重新分布,并且可基于其功能而通过电连接结构170物理连接或电连接到外部源。连接构件140可包括设置在芯构件110和半导体芯片120的有效表面上的绝缘层141、设置在绝缘层141上的重新分布层142以及贯穿绝缘层141并且将连接焊盘122和重新分布层142彼此连接的过孔143。图中将连接构件140示出为包括一个绝缘层、一个重新分布层和一个过孔层,但是连接构件140也可包括更多数量的绝缘层、重新分布层和过孔层。
绝缘层141中的每个的材料可以为绝缘材料。诸如PID树脂的感光绝缘材料也可用作绝缘材料。也就是说,绝缘层141中的每个可以为感光绝缘层。当绝缘层141具有感光性质时,绝缘层141可形成为具有较小的厚度,并且可更容易实现过孔143的精细的节距。绝缘层141中的每个可以为包括绝缘树脂和无机填料的感光绝缘层。当绝缘层141包括多层时,绝缘层141的材料可彼此相同或可彼此不同。当绝缘层141包括多层时,绝缘层141可彼此一体化,使得多层之间的边界可以不明显。
重新分布层142可大体用于使连接焊盘122重新分布。重新分布层142中的每个的材料可以为导电材料,诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金。重新分布层142可基于其相应的层的设计而执行各种功能。例如,重新分布层142可包括接地(GND)图案、电力(PWR)图案、信号(S)图案等。除了接地(GND)图案、电力(PWR)图案之外,信号(S)图案可包括诸如数据信号等的各种信号等。重新分布层142可包括过孔焊盘图案、电连接结构焊盘图案等。重新分布层142中的每个可具有近似0.5μm至15μm的厚度。
过孔143可将形成在不同层上的重新分布层142、连接焊盘122等彼此电连接,结果在扇出型半导体封装件100A中形成电路径。过孔143中的每个的材料可以为例如导电材料,诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金。过孔143中的每个可完全被导电材料填充,或导电材料也可沿着过孔中的每个的壁形成。过孔143可具有诸如锥形形状、圆柱形状等形状。
钝化层150可保护连接构件140免受外部物理损坏或化学损坏。钝化层150可具有使连接构件140的重新分布层142的至少部分暴露的开口。形成在钝化层150中的开口151的数量可以为数十至数千。钝化层150的材料不被具体限制,且可以为绝缘材料。绝缘材料可以为诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂、热固性树脂或热塑性树脂与无机填料混合或与无机填料一起被浸入诸如玻璃纤维(或玻璃布或玻璃织物)的芯材料中的树脂,例如,半固化片、ABF、FR-4、BT等。可选地,可使用阻焊剂。
凸块下金属层160可提高电连接结构170的连接可靠性,以提高扇出型半导体封装件100A的板级可靠性。凸块下金属层160可连接到连接构件140的通过钝化层150的开口151暴露的重新分布层142。凸块下金属层160可使用导电金属通过金属化方法形成在钝化层150的开口151中。
电连接结构170可物理连接或电连接扇出型半导体封装件100A。例如,扇出型半导体封装件100A可通过电连接结构170安装在电子装置的主板上。电连接结构170中的每个可由例如焊料等的导电材料形成。然而,电连接结构170中的每个的材料不被具体限制于此。电连接结构170中的每个可以为焊盘(land)、球、引脚等。电连接结构170可形成为多层结构或单层结构。当电连接结构170形成为多层结构时,电连接结构170可包括铜(Cu)柱和焊料。当电连接结构170形成为单层结构时,电连接结构170可包括锡银焊料或铜(Cu)。然而,电连接结构170不限于此。
电连接结构170的数量、间距、形式等不被具体限制,可基于设计细节来选择。电连接结构170可根据连接焊盘122的数量按照数十至数千的数量设置,或可按照数十至数千或更多的数量或者数十至数千或更少的数量设置。当电连接结构170为焊球时,电连接结构170可覆盖凸块下金属层160的延伸到钝化层150的一个表面上的侧表面,并且连接可靠性可更优异。
电连接结构170中的至少一个可设置在扇出区域中。扇出区域为从位于半导体芯片120竖直下方的区域向外的区域。与扇入型封装件相比,扇出型封装件可具有优异的可靠性,可实现多个输入/输出(I/O)端子,并且可有助于3D互联。此外,与球栅阵列(BGA)封装件、栅格阵列(LGA)封装件等相比,扇出型封装件可被制造为具有小厚度,并且可具有价格竞争力。
虽然图中未示出,但是如果需要,金属薄膜可形成在通孔110H的壁上,以散热或阻截电磁波。执行彼此相同或彼此不同的功能的多个半导体芯片120可设置在通孔110H中,诸如电感器、电容器等的单独的无源组件可设置在通孔110H中。例如,包括电感器、电容器等的表面安装技术(SMT)组件的无源组件可设置在钝化层150的表面上。
图11包括示出图9的扇出型半导体封装件的包封工艺的示意图。
参照图11,首先,可将具有通孔110H的芯构件110附着到带210。可提前通过激光处理在芯构件110中形成槽部GA1和GA2。可将半导体芯片120附着到带210的通过通孔110H暴露的区域。可通过在带210上层叠包封剂130以执行包封工艺。在通过槽部GA1和GA2填充包封剂130时,可增大压力,并且槽部GA1和GA2可用作排气口。因此,可防止在使用包封剂130包封半导体芯片120和芯构件110时产生空隙,或使在使用包封剂130包封半导体芯片120和芯构件110时产生的空隙最小化。当使用包封剂130包封半导体芯片120和芯构件110时,包封剂130可通过槽部GA1和GA2向下填充至芯构件110的外部的锯割线,以防止产生空隙。为了应对通过包封剂的仅部分填充,可在堆叠包封剂130后使用压力箱对未填充的区域进行补偿。当使用如上所述的通过压力填充包封剂的方式时,可几乎于实现大体无空隙的结构。填充在锯割线中的包封剂可在锯割扇出型半导体封装件时被去除。至少部分被填充有包封剂130的边缘区域的槽部GA2和内部设计区域的槽部GA1可保留在各个扇出型半导体封装件100A中。
图12是示出另一示例性扇出型半导体封装件的示意性截面图。
图13是图12的扇出型半导体封装件的沿着II-II′线截取的示意性平面图。
参照图12,在根据本公开的另一示例性实施例的扇出型半导体封装件100B中,芯构件110可包括与连接构件140接触的第一绝缘层111a;第一布线层112a,与连接构件140接触并可嵌在第一绝缘层111a的表面中;第二布线层112b,可设置在第一绝缘层111a的与接触连接构件140的表面背对的表面上;第二绝缘层111b,可设置在第一绝缘层111a上,并且可覆盖第二布线层112b;第三布线层112c,可设置在第二绝缘层111b上。第一布线层112a、第二布线层112b和第三布线层112c可电连接到连接焊盘122。第一布线层112a和第二布线层112b可通过贯穿第一绝缘层111a的第一过孔113a而彼此电连接,第二布线层112b和第三布线层112c可通过贯穿第二绝缘层111b的第二过孔113b而彼此电连接。
上述的槽部GA1和GA2可形成在第一绝缘层111a的下部中。因此,如上所述,在扇出型半导体封装件100B中,可防止在形成包封剂130时产生空隙或使在形成包封剂130产生的空隙最小化。为了更容易描述根据另一示例性实施例的扇出型半导体封装件100B的特征,在图12的截面图中,槽部GA1和GA2是不可见的,但通过在图13中所示的虚线示出了槽部GA1和GA2。槽部GA1和GA2的截面的形状可与图9中示出的槽部GA1和GA2的截面的形状相似,槽部GA1和GA2的至少部分可填充有包封剂130。
使第一布线层112a嵌在第一绝缘层111a中可显著减小或消除由于第一布线层112a的厚度产生的台阶,连接构件140的绝缘距离可因此变得恒定。也就是说,从连接构件140的重新分布层142到第一绝缘层111a的下表面的距离与从连接构件140的重新分布层142到半导体芯片120的连接焊盘122的距离之间的差异可以最小或没有差异。例如,该差异可小于第一布线层112a的厚度。因此,可更容易实现连接构件140的高密度布线设计。
芯构件110的第一布线层112a的下表面可设置在半导体芯片120的连接焊盘122的下表面之上的水平面上。此外,连接构件140的重新分布层142与芯构件110的第一布线层112a之间的距离可大于连接构件140的重新分布层142与半导体芯片120的连接焊盘122之间的距离。这可使得第一布线层112a凹入到第一绝缘层111a中。第一布线层112a凹入到第一绝缘层111a中,使得在第一绝缘层111a的下表面与第一布线层112a的下表面之间具有台阶,可防止包封剂130的材料流入而污染第一布线层112a。芯构件110的第二布线层112b可设置在半导体芯片120的有效表面和无效表面之间的水平面上。芯构件110可按照与半导体芯片120的厚度相对应的厚度形成。因此,形成在芯构件110中的第二布线层112b可设置在半导体芯片120的有效表面和无效表面之间的水平面上。
芯构件110的布线层112a、112b和112c的厚度可大于连接构件140的重新分布层142的厚度。由于芯构件110可具有等于或大于半导体芯片120的厚度的厚度,因此布线层112a、112b和112c可基于芯构件110的尺寸而具有大尺寸。另一方面,连接构件140的重新分布层142具有比布线层112a、112b和112c的尺寸相对小的尺寸,以实现纤薄化。
绝缘层111a和111b中的每个的材料不被具体限制,可使用绝缘材料。绝缘材料可以为诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂、热固性树脂或热塑性树脂与无机填料混合或者与无机填料一起被浸入诸如玻璃纤维(或玻璃布或玻璃织物)的芯材料中的树脂,例如,半固化片、ABF、FR-4或BT等。可选地,也可使用PID树脂作为绝缘材料。
布线层112a、112b和112c可用于使半导体芯片120的连接焊盘122重新分布。布线层112a、112b和112c中的每个的材料可以为导电材料,诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金。布线层112a、112b和112c可基于其相应的层的设计而执行各种功能。例如,布线层112a、112b和112c可包括接地(GND)图案、电力(PWR)图案、信号(S)图案等。除了接地(GND)图案、电力(PWR)图案之外,信号(S)图案可包括诸如数据信号等的各种信号等。布线层112a、112b和112c可包括过孔焊盘、布线焊盘、电连接结构焊盘等。
过孔113a和113b可将形成在不同层上的布线层112a、112b和112c彼此电连接,结果在芯构件110中形成电路径。过孔113a和113b中的每个的材料可以为导电材料。过孔113a和113b中的每个可完全被导电材料填充,或导电材料也可沿着通路孔中的每个的壁形成。过孔113a和113b中的每个可具有现有技术中已知的诸如锥形形状、圆柱形状等的所有形状。当形成用于第一过孔113a的孔时,第一布线层112a的焊盘中的一些可用作阻挡件,因此其可有利于第一过孔113a中的每个具有上表面的宽度大于下表面的宽度的锥形形状。第一过孔113a可与第二布线层112b的焊盘图案一体化。此外,当形成用于第二过孔113b的孔时,第二布线层112b的焊盘中的一些也可用作阻挡件,因此其可类似地有利于第二过孔113b中的每个具有上表面的宽度大于下表面的宽度的锥形形状。第二过孔113b可与第三布线层112c的焊盘图案一体化。
在下文中,省略了与上面描述的方面重复的方面的描述。
图14是示出另一示例性扇出型半导体封装件的示意性截面图。
图15是图14的扇出型半导体封装件的沿着III-III′线截取的示意性平面图。
参照图14,在根据本公开的另一示例性实施例的扇出型半导体封装件100C中,芯构件110可包括第一绝缘层111a;第一布线层112a和第二布线层112b,可分别设置在第一绝缘层111a的背对的表面上;第二绝缘层111b,可设置在第一绝缘层111a下方并且覆盖第一布线层112a;第三布线层112c,可设置在第二绝缘层111b下方;第三绝缘层111c,可设置在第一绝缘层111a上方并且可覆盖第二布线层112b;第四布线层112d,可设置在第三绝缘层111c上方。第一布线层112a、第二布线层112b、第三布线层112c和第四布线层112d可电连接到连接焊盘122。由于芯构件110可包括大量的布线层112a、112b、112c和112d,因此连接构件140可进一步被简化。这可抑制由于在制造过程期间产生的缺陷导致的良率的下降。第一布线层112a、第二布线层112b、第三布线层112c和第四布线层112d可通过贯穿第一绝缘层111a的第一过孔113a、贯穿第二绝缘层111b的第二过孔113b和贯穿第三绝缘层111c的第三过孔113c而彼此电连接。
上述槽部GA1和GA2可形成在位于第一绝缘层111a下方的第二绝缘层111b的下部中。因此,如上所述,在扇出型半导体封装件100C中,可防止在形成包封剂130时产生空隙或使得在形成包封剂130时产生的空隙最小化。在图14的截面图中,为了更容易描述根据另一示例性实施例的扇出型半导体封装件100C的特征,槽部GA1位于不可见的位置,但槽部GA1和GA2可如图15所示地形成。槽部GA1和GA2的截面的形状可与图9中所示的槽部GA1和GA2的截面的形状相似,槽部GA1和GA2的至少部分可填充有包封剂130。
第一绝缘层111a可具有比第二绝缘层111b的厚度或第三绝缘层111c的厚度大的厚度。第一绝缘层111a可相对较厚以保持刚性,可添加第二绝缘层111b和第三绝缘层111c以形成较多数量的布线层112c和112d。第一绝缘层111a可包括与第二绝缘层111b和第三绝缘层111c的绝缘材料不同的绝缘材料。例如,第一绝缘层111a可以为例如包括芯材料、填料和绝缘树脂的半固化片,第二绝缘层111b和第三绝缘层111c可以为ABF或包括填料和绝缘树脂的PID膜。然而,第一绝缘层111a以及第二绝缘层111b和第三绝缘层111c的材料不限于此。第一绝缘层111a的材料的强度可大于第二绝缘层111b和第三绝缘层111c的材料的强度,使得第一绝缘层111a提供刚性。贯穿第一绝缘层111a的第一过孔113a可具有比贯穿第二绝缘层111b的第二过孔113b的直径和贯穿第三绝缘层111c的第三过孔113c的直径大的直径。
芯构件110的第三布线层112c的下表面可设置在半导体芯片120的连接焊盘122的下表面之下的水平面上。连接构件140的重新分布层142与芯构件110的第三布线层112c之间的距离可小于连接构件140的重新分布层142与半导体芯片120的连接焊盘122之间的距离。第三布线层112c可以按照突出形式设置在第二绝缘层111b上,使得其与连接构件140接触。芯构件110的第一布线层112a和第二布线层112b可设置在均位于半导体芯片120的有效表面和无效表面之间的相应的水平面上。芯构件110可按照与半导体芯片120的厚度相对应的厚度形成。因此,形成在芯构件110中的第一布线层112a和第二布线层112b可设置在半导体芯片120的有效表面和无效表面之间的水平面上。
芯构件110的布线层112a、112b、112c和112d的厚度可大于连接构件140的重新分布层142的厚度。由于芯构件110可具有等于或大于半导体芯片120的厚度的厚度,因此布线层112a、112b、112c和112d可具有大尺寸。另一方面,为了纤薄化,连接构件140的重新分布层142可具有相对小的尺寸。
在各种实施例的上面的论述中,为了方便和可读性,仅省略了重复的描述。
如上所述,根据本公开的示例性实施例,扇出型半导体封装件包括设置在半导体芯片被包封的区域中的芯构件。芯构件可支撑扇出型半导体封装件并且包括布线。尽管包括芯构件,扇出型半导体封装件也可大体防止包封剂中的空隙的问题。
虽然上面已经示出并且描述了示例性实施例,但是对本领域技术人员将显而易见的是,在不脱离由所附的权利要求限定的本发明的范围的情况下,可做出修改和变形。
Claims (22)
1.一种扇出型半导体封装件,包括:
芯构件,具有通孔;
半导体芯片,设置在所述通孔中,并且包括具有连接焊盘的有效表面和与所述有效表面背对的无效表面;
包封剂,包封所述芯构件和所述半导体芯片的至少部分,并且填充所述通孔的至少部分;及
连接构件,位于所述芯构件和所述半导体芯片的所述有效表面上,并且包括电连接到所述半导体芯片的所述连接焊盘的重新分布层,
其中,在所述芯构件的设置有所述连接构件的下部中,所述芯构件包括从所述通孔的壁向外贯穿到所述芯构件的外侧表面的槽部。
2.如权利要求1所述的扇出型半导体封装件,其中,所述包封剂填充所述槽部的至少部分。
3.如权利要求1所述的扇出型半导体封装件,其中,所述槽部包括分别位于所述芯构件的所述下部的四个角中的第一槽部、第二槽部、第三槽部和第四槽部。
4.如权利要求3所述的扇出型半导体封装件,其中,
在所述芯构件的所述下部的外侧部中,所述芯构件包括沿着所述芯构件的边缘贯穿所述芯构件的所述下部的第五槽部,并且
其中,所述第一槽部至所述第四槽部连接到所述第五槽部。
5.如权利要求1所述的扇出型半导体封装件,其中,所述芯构件的所述通孔具有锥形形状。
6.如权利要求1所述的扇出型半导体封装件,其中,
所述半导体芯片包括位于所述有效表面上并且覆盖所述连接焊盘的至少部分的钝化层,并且
其中,所述包封剂填充所述钝化层和所述连接构件之间的空间的至少部分。
7.如权利要求1所述的扇出型半导体封装件,其中,
所述芯构件包括与所述连接构件接触的第一绝缘层、与所述连接构件接触并且嵌在所述第一绝缘层中的第一布线层以及设置在所述第一绝缘层的与所述第一绝缘层的嵌入有所述第一布线层的第一表面背对的第二表面上的第二布线层,并且
其中,所述第一布线层和所述第二布线层电连接到所述连接焊盘。
8.如权利要求7所述的扇出型半导体封装件,其中,
所述芯构件还包括位于所述第一绝缘层上并且覆盖所述第二布线层的第二绝缘层以及位于所述第二绝缘层上的第三布线层,并且
其中,所述第三布线层电连接到所述连接焊盘。
9.如权利要求8所述的扇出型半导体封装件,其中,所述槽部形成在所述第一绝缘层的下部中。
10.如权利要求8所述的扇出型半导体封装件,其中,所述第一绝缘层的下表面相对于所述第一布线层的下表面具有台阶。
11.如权利要求1所述的扇出型半导体封装件,其中,
所述芯构件包括第一绝缘层以及分别位于所述第一绝缘层的背对的表面上的第一布线层和第二布线层,并且
其中,所述第一布线层和所述第二布线层电连接到所述连接焊盘。
12.如权利要求11所述的扇出型半导体封装件,其中,
所述芯构件还包括位于所述第一绝缘层上并且覆盖所述第一布线层的第二绝缘层、位于所述第二绝缘层上的第三布线层、位于所述第一绝缘层上并且覆盖所述第二布线层的第三绝缘层以及位于所述第三绝缘层上的第四布线层,并且
其中,所述第三布线层和所述第四布线层电连接到所述连接焊盘。
13.如权利要求12所述的扇出型半导体封装件,其中,所述槽部形成在所述第二绝缘层的下部中。
14.如权利要求12所述的扇出型半导体封装件,其中,所述第一绝缘层具有比所述第二绝缘层的厚度和所述第三绝缘层的厚度大的厚度。
15.一种扇出型半导体封装件,包括:
连接构件;
电子组件,位于所述连接构件上;及
芯构件,位于所述连接构件上,包括通孔,并且所述电子组件位于所述通孔内,并且还包括沿着所述芯构件的下表面的一个或更多个槽,所述一个或更多个槽面对所述连接构件并且从所述通孔延伸到所述芯构件的外周方向上的外表面。
16.如权利要求15所述的扇出型半导体封装件,其中,所述芯构件还包括面对所述连接构件并且沿着所述芯构件的外周延伸的外周槽。
17.如权利要求15所述的扇出型半导体封装件,其中,在平面图中位于所述芯构件的面对所述连接构件的下侧上,所述芯构件的所述通孔具有下部区域,其中,所述下部区域比在平面图中位于所述芯构件的与所述下侧背对的上侧的上部区域小。
18.如权利要求15所述的扇出型半导体封装件,其中,
所述电子组件包括面对所述连接构件并且包括多个连接焊盘的有效表面,并且
所述连接构件包括电连接到所述电子组件的所述多个连接焊盘的重新分布层。
19.一种扇出型半导体封装件,包括:
连接构件,具有上表面和下表面并且包括重新分布层以及从所述下表面突出并且电连接到所述重新分布层的电连接结构;
半导体芯片,位于所述连接构件的所述上表面上方,包括位于所述半导体芯片的下表面上并面对所述连接构件的连接焊盘,所述连接焊盘电连接到所述连接构件的所述重新分布层;
芯构件,位于所述连接构件的所述上表面上方,包括容纳所述半导体芯片的通孔、电连接到所述连接构件的所述重新分布层的布线层以及面对所述连接构件并且从所述通孔的相应的内角延伸到所述芯构件的外周方向上的相应的外角的第一槽、第二槽、第三槽和第四槽;
包封剂,位于所述半导体芯片和所述芯构件上、位于所述半导体芯片和所述芯构件之间的所述通孔中以及位于所述第一槽至所述第四槽的至少部分中。
20.如权利要求19所述的扇出型半导体封装件,其中,
所述芯构件还包括外槽,所述外槽面对所述连接构件、沿着所述芯构件的外周延伸并且连接到所述第一槽至所述第四槽,并且
所述包封剂大体填充所述第一槽至所述第四槽,并且位于所述外槽的至少部分中。
21.如权利要求20所述的扇出型半导体封装件,其中,所述通孔具有锥形形状,并且所述通孔的面积朝向所述连接构件减小。
22.如权利要求19所述的扇出型半导体封装件,其中,所述芯构件包括多个绝缘层,所述多个绝缘层中的一个绝缘层比所述多个绝缘层中的任何其他绝缘层厚,并且包含与所述多个绝缘层中的任何其他绝缘层的材料不同的材料。
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TWI670807B (zh) | 2019-09-01 |
US20190088566A1 (en) | 2019-03-21 |
KR20190030972A (ko) | 2019-03-25 |
US10658260B2 (en) | 2020-05-19 |
US20190348339A1 (en) | 2019-11-14 |
CN109509726A (zh) | 2019-03-22 |
JP2019054226A (ja) | 2019-04-04 |
KR102380821B1 (ko) | 2022-03-31 |
TW201916269A (zh) | 2019-04-16 |
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